* [Intel-gfx] [PATCH 0/2] drm/i915/mtl: Disable MC6 for MTL A step @ 2023-03-08 10:21 Badal Nilawar 2023-03-08 10:21 ` [Intel-gfx] [PATCH 1/2] Revert "drm/i915/mtl: Add Wa_14017073508 for SAMedia" Badal Nilawar 2023-03-08 10:21 ` [Intel-gfx] [PATCH 2/2] drm/i915/mtl: Disable MC6 for MTL A step Badal Nilawar 0 siblings, 2 replies; 9+ messages in thread From: Badal Nilawar @ 2023-03-08 10:21 UTC (permalink / raw) To: intel-gfx Cc: hima.b.chilmakuru, rodrigo.vivi, gregory.f.germano, srikanth.nandamuri Disabling MC6 for A step as it is not feasible to extend Wa_14017073508 in forcewake path to cover all corner cases. Reverting the commit 8f70f1ec587da. Badal Nilawar (2): Revert "drm/i915/mtl: Add Wa_14017073508 for SAMedia" drm/i915/mtl: Disable MC6 for MTL A step drivers/gpu/drm/i915/gt/intel_gt_pm.c | 27 ----------------------- drivers/gpu/drm/i915/gt/intel_rc6.c | 8 +++++++ drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 13 +---------- drivers/gpu/drm/i915/i915_reg.h | 9 -------- 4 files changed, 9 insertions(+), 48 deletions(-) -- 2.25.1 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH 1/2] Revert "drm/i915/mtl: Add Wa_14017073508 for SAMedia" 2023-03-08 10:21 [Intel-gfx] [PATCH 0/2] drm/i915/mtl: Disable MC6 for MTL A step Badal Nilawar @ 2023-03-08 10:21 ` Badal Nilawar 2023-03-08 11:18 ` Jani Nikula 2023-03-08 10:21 ` [Intel-gfx] [PATCH 2/2] drm/i915/mtl: Disable MC6 for MTL A step Badal Nilawar 1 sibling, 1 reply; 9+ messages in thread From: Badal Nilawar @ 2023-03-08 10:21 UTC (permalink / raw) To: intel-gfx Cc: hima.b.chilmakuru, rodrigo.vivi, gregory.f.germano, srikanth.nandamuri This reverts commit 8f70f1ec587da0b0d52d768fd8c3defbc5e5b55c. Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 27 ----------------------- drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 13 +---------- drivers/gpu/drm/i915/i915_reg.h | 9 -------- 3 files changed, 1 insertion(+), 48 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c index 85ae7dc079f2..e02cb90723ae 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c @@ -20,31 +20,10 @@ #include "intel_rc6.h" #include "intel_rps.h" #include "intel_wakeref.h" -#include "intel_pcode.h" #include "pxp/intel_pxp_pm.h" #define I915_GT_SUSPEND_IDLE_TIMEOUT (HZ / 2) -static void mtl_media_busy(struct intel_gt *gt) -{ - /* Wa_14017073508: mtl */ - if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) && - gt->type == GT_MEDIA) - snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE, - PCODE_MBOX_GT_STATE_MEDIA_BUSY, - PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0); -} - -static void mtl_media_idle(struct intel_gt *gt) -{ - /* Wa_14017073508: mtl */ - if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) && - gt->type == GT_MEDIA) - snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE, - PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY, - PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0); -} - static void user_forcewake(struct intel_gt *gt, bool suspend) { int count = atomic_read(>->user_wakeref); @@ -92,9 +71,6 @@ static int __gt_unpark(struct intel_wakeref *wf) GT_TRACE(gt, "\n"); - /* Wa_14017073508: mtl */ - mtl_media_busy(gt); - /* * It seems that the DMC likes to transition between the DC states a lot * when there are no connected displays (no active power domains) during @@ -144,9 +120,6 @@ static int __gt_park(struct intel_wakeref *wf) GEM_BUG_ON(!wakeref); intel_display_power_put_async(i915, POWER_DOMAIN_GT_IRQ, wakeref); - /* Wa_14017073508: mtl */ - mtl_media_idle(gt); - return 0; } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c index fcf51614f9a4..1adec6de223c 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c @@ -12,20 +12,9 @@ static bool __guc_rc_supported(struct intel_guc *guc) { - struct intel_gt *gt = guc_to_gt(guc); - - /* - * Wa_14017073508: mtl - * Do not enable gucrc to avoid additional interrupts which - * may disrupt pcode wa. - */ - if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) && - gt->type == GT_MEDIA) - return false; - /* GuC RC is unavailable for pre-Gen12 */ return guc->submission_supported && - GRAPHICS_VER(gt->i915) >= 12; + GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12; } static bool __guc_rc_selected(struct intel_guc *guc) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f2ce4bde6a68..b177cdeee1ec 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6469,15 +6469,6 @@ /* XEHP_PCODE_FREQUENCY_CONFIG param2 */ #define PCODE_MBOX_DOMAIN_NONE 0x0 #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3 - -/* Wa_14017210380: mtl */ -#define PCODE_MBOX_GT_STATE 0x50 -/* sub-commands (param1) */ -#define PCODE_MBOX_GT_STATE_MEDIA_BUSY 0x1 -#define PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY 0x2 -/* param2 */ -#define PCODE_MBOX_GT_STATE_DOMAIN_MEDIA 0x1 - #define GEN6_PCODE_DATA _MMIO(0x138128) #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 -- 2.25.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] Revert "drm/i915/mtl: Add Wa_14017073508 for SAMedia" 2023-03-08 10:21 ` [Intel-gfx] [PATCH 1/2] Revert "drm/i915/mtl: Add Wa_14017073508 for SAMedia" Badal Nilawar @ 2023-03-08 11:18 ` Jani Nikula 2023-03-08 15:25 ` Nilawar, Badal 0 siblings, 1 reply; 9+ messages in thread From: Jani Nikula @ 2023-03-08 11:18 UTC (permalink / raw) To: Badal Nilawar, intel-gfx Cc: gregory.f.germano, hima.b.chilmakuru, srikanth.nandamuri, rodrigo.vivi On Wed, 08 Mar 2023, Badal Nilawar <badal.nilawar@intel.com> wrote: > This reverts commit 8f70f1ec587da0b0d52d768fd8c3defbc5e5b55c. Reverts need a commit message too. The why. The cover letter is not recorded in git history. BR, Jani. > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_pm.c | 27 ----------------------- > drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 13 +---------- > drivers/gpu/drm/i915/i915_reg.h | 9 -------- > 3 files changed, 1 insertion(+), 48 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c > index 85ae7dc079f2..e02cb90723ae 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c > @@ -20,31 +20,10 @@ > #include "intel_rc6.h" > #include "intel_rps.h" > #include "intel_wakeref.h" > -#include "intel_pcode.h" > #include "pxp/intel_pxp_pm.h" > > #define I915_GT_SUSPEND_IDLE_TIMEOUT (HZ / 2) > > -static void mtl_media_busy(struct intel_gt *gt) > -{ > - /* Wa_14017073508: mtl */ > - if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) && > - gt->type == GT_MEDIA) > - snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE, > - PCODE_MBOX_GT_STATE_MEDIA_BUSY, > - PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0); > -} > - > -static void mtl_media_idle(struct intel_gt *gt) > -{ > - /* Wa_14017073508: mtl */ > - if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) && > - gt->type == GT_MEDIA) > - snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE, > - PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY, > - PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0); > -} > - > static void user_forcewake(struct intel_gt *gt, bool suspend) > { > int count = atomic_read(>->user_wakeref); > @@ -92,9 +71,6 @@ static int __gt_unpark(struct intel_wakeref *wf) > > GT_TRACE(gt, "\n"); > > - /* Wa_14017073508: mtl */ > - mtl_media_busy(gt); > - > /* > * It seems that the DMC likes to transition between the DC states a lot > * when there are no connected displays (no active power domains) during > @@ -144,9 +120,6 @@ static int __gt_park(struct intel_wakeref *wf) > GEM_BUG_ON(!wakeref); > intel_display_power_put_async(i915, POWER_DOMAIN_GT_IRQ, wakeref); > > - /* Wa_14017073508: mtl */ > - mtl_media_idle(gt); > - > return 0; > } > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c > index fcf51614f9a4..1adec6de223c 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c > @@ -12,20 +12,9 @@ > > static bool __guc_rc_supported(struct intel_guc *guc) > { > - struct intel_gt *gt = guc_to_gt(guc); > - > - /* > - * Wa_14017073508: mtl > - * Do not enable gucrc to avoid additional interrupts which > - * may disrupt pcode wa. > - */ > - if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) && > - gt->type == GT_MEDIA) > - return false; > - > /* GuC RC is unavailable for pre-Gen12 */ > return guc->submission_supported && > - GRAPHICS_VER(gt->i915) >= 12; > + GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12; > } > > static bool __guc_rc_selected(struct intel_guc *guc) > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index f2ce4bde6a68..b177cdeee1ec 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6469,15 +6469,6 @@ > /* XEHP_PCODE_FREQUENCY_CONFIG param2 */ > #define PCODE_MBOX_DOMAIN_NONE 0x0 > #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3 > - > -/* Wa_14017210380: mtl */ > -#define PCODE_MBOX_GT_STATE 0x50 > -/* sub-commands (param1) */ > -#define PCODE_MBOX_GT_STATE_MEDIA_BUSY 0x1 > -#define PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY 0x2 > -/* param2 */ > -#define PCODE_MBOX_GT_STATE_DOMAIN_MEDIA 0x1 > - > #define GEN6_PCODE_DATA _MMIO(0x138128) > #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 > #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] Revert "drm/i915/mtl: Add Wa_14017073508 for SAMedia" 2023-03-08 11:18 ` Jani Nikula @ 2023-03-08 15:25 ` Nilawar, Badal 2023-03-09 5:38 ` Nilawar, Badal 0 siblings, 1 reply; 9+ messages in thread From: Nilawar, Badal @ 2023-03-08 15:25 UTC (permalink / raw) To: Jani Nikula, intel-gfx Cc: gregory.f.germano, hima.b.chilmakuru, srikanth.nandamuri, rodrigo.vivi Hi Jani, On 08-03-2023 16:48, Jani Nikula wrote: > On Wed, 08 Mar 2023, Badal Nilawar <badal.nilawar@intel.com> wrote: >> This reverts commit 8f70f1ec587da0b0d52d768fd8c3defbc5e5b55c. > > Reverts need a commit message too. The why. The cover letter is not > recorded in git history. I will add commit message. Regards, Badal > > BR, > Jani. > >> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> >> --- >> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 27 ----------------------- >> drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 13 +---------- >> drivers/gpu/drm/i915/i915_reg.h | 9 -------- >> 3 files changed, 1 insertion(+), 48 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c >> index 85ae7dc079f2..e02cb90723ae 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c >> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c >> @@ -20,31 +20,10 @@ >> #include "intel_rc6.h" >> #include "intel_rps.h" >> #include "intel_wakeref.h" >> -#include "intel_pcode.h" >> #include "pxp/intel_pxp_pm.h" >> >> #define I915_GT_SUSPEND_IDLE_TIMEOUT (HZ / 2) >> >> -static void mtl_media_busy(struct intel_gt *gt) >> -{ >> - /* Wa_14017073508: mtl */ >> - if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) && >> - gt->type == GT_MEDIA) >> - snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE, >> - PCODE_MBOX_GT_STATE_MEDIA_BUSY, >> - PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0); >> -} >> - >> -static void mtl_media_idle(struct intel_gt *gt) >> -{ >> - /* Wa_14017073508: mtl */ >> - if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) && >> - gt->type == GT_MEDIA) >> - snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE, >> - PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY, >> - PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0); >> -} >> - >> static void user_forcewake(struct intel_gt *gt, bool suspend) >> { >> int count = atomic_read(>->user_wakeref); >> @@ -92,9 +71,6 @@ static int __gt_unpark(struct intel_wakeref *wf) >> >> GT_TRACE(gt, "\n"); >> >> - /* Wa_14017073508: mtl */ >> - mtl_media_busy(gt); >> - >> /* >> * It seems that the DMC likes to transition between the DC states a lot >> * when there are no connected displays (no active power domains) during >> @@ -144,9 +120,6 @@ static int __gt_park(struct intel_wakeref *wf) >> GEM_BUG_ON(!wakeref); >> intel_display_power_put_async(i915, POWER_DOMAIN_GT_IRQ, wakeref); >> >> - /* Wa_14017073508: mtl */ >> - mtl_media_idle(gt); >> - >> return 0; >> } >> >> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c >> index fcf51614f9a4..1adec6de223c 100644 >> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c >> @@ -12,20 +12,9 @@ >> >> static bool __guc_rc_supported(struct intel_guc *guc) >> { >> - struct intel_gt *gt = guc_to_gt(guc); >> - >> - /* >> - * Wa_14017073508: mtl >> - * Do not enable gucrc to avoid additional interrupts which >> - * may disrupt pcode wa. >> - */ >> - if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) && >> - gt->type == GT_MEDIA) >> - return false; >> - >> /* GuC RC is unavailable for pre-Gen12 */ >> return guc->submission_supported && >> - GRAPHICS_VER(gt->i915) >= 12; >> + GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12; >> } >> >> static bool __guc_rc_selected(struct intel_guc *guc) >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index f2ce4bde6a68..b177cdeee1ec 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -6469,15 +6469,6 @@ >> /* XEHP_PCODE_FREQUENCY_CONFIG param2 */ >> #define PCODE_MBOX_DOMAIN_NONE 0x0 >> #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3 >> - >> -/* Wa_14017210380: mtl */ >> -#define PCODE_MBOX_GT_STATE 0x50 >> -/* sub-commands (param1) */ >> -#define PCODE_MBOX_GT_STATE_MEDIA_BUSY 0x1 >> -#define PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY 0x2 >> -/* param2 */ >> -#define PCODE_MBOX_GT_STATE_DOMAIN_MEDIA 0x1 >> - >> #define GEN6_PCODE_DATA _MMIO(0x138128) >> #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 >> #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] Revert "drm/i915/mtl: Add Wa_14017073508 for SAMedia" 2023-03-08 15:25 ` Nilawar, Badal @ 2023-03-09 5:38 ` Nilawar, Badal 2023-03-09 14:05 ` Rodrigo Vivi 0 siblings, 1 reply; 9+ messages in thread From: Nilawar, Badal @ 2023-03-09 5:38 UTC (permalink / raw) To: Jani Nikula, intel-gfx, Rodrigo Vivi Cc: gregory.f.germano, hima.b.chilmakuru, srikanth.nandamuri On 08-03-2023 20:55, Nilawar, Badal wrote: > Hi Jani, > > On 08-03-2023 16:48, Jani Nikula wrote: >> On Wed, 08 Mar 2023, Badal Nilawar <badal.nilawar@intel.com> wrote: >>> This reverts commit 8f70f1ec587da0b0d52d768fd8c3defbc5e5b55c. >> >> Reverts need a commit message too. The why. The cover letter is not >> recorded in git history. > > I will add commit message. Is it ok if I squash both the commits? > Regards, > Badal >> >> BR, >> Jani. >> >>> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> >>> --- >>> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 27 ----------------------- >>> drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 13 +---------- >>> drivers/gpu/drm/i915/i915_reg.h | 9 -------- >>> 3 files changed, 1 insertion(+), 48 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c >>> b/drivers/gpu/drm/i915/gt/intel_gt_pm.c >>> index 85ae7dc079f2..e02cb90723ae 100644 >>> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c >>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c >>> @@ -20,31 +20,10 @@ >>> #include "intel_rc6.h" >>> #include "intel_rps.h" >>> #include "intel_wakeref.h" >>> -#include "intel_pcode.h" >>> #include "pxp/intel_pxp_pm.h" >>> #define I915_GT_SUSPEND_IDLE_TIMEOUT (HZ / 2) >>> -static void mtl_media_busy(struct intel_gt *gt) >>> -{ >>> - /* Wa_14017073508: mtl */ >>> - if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) && >>> - gt->type == GT_MEDIA) >>> - snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE, >>> - PCODE_MBOX_GT_STATE_MEDIA_BUSY, >>> - PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0); >>> -} >>> - >>> -static void mtl_media_idle(struct intel_gt *gt) >>> -{ >>> - /* Wa_14017073508: mtl */ >>> - if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) && >>> - gt->type == GT_MEDIA) >>> - snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE, >>> - PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY, >>> - PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0); >>> -} >>> - >>> static void user_forcewake(struct intel_gt *gt, bool suspend) >>> { >>> int count = atomic_read(>->user_wakeref); >>> @@ -92,9 +71,6 @@ static int __gt_unpark(struct intel_wakeref *wf) >>> GT_TRACE(gt, "\n"); >>> - /* Wa_14017073508: mtl */ >>> - mtl_media_busy(gt); >>> - >>> /* >>> * It seems that the DMC likes to transition between the DC >>> states a lot >>> * when there are no connected displays (no active power >>> domains) during >>> @@ -144,9 +120,6 @@ static int __gt_park(struct intel_wakeref *wf) >>> GEM_BUG_ON(!wakeref); >>> intel_display_power_put_async(i915, POWER_DOMAIN_GT_IRQ, wakeref); >>> - /* Wa_14017073508: mtl */ >>> - mtl_media_idle(gt); >>> - >>> return 0; >>> } >>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c >>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c >>> index fcf51614f9a4..1adec6de223c 100644 >>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c >>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c >>> @@ -12,20 +12,9 @@ >>> static bool __guc_rc_supported(struct intel_guc *guc) >>> { >>> - struct intel_gt *gt = guc_to_gt(guc); >>> - >>> - /* >>> - * Wa_14017073508: mtl >>> - * Do not enable gucrc to avoid additional interrupts which >>> - * may disrupt pcode wa. >>> - */ >>> - if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) && >>> - gt->type == GT_MEDIA) >>> - return false; >>> - >>> /* GuC RC is unavailable for pre-Gen12 */ >>> return guc->submission_supported && >>> - GRAPHICS_VER(gt->i915) >= 12; >>> + GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12; >>> } >>> static bool __guc_rc_selected(struct intel_guc *guc) >>> diff --git a/drivers/gpu/drm/i915/i915_reg.h >>> b/drivers/gpu/drm/i915/i915_reg.h >>> index f2ce4bde6a68..b177cdeee1ec 100644 >>> --- a/drivers/gpu/drm/i915/i915_reg.h >>> +++ b/drivers/gpu/drm/i915/i915_reg.h >>> @@ -6469,15 +6469,6 @@ >>> /* XEHP_PCODE_FREQUENCY_CONFIG param2 */ >>> #define PCODE_MBOX_DOMAIN_NONE 0x0 >>> #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3 >>> - >>> -/* Wa_14017210380: mtl */ >>> -#define PCODE_MBOX_GT_STATE 0x50 >>> -/* sub-commands (param1) */ >>> -#define PCODE_MBOX_GT_STATE_MEDIA_BUSY 0x1 >>> -#define PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY 0x2 >>> -/* param2 */ >>> -#define PCODE_MBOX_GT_STATE_DOMAIN_MEDIA 0x1 >>> - >>> #define GEN6_PCODE_DATA _MMIO(0x138128) >>> #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 >>> #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 >> ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] Revert "drm/i915/mtl: Add Wa_14017073508 for SAMedia" 2023-03-09 5:38 ` Nilawar, Badal @ 2023-03-09 14:05 ` Rodrigo Vivi 0 siblings, 0 replies; 9+ messages in thread From: Rodrigo Vivi @ 2023-03-09 14:05 UTC (permalink / raw) To: Nilawar, Badal Cc: intel-gfx, gregory.f.germano, srikanth.nandamuri, hima.b.chilmakuru On Thu, Mar 09, 2023 at 11:08:09AM +0530, Nilawar, Badal wrote: > > > On 08-03-2023 20:55, Nilawar, Badal wrote: > > Hi Jani, > > > > On 08-03-2023 16:48, Jani Nikula wrote: > > > On Wed, 08 Mar 2023, Badal Nilawar <badal.nilawar@intel.com> wrote: > > > > This reverts commit 8f70f1ec587da0b0d52d768fd8c3defbc5e5b55c. > > > > > > Reverts need a commit message too. The why. The cover letter is not > > > recorded in git history. > > > > I will add commit message. > > Is it ok if I squash both the commits? yes, it is. just don't mark as revert and make sure to add the original one as a Fixes tag. Easier to backport actually. > > > Regards, > > Badal > > > > > > BR, > > > Jani. > > > > > > > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/gt/intel_gt_pm.c | 27 ----------------------- > > > > drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 13 +---------- > > > > drivers/gpu/drm/i915/i915_reg.h | 9 -------- > > > > 3 files changed, 1 insertion(+), 48 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c > > > > b/drivers/gpu/drm/i915/gt/intel_gt_pm.c > > > > index 85ae7dc079f2..e02cb90723ae 100644 > > > > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c > > > > @@ -20,31 +20,10 @@ > > > > #include "intel_rc6.h" > > > > #include "intel_rps.h" > > > > #include "intel_wakeref.h" > > > > -#include "intel_pcode.h" > > > > #include "pxp/intel_pxp_pm.h" > > > > #define I915_GT_SUSPEND_IDLE_TIMEOUT (HZ / 2) > > > > -static void mtl_media_busy(struct intel_gt *gt) > > > > -{ > > > > - /* Wa_14017073508: mtl */ > > > > - if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) && > > > > - gt->type == GT_MEDIA) > > > > - snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE, > > > > - PCODE_MBOX_GT_STATE_MEDIA_BUSY, > > > > - PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0); > > > > -} > > > > - > > > > -static void mtl_media_idle(struct intel_gt *gt) > > > > -{ > > > > - /* Wa_14017073508: mtl */ > > > > - if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) && > > > > - gt->type == GT_MEDIA) > > > > - snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE, > > > > - PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY, > > > > - PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0); > > > > -} > > > > - > > > > static void user_forcewake(struct intel_gt *gt, bool suspend) > > > > { > > > > int count = atomic_read(>->user_wakeref); > > > > @@ -92,9 +71,6 @@ static int __gt_unpark(struct intel_wakeref *wf) > > > > GT_TRACE(gt, "\n"); > > > > - /* Wa_14017073508: mtl */ > > > > - mtl_media_busy(gt); > > > > - > > > > /* > > > > * It seems that the DMC likes to transition between the > > > > DC states a lot > > > > * when there are no connected displays (no active power > > > > domains) during > > > > @@ -144,9 +120,6 @@ static int __gt_park(struct intel_wakeref *wf) > > > > GEM_BUG_ON(!wakeref); > > > > intel_display_power_put_async(i915, POWER_DOMAIN_GT_IRQ, wakeref); > > > > - /* Wa_14017073508: mtl */ > > > > - mtl_media_idle(gt); > > > > - > > > > return 0; > > > > } > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c > > > > b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c > > > > index fcf51614f9a4..1adec6de223c 100644 > > > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c > > > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c > > > > @@ -12,20 +12,9 @@ > > > > static bool __guc_rc_supported(struct intel_guc *guc) > > > > { > > > > - struct intel_gt *gt = guc_to_gt(guc); > > > > - > > > > - /* > > > > - * Wa_14017073508: mtl > > > > - * Do not enable gucrc to avoid additional interrupts which > > > > - * may disrupt pcode wa. > > > > - */ > > > > - if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) && > > > > - gt->type == GT_MEDIA) > > > > - return false; > > > > - > > > > /* GuC RC is unavailable for pre-Gen12 */ > > > > return guc->submission_supported && > > > > - GRAPHICS_VER(gt->i915) >= 12; > > > > + GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12; > > > > } > > > > static bool __guc_rc_selected(struct intel_guc *guc) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > > > b/drivers/gpu/drm/i915/i915_reg.h > > > > index f2ce4bde6a68..b177cdeee1ec 100644 > > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > > @@ -6469,15 +6469,6 @@ > > > > /* XEHP_PCODE_FREQUENCY_CONFIG param2 */ > > > > #define PCODE_MBOX_DOMAIN_NONE 0x0 > > > > #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3 > > > > - > > > > -/* Wa_14017210380: mtl */ > > > > -#define PCODE_MBOX_GT_STATE 0x50 > > > > -/* sub-commands (param1) */ > > > > -#define PCODE_MBOX_GT_STATE_MEDIA_BUSY 0x1 > > > > -#define PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY 0x2 > > > > -/* param2 */ > > > > -#define PCODE_MBOX_GT_STATE_DOMAIN_MEDIA 0x1 > > > > - > > > > #define GEN6_PCODE_DATA _MMIO(0x138128) > > > > #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 > > > > #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 > > > ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/mtl: Disable MC6 for MTL A step 2023-03-08 10:21 [Intel-gfx] [PATCH 0/2] drm/i915/mtl: Disable MC6 for MTL A step Badal Nilawar 2023-03-08 10:21 ` [Intel-gfx] [PATCH 1/2] Revert "drm/i915/mtl: Add Wa_14017073508 for SAMedia" Badal Nilawar @ 2023-03-08 10:21 ` Badal Nilawar 2023-03-08 13:29 ` Rodrigo Vivi 1 sibling, 1 reply; 9+ messages in thread From: Badal Nilawar @ 2023-03-08 10:21 UTC (permalink / raw) To: intel-gfx Cc: hima.b.chilmakuru, rodrigo.vivi, gregory.f.germano, srikanth.nandamuri The Wa_14017073508 require to send Media Busy/Idle mailbox while accessing Media tile. As of now it is getting handled while __gt_unpark, __gt_park. But there are various corner cases where forcewakes are taken without __gt_unpark i.e. without sending Busy Mailbox especially during register reads. Forcewakes are taken without busy mailbox leads to GPU HANG. So bringing mailbox calls under forcewake calls are no feasible option as forcewake calls are atomic and mailbox calls are blocking. The issue already fixed in B step so disabling MC6 on A step and reverting previous commits which handles Wa_14017073508 Fixes: 8f70f1ec587d ("drm/i915/mtl: Add Wa_14017073508 for SAMedia") Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> --- drivers/gpu/drm/i915/gt/intel_rc6.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 5c91622dfca4..f4150f61f39c 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -486,6 +486,7 @@ static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6) static bool rc6_supported(struct intel_rc6 *rc6) { struct drm_i915_private *i915 = rc6_to_i915(rc6); + struct intel_gt *gt = rc6_to_gt(rc6); if (!HAS_RC6(i915)) return false; @@ -502,6 +503,13 @@ static bool rc6_supported(struct intel_rc6 *rc6) return false; } + if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) && + gt->type == GT_MEDIA) { + drm_notice(&i915->drm, + "Media RC6 disabled on A step\n"); + return false; + } + return true; } -- 2.25.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/mtl: Disable MC6 for MTL A step 2023-03-08 10:21 ` [Intel-gfx] [PATCH 2/2] drm/i915/mtl: Disable MC6 for MTL A step Badal Nilawar @ 2023-03-08 13:29 ` Rodrigo Vivi 2023-03-08 15:24 ` Nilawar, Badal 0 siblings, 1 reply; 9+ messages in thread From: Rodrigo Vivi @ 2023-03-08 13:29 UTC (permalink / raw) To: Badal Nilawar Cc: gregory.f.germano, intel-gfx, srikanth.nandamuri, hima.b.chilmakuru On Wed, Mar 08, 2023 at 03:51:09PM +0530, Badal Nilawar wrote: > The Wa_14017073508 require to send Media Busy/Idle mailbox while > accessing Media tile. As of now it is getting handled while __gt_unpark, > __gt_park. But there are various corner cases where forcewakes are taken > without __gt_unpark i.e. without sending Busy Mailbox especially during > register reads. Forcewakes are taken without busy mailbox leads to > GPU HANG. So bringing mailbox calls under forcewake calls are no feasible > option as forcewake calls are atomic and mailbox calls are blocking. > The issue already fixed in B step so disabling MC6 on A step and > reverting previous commits which handles Wa_14017073508 > > Fixes: 8f70f1ec587d ("drm/i915/mtl: Add Wa_14017073508 for SAMedia") > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> This patch should probably come before the revert itself. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_rc6.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c > index 5c91622dfca4..f4150f61f39c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rc6.c > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c > @@ -486,6 +486,7 @@ static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6) > static bool rc6_supported(struct intel_rc6 *rc6) > { > struct drm_i915_private *i915 = rc6_to_i915(rc6); > + struct intel_gt *gt = rc6_to_gt(rc6); > > if (!HAS_RC6(i915)) > return false; > @@ -502,6 +503,13 @@ static bool rc6_supported(struct intel_rc6 *rc6) > return false; > } > > + if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) && > + gt->type == GT_MEDIA) { > + drm_notice(&i915->drm, > + "Media RC6 disabled on A step\n"); > + return false; > + } > + > return true; > } > > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/mtl: Disable MC6 for MTL A step 2023-03-08 13:29 ` Rodrigo Vivi @ 2023-03-08 15:24 ` Nilawar, Badal 0 siblings, 0 replies; 9+ messages in thread From: Nilawar, Badal @ 2023-03-08 15:24 UTC (permalink / raw) To: Rodrigo Vivi Cc: gregory.f.germano, intel-gfx, srikanth.nandamuri, hima.b.chilmakuru Hi Rodrigo, On 08-03-2023 18:59, Rodrigo Vivi wrote: > On Wed, Mar 08, 2023 at 03:51:09PM +0530, Badal Nilawar wrote: >> The Wa_14017073508 require to send Media Busy/Idle mailbox while >> accessing Media tile. As of now it is getting handled while __gt_unpark, >> __gt_park. But there are various corner cases where forcewakes are taken >> without __gt_unpark i.e. without sending Busy Mailbox especially during >> register reads. Forcewakes are taken without busy mailbox leads to >> GPU HANG. So bringing mailbox calls under forcewake calls are no feasible >> option as forcewake calls are atomic and mailbox calls are blocking. >> The issue already fixed in B step so disabling MC6 on A step and >> reverting previous commits which handles Wa_14017073508 >> >> Fixes: 8f70f1ec587d ("drm/i915/mtl: Add Wa_14017073508 for SAMedia") >> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> >> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> > > This patch should probably come before the revert itself. > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Thanks for RB. I will put this patch before revert. Regards, Badal Nilawar > >> --- >> drivers/gpu/drm/i915/gt/intel_rc6.c | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c >> index 5c91622dfca4..f4150f61f39c 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c >> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c >> @@ -486,6 +486,7 @@ static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6) >> static bool rc6_supported(struct intel_rc6 *rc6) >> { >> struct drm_i915_private *i915 = rc6_to_i915(rc6); >> + struct intel_gt *gt = rc6_to_gt(rc6); >> >> if (!HAS_RC6(i915)) >> return false; >> @@ -502,6 +503,13 @@ static bool rc6_supported(struct intel_rc6 *rc6) >> return false; >> } >> >> + if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) && >> + gt->type == GT_MEDIA) { >> + drm_notice(&i915->drm, >> + "Media RC6 disabled on A step\n"); >> + return false; >> + } >> + >> return true; >> } >> >> -- >> 2.25.1 >> ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-03-09 14:05 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-03-08 10:21 [Intel-gfx] [PATCH 0/2] drm/i915/mtl: Disable MC6 for MTL A step Badal Nilawar 2023-03-08 10:21 ` [Intel-gfx] [PATCH 1/2] Revert "drm/i915/mtl: Add Wa_14017073508 for SAMedia" Badal Nilawar 2023-03-08 11:18 ` Jani Nikula 2023-03-08 15:25 ` Nilawar, Badal 2023-03-09 5:38 ` Nilawar, Badal 2023-03-09 14:05 ` Rodrigo Vivi 2023-03-08 10:21 ` [Intel-gfx] [PATCH 2/2] drm/i915/mtl: Disable MC6 for MTL A step Badal Nilawar 2023-03-08 13:29 ` Rodrigo Vivi 2023-03-08 15:24 ` Nilawar, Badal
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox