[Intel-gfx] [PATCH 0/4] Misc GuC CT improvements

[Intel-gfx] [PATCH 0/4] Misc GuC CT improvements

[Michal Wajdeczko]

Michal Wajdeczko (4):
  drm/i915/guc: Simpler CT message size calculation
  drm/i915/guc: Introduce CT_ERROR
  drm/i915/guc: Update CTB helpers to use CT_ERROR
  drm/i915/guc: Use correct name for last CT fence

 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 113 +++++++++++++---------
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h |   2 +-
 2 files changed, 69 insertions(+), 46 deletions(-)

-- 
2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 1/4] drm/i915/guc: Simpler CT message size calculation

[Michal Wajdeczko]

We need CT message size in bytes so just use that in helper var.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index c6f971a049f9..4aa07a53a9cf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -627,7 +627,7 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
 {
 	u32 header = msg[0];
 	u32 len = ct_header_get_len(header);
-	u32 msglen = len + 1; /* total message length including header */
+	u32 msgsize = (len + 1) * sizeof(u32); /* msg size in bytes w/header */
 	u32 fence;
 	u32 status;
 	u32 datalen;
@@ -639,7 +639,7 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
 
 	/* Response payload shall at least include fence and status */
 	if (unlikely(len < 2)) {
-		DRM_ERROR("CT: corrupted response %*ph\n", 4 * msglen, msg);
+		DRM_ERROR("CT: corrupted response %*ph\n", msgsize, msg);
 		return -EPROTO;
 	}
 
@@ -649,7 +649,7 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
 
 	/* Format of the status follows RESPONSE message */
 	if (unlikely(!INTEL_GUC_MSG_IS_RESPONSE(status))) {
-		DRM_ERROR("CT: corrupted response %*ph\n", 4 * msglen, msg);
+		DRM_ERROR("CT: corrupted response %*ph\n", msgsize, msg);
 		return -EPROTO;
 	}
 
@@ -664,7 +664,7 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
 		}
 		if (unlikely(datalen > req->response_len)) {
 			DRM_ERROR("CT: response %u too long %*ph\n",
-				  req->fence, 4 * msglen, msg);
+				  req->fence, msgsize, msg);
 			datalen = 0;
 		}
 		if (datalen)
@@ -677,7 +677,7 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
 	spin_unlock(&ct->requests.lock);
 
 	if (!found)
-		DRM_ERROR("CT: unsolicited response %*ph\n", 4 * msglen, msg);
+		DRM_ERROR("CT: unsolicited response %*ph\n", msgsize, msg);
 	return 0;
 }
 
@@ -767,18 +767,18 @@ static int ct_handle_request(struct intel_guc_ct *ct, const u32 *msg)
 {
 	u32 header = msg[0];
 	u32 len = ct_header_get_len(header);
-	u32 msglen = len + 1; /* total message length including header */
+	u32 msgsize = (len + 1) * sizeof(u32); /* msg size in bytes w/header */
 	struct ct_incoming_request *request;
 	unsigned long flags;
 
 	GEM_BUG_ON(ct_header_is_response(header));
 
-	request = kmalloc(sizeof(*request) + 4 * msglen, GFP_ATOMIC);
+	request = kmalloc(sizeof(*request) + msgsize, GFP_ATOMIC);
 	if (unlikely(!request)) {
-		DRM_ERROR("CT: dropping request %*ph\n", 4 * msglen, msg);
+		DRM_ERROR("CT: dropping request %*ph\n", msgsize, msg);
 		return 0; /* XXX: -ENOMEM ? */
 	}
-	memcpy(request->msg, msg, 4 * msglen);
+	memcpy(request->msg, msg, msgsize);
 
 	spin_lock_irqsave(&ct->requests.lock, flags);
 	list_add_tail(&request->link, &ct->requests.incoming);
-- 
2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/4] drm/i915/guc: Simpler CT message size calculation

[Daniele Ceraolo Spurio]

On 1/11/2020 3:11 PM, Michal Wajdeczko wrote:
> We need CT message size in bytes so just use that in helper var.
>
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

> ---
>   drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 18 +++++++++---------
>   1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index c6f971a049f9..4aa07a53a9cf 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -627,7 +627,7 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
>   {
>   	u32 header = msg[0];
>   	u32 len = ct_header_get_len(header);
> -	u32 msglen = len + 1; /* total message length including header */
> +	u32 msgsize = (len + 1) * sizeof(u32); /* msg size in bytes w/header */
>   	u32 fence;
>   	u32 status;
>   	u32 datalen;
> @@ -639,7 +639,7 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
>   
>   	/* Response payload shall at least include fence and status */
>   	if (unlikely(len < 2)) {
> -		DRM_ERROR("CT: corrupted response %*ph\n", 4 * msglen, msg);
> +		DRM_ERROR("CT: corrupted response %*ph\n", msgsize, msg);
>   		return -EPROTO;
>   	}
>   
> @@ -649,7 +649,7 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
>   
>   	/* Format of the status follows RESPONSE message */
>   	if (unlikely(!INTEL_GUC_MSG_IS_RESPONSE(status))) {
> -		DRM_ERROR("CT: corrupted response %*ph\n", 4 * msglen, msg);
> +		DRM_ERROR("CT: corrupted response %*ph\n", msgsize, msg);
>   		return -EPROTO;
>   	}
>   
> @@ -664,7 +664,7 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
>   		}
>   		if (unlikely(datalen > req->response_len)) {
>   			DRM_ERROR("CT: response %u too long %*ph\n",
> -				  req->fence, 4 * msglen, msg);
> +				  req->fence, msgsize, msg);
>   			datalen = 0;
>   		}
>   		if (datalen)
> @@ -677,7 +677,7 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
>   	spin_unlock(&ct->requests.lock);
>   
>   	if (!found)
> -		DRM_ERROR("CT: unsolicited response %*ph\n", 4 * msglen, msg);
> +		DRM_ERROR("CT: unsolicited response %*ph\n", msgsize, msg);
>   	return 0;
>   }
>   
> @@ -767,18 +767,18 @@ static int ct_handle_request(struct intel_guc_ct *ct, const u32 *msg)
>   {
>   	u32 header = msg[0];
>   	u32 len = ct_header_get_len(header);
> -	u32 msglen = len + 1; /* total message length including header */
> +	u32 msgsize = (len + 1) * sizeof(u32); /* msg size in bytes w/header */
>   	struct ct_incoming_request *request;
>   	unsigned long flags;
>   
>   	GEM_BUG_ON(ct_header_is_response(header));
>   
> -	request = kmalloc(sizeof(*request) + 4 * msglen, GFP_ATOMIC);
> +	request = kmalloc(sizeof(*request) + msgsize, GFP_ATOMIC);
>   	if (unlikely(!request)) {
> -		DRM_ERROR("CT: dropping request %*ph\n", 4 * msglen, msg);
> +		DRM_ERROR("CT: dropping request %*ph\n", msgsize, msg);
>   		return 0; /* XXX: -ENOMEM ? */
>   	}
> -	memcpy(request->msg, msg, 4 * msglen);
> +	memcpy(request->msg, msg, msgsize);
>   
>   	spin_lock_irqsave(&ct->requests.lock, flags);
>   	list_add_tail(&request->link, &ct->requests.incoming);

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 2/4] drm/i915/guc: Introduce CT_ERROR

[Michal Wajdeczko]

We should start using dev variants of error logging and
to simplify that introduce helper macro that will do any
necessary conversions to obtain pointer to device struct.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 46 ++++++++++++++++-------
 1 file changed, 32 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 4aa07a53a9cf..eb123543392a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -5,7 +5,10 @@
 
 #include "i915_drv.h"
 #include "intel_guc_ct.h"
+#include "gt/intel_gt.h"
 
+#define CT_ERROR(_ct, _fmt, ...) \
+	DRM_DEV_ERROR(ct_to_dev(_ct), "CT: " _fmt, ##__VA_ARGS__)
 #ifdef CONFIG_DRM_I915_DEBUG_GUC
 #define CT_DEBUG_DRIVER(...)	DRM_DEBUG_DRIVER(__VA_ARGS__)
 #else
@@ -48,6 +51,21 @@ static inline struct intel_guc *ct_to_guc(struct intel_guc_ct *ct)
 	return container_of(ct, struct intel_guc, ct);
 }
 
+static inline struct intel_gt *ct_to_gt(struct intel_guc_ct *ct)
+{
+	return guc_to_gt(ct_to_guc(ct));
+}
+
+static inline struct drm_i915_private *ct_to_i915(struct intel_guc_ct *ct)
+{
+	return ct_to_gt(ct)->i915;
+}
+
+static inline struct device *ct_to_dev(struct intel_guc_ct *ct)
+{
+	return ct_to_i915(ct)->drm.dev;
+}
+
 static inline const char *guc_ct_buffer_type_to_str(u32 type)
 {
 	switch (type) {
@@ -157,8 +175,8 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
 	 */
 
 	err = intel_guc_allocate_and_map_vma(guc, PAGE_SIZE, &ct->vma, &blob);
-	if (err) {
-		DRM_ERROR("CT: channel allocation failed; err=%d\n", err);
+	if (unlikely(err)) {
+		CT_ERROR(ct, "Failed to allocate CT channel (err=%d)\n", err);
 		return err;
 	}
 
@@ -240,7 +258,7 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
 	guc_action_deregister_ct_buffer(guc,
 					INTEL_GUC_CT_BUFFER_TYPE_RECV);
 err_out:
-	DRM_ERROR("CT: can't open channel; err=%d\n", err);
+	CT_ERROR(ct, "Failed to open open CT channel (err=%d)\n", err);
 	return err;
 }
 
@@ -526,8 +544,8 @@ int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len,
 
 	ret = ct_send(ct, action, len, response_buf, response_buf_size, &status);
 	if (unlikely(ret < 0)) {
-		DRM_ERROR("CT: send action %#X failed; err=%d status=%#X\n",
-			  action[0], ret, status);
+		CT_ERROR(ct, "Sending action %#x failed (err=%d status=%#X)\n",
+			 action[0], ret, status);
 	} else if (unlikely(ret)) {
 		CT_DEBUG_DRIVER("CT: send action %#x returned %d (%#x)\n",
 				action[0], ret, ret);
@@ -639,7 +657,7 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
 
 	/* Response payload shall at least include fence and status */
 	if (unlikely(len < 2)) {
-		DRM_ERROR("CT: corrupted response %*ph\n", msgsize, msg);
+		CT_ERROR(ct, "Corrupted response %*ph\n", msgsize, msg);
 		return -EPROTO;
 	}
 
@@ -649,7 +667,7 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
 
 	/* Format of the status follows RESPONSE message */
 	if (unlikely(!INTEL_GUC_MSG_IS_RESPONSE(status))) {
-		DRM_ERROR("CT: corrupted response %*ph\n", msgsize, msg);
+		CT_ERROR(ct, "Corrupted response %*ph\n", msgsize, msg);
 		return -EPROTO;
 	}
 
@@ -663,8 +681,8 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
 			continue;
 		}
 		if (unlikely(datalen > req->response_len)) {
-			DRM_ERROR("CT: response %u too long %*ph\n",
-				  req->fence, msgsize, msg);
+			CT_ERROR(ct, "Response for %u is too long %*ph\n",
+				 req->fence, msgsize, msg);
 			datalen = 0;
 		}
 		if (datalen)
@@ -677,7 +695,7 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
 	spin_unlock(&ct->requests.lock);
 
 	if (!found)
-		DRM_ERROR("CT: unsolicited response %*ph\n", msgsize, msg);
+		CT_ERROR(ct, "Unsolicited response %*ph\n", msgsize, msg);
 	return 0;
 }
 
@@ -698,8 +716,8 @@ static void ct_process_request(struct intel_guc_ct *ct,
 
 	default:
 fail_unexpected:
-		DRM_ERROR("CT: unexpected request %x %*ph\n",
-			  action, 4 * len, payload);
+		CT_ERROR(ct, "Unexpected request %x %*ph\n",
+			 action, 4 * len, payload);
 		break;
 	}
 }
@@ -775,7 +793,7 @@ static int ct_handle_request(struct intel_guc_ct *ct, const u32 *msg)
 
 	request = kmalloc(sizeof(*request) + msgsize, GFP_ATOMIC);
 	if (unlikely(!request)) {
-		DRM_ERROR("CT: dropping request %*ph\n", msgsize, msg);
+		CT_ERROR(ct, "Dropping request %*ph\n", msgsize, msg);
 		return 0; /* XXX: -ENOMEM ? */
 	}
 	memcpy(request->msg, msg, msgsize);
@@ -815,7 +833,7 @@ void intel_guc_ct_event_handler(struct intel_guc_ct *ct)
 	} while (!err);
 
 	if (GEM_WARN_ON(err == -EPROTO)) {
-		DRM_ERROR("CT: corrupted message detected!\n");
+		CT_ERROR(ct, "Corrupted message: %#x\n", msg[0]);
 		ctb->desc->is_in_error = 1;
 	}
 }
-- 
2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 2/4] drm/i915/guc: Introduce CT_ERROR

[Daniele Ceraolo Spurio]

On 1/11/2020 3:11 PM, Michal Wajdeczko wrote:
> We should start using dev variants of error logging and
> to simplify that introduce helper macro that will do any
> necessary conversions to obtain pointer to device struct.
>
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 46 ++++++++++++++++-------
>   1 file changed, 32 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index 4aa07a53a9cf..eb123543392a 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -5,7 +5,10 @@
>   
>   #include "i915_drv.h"
>   #include "intel_guc_ct.h"
> +#include "gt/intel_gt.h"
>   
> +#define CT_ERROR(_ct, _fmt, ...) \
> +	DRM_DEV_ERROR(ct_to_dev(_ct), "CT: " _fmt, ##__VA_ARGS__)
>   #ifdef CONFIG_DRM_I915_DEBUG_GUC
>   #define CT_DEBUG_DRIVER(...)	DRM_DEBUG_DRIVER(__VA_ARGS__)

I'm not convinced by the fact that CT_ERROR and CT_DEBUG_DRIVER now have 
different styles. Maybe we should go with something like:

#define __CT_MSG(level, _ct, _fmt, ...) \
	DRM_DEV_##level(ct_to_dev(_ct), "CT: " _fmt, ##__VA_ARGS__)

#define CT_ERROR(_ct, _fmt, ...) __CT_MSG(ERROR, _ct, _fmt, ##__VA_ARGS__)

#ifdef CONFIG_DRM_I915_DEBUG_GUC
#define CT_DEBUG(_ct, _fmt, ...) \
	__CT_MSG(DEBUG_DRIVER, _ct, _fmt, ##__VA_ARGS__)
#else
#define CT_DEBUG(...)  do { } while (0)
#endif


Thoughts?

Daniele

>   #else
> @@ -48,6 +51,21 @@ static inline struct intel_guc *ct_to_guc(struct intel_guc_ct *ct)
>   	return container_of(ct, struct intel_guc, ct);
>   }
>   
> +static inline struct intel_gt *ct_to_gt(struct intel_guc_ct *ct)
> +{
> +	return guc_to_gt(ct_to_guc(ct));
> +}
> +
> +static inline struct drm_i915_private *ct_to_i915(struct intel_guc_ct *ct)
> +{
> +	return ct_to_gt(ct)->i915;
> +}
> +
> +static inline struct device *ct_to_dev(struct intel_guc_ct *ct)
> +{
> +	return ct_to_i915(ct)->drm.dev;
> +}
> +
>   static inline const char *guc_ct_buffer_type_to_str(u32 type)
>   {
>   	switch (type) {
> @@ -157,8 +175,8 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
>   	 */
>   
>   	err = intel_guc_allocate_and_map_vma(guc, PAGE_SIZE, &ct->vma, &blob);
> -	if (err) {
> -		DRM_ERROR("CT: channel allocation failed; err=%d\n", err);
> +	if (unlikely(err)) {
> +		CT_ERROR(ct, "Failed to allocate CT channel (err=%d)\n", err);
>   		return err;
>   	}
>   
> @@ -240,7 +258,7 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
>   	guc_action_deregister_ct_buffer(guc,
>   					INTEL_GUC_CT_BUFFER_TYPE_RECV);
>   err_out:
> -	DRM_ERROR("CT: can't open channel; err=%d\n", err);
> +	CT_ERROR(ct, "Failed to open open CT channel (err=%d)\n", err);
>   	return err;
>   }
>   
> @@ -526,8 +544,8 @@ int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len,
>   
>   	ret = ct_send(ct, action, len, response_buf, response_buf_size, &status);
>   	if (unlikely(ret < 0)) {
> -		DRM_ERROR("CT: send action %#X failed; err=%d status=%#X\n",
> -			  action[0], ret, status);
> +		CT_ERROR(ct, "Sending action %#x failed (err=%d status=%#X)\n",
> +			 action[0], ret, status);
>   	} else if (unlikely(ret)) {
>   		CT_DEBUG_DRIVER("CT: send action %#x returned %d (%#x)\n",
>   				action[0], ret, ret);
> @@ -639,7 +657,7 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
>   
>   	/* Response payload shall at least include fence and status */
>   	if (unlikely(len < 2)) {
> -		DRM_ERROR("CT: corrupted response %*ph\n", msgsize, msg);
> +		CT_ERROR(ct, "Corrupted response %*ph\n", msgsize, msg);
>   		return -EPROTO;
>   	}
>   
> @@ -649,7 +667,7 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
>   
>   	/* Format of the status follows RESPONSE message */
>   	if (unlikely(!INTEL_GUC_MSG_IS_RESPONSE(status))) {
> -		DRM_ERROR("CT: corrupted response %*ph\n", msgsize, msg);
> +		CT_ERROR(ct, "Corrupted response %*ph\n", msgsize, msg);
>   		return -EPROTO;
>   	}
>   
> @@ -663,8 +681,8 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
>   			continue;
>   		}
>   		if (unlikely(datalen > req->response_len)) {
> -			DRM_ERROR("CT: response %u too long %*ph\n",
> -				  req->fence, msgsize, msg);
> +			CT_ERROR(ct, "Response for %u is too long %*ph\n",
> +				 req->fence, msgsize, msg);
>   			datalen = 0;
>   		}
>   		if (datalen)
> @@ -677,7 +695,7 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
>   	spin_unlock(&ct->requests.lock);
>   
>   	if (!found)
> -		DRM_ERROR("CT: unsolicited response %*ph\n", msgsize, msg);
> +		CT_ERROR(ct, "Unsolicited response %*ph\n", msgsize, msg);
>   	return 0;
>   }
>   
> @@ -698,8 +716,8 @@ static void ct_process_request(struct intel_guc_ct *ct,
>   
>   	default:
>   fail_unexpected:
> -		DRM_ERROR("CT: unexpected request %x %*ph\n",
> -			  action, 4 * len, payload);
> +		CT_ERROR(ct, "Unexpected request %x %*ph\n",
> +			 action, 4 * len, payload);
>   		break;
>   	}
>   }
> @@ -775,7 +793,7 @@ static int ct_handle_request(struct intel_guc_ct *ct, const u32 *msg)
>   
>   	request = kmalloc(sizeof(*request) + msgsize, GFP_ATOMIC);
>   	if (unlikely(!request)) {
> -		DRM_ERROR("CT: dropping request %*ph\n", msgsize, msg);
> +		CT_ERROR(ct, "Dropping request %*ph\n", msgsize, msg);
>   		return 0; /* XXX: -ENOMEM ? */
>   	}
>   	memcpy(request->msg, msg, msgsize);
> @@ -815,7 +833,7 @@ void intel_guc_ct_event_handler(struct intel_guc_ct *ct)
>   	} while (!err);
>   
>   	if (GEM_WARN_ON(err == -EPROTO)) {
> -		DRM_ERROR("CT: corrupted message detected!\n");
> +		CT_ERROR(ct, "Corrupted message: %#x\n", msg[0]);
>   		ctb->desc->is_in_error = 1;
>   	}
>   }

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 2/4] drm/i915/guc: Introduce CT_ERROR

[Michal Wajdeczko]

On Mon, 13 Jan 2020 21:20:25 +0100, Daniele Ceraolo Spurio  
<daniele.ceraolospurio@intel.com> wrote:

>
>
> On 1/11/2020 3:11 PM, Michal Wajdeczko wrote:
>> We should start using dev variants of error logging and
>> to simplify that introduce helper macro that will do any
>> necessary conversions to obtain pointer to device struct.
>>
>> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> ---
>>   drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 46 ++++++++++++++++-------
>>   1 file changed, 32 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c  
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> index 4aa07a53a9cf..eb123543392a 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> @@ -5,7 +5,10 @@
>>     #include "i915_drv.h"
>>   #include "intel_guc_ct.h"
>> +#include "gt/intel_gt.h"
>>   +#define CT_ERROR(_ct, _fmt, ...) \
>> +	DRM_DEV_ERROR(ct_to_dev(_ct), "CT: " _fmt, ##__VA_ARGS__)
>>   #ifdef CONFIG_DRM_I915_DEBUG_GUC
>>   #define CT_DEBUG_DRIVER(...)	DRM_DEBUG_DRIVER(__VA_ARGS__)
>
> I'm not convinced by the fact that CT_ERROR and CT_DEBUG_DRIVER now have  
> different styles. Maybe we should go with something like:
>
> #define __CT_MSG(level, _ct, _fmt, ...) \
> 	DRM_DEV_##level(ct_to_dev(_ct), "CT: " _fmt, ##__VA_ARGS__)
>
> #define CT_ERROR(_ct, _fmt, ...) __CT_MSG(ERROR, _ct, _fmt,  
> ##__VA_ARGS__)
>
> #ifdef CONFIG_DRM_I915_DEBUG_GUC
> #define CT_DEBUG(_ct, _fmt, ...) \
> 	__CT_MSG(DEBUG_DRIVER, _ct, _fmt, ##__VA_ARGS__)
> #else
> #define CT_DEBUG(...)  do { } while (0)
> #endif
>
>
> Thoughts?

This is on my todo-list: I'm planning to add CT_DEBUG (with unified
style) after completing some other necessary refactoring to get 'ct'
in all places where we would like to replace old CT_DEBUG_DRIVER (as
you may notice now in some places we don't have ct/dev handy)

Michal

>
> Daniele
>
>>   #else
>> @@ -48,6 +51,21 @@ static inline struct intel_guc *ct_to_guc(struct  
>> intel_guc_ct *ct)
>>   	return container_of(ct, struct intel_guc, ct);
>>   }
>>   +static inline struct intel_gt *ct_to_gt(struct intel_guc_ct *ct)
>> +{
>> +	return guc_to_gt(ct_to_guc(ct));
>> +}
>> +
>> +static inline struct drm_i915_private *ct_to_i915(struct intel_guc_ct  
>> *ct)
>> +{
>> +	return ct_to_gt(ct)->i915;
>> +}
>> +
>> +static inline struct device *ct_to_dev(struct intel_guc_ct *ct)
>> +{
>> +	return ct_to_i915(ct)->drm.dev;
>> +}
>> +
>>   static inline const char *guc_ct_buffer_type_to_str(u32 type)
>>   {
>>   	switch (type) {
>> @@ -157,8 +175,8 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
>>   	 */
>>     	err = intel_guc_allocate_and_map_vma(guc, PAGE_SIZE, &ct->vma,  
>> &blob);
>> -	if (err) {
>> -		DRM_ERROR("CT: channel allocation failed; err=%d\n", err);
>> +	if (unlikely(err)) {
>> +		CT_ERROR(ct, "Failed to allocate CT channel (err=%d)\n", err);
>>   		return err;
>>   	}
>>   @@ -240,7 +258,7 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
>>   	guc_action_deregister_ct_buffer(guc,
>>   					INTEL_GUC_CT_BUFFER_TYPE_RECV);
>>   err_out:
>> -	DRM_ERROR("CT: can't open channel; err=%d\n", err);
>> +	CT_ERROR(ct, "Failed to open open CT channel (err=%d)\n", err);
>>   	return err;
>>   }
>>   @@ -526,8 +544,8 @@ int intel_guc_ct_send(struct intel_guc_ct *ct,  
>> const u32 *action, u32 len,
>>     	ret = ct_send(ct, action, len, response_buf, response_buf_size,  
>> &status);
>>   	if (unlikely(ret < 0)) {
>> -		DRM_ERROR("CT: send action %#X failed; err=%d status=%#X\n",
>> -			  action[0], ret, status);
>> +		CT_ERROR(ct, "Sending action %#x failed (err=%d status=%#X)\n",
>> +			 action[0], ret, status);
>>   	} else if (unlikely(ret)) {
>>   		CT_DEBUG_DRIVER("CT: send action %#x returned %d (%#x)\n",
>>   				action[0], ret, ret);
>> @@ -639,7 +657,7 @@ static int ct_handle_response(struct intel_guc_ct  
>> *ct, const u32 *msg)
>>     	/* Response payload shall at least include fence and status */
>>   	if (unlikely(len < 2)) {
>> -		DRM_ERROR("CT: corrupted response %*ph\n", msgsize, msg);
>> +		CT_ERROR(ct, "Corrupted response %*ph\n", msgsize, msg);
>>   		return -EPROTO;
>>   	}
>>   @@ -649,7 +667,7 @@ static int ct_handle_response(struct intel_guc_ct  
>> *ct, const u32 *msg)
>>     	/* Format of the status follows RESPONSE message */
>>   	if (unlikely(!INTEL_GUC_MSG_IS_RESPONSE(status))) {
>> -		DRM_ERROR("CT: corrupted response %*ph\n", msgsize, msg);
>> +		CT_ERROR(ct, "Corrupted response %*ph\n", msgsize, msg);
>>   		return -EPROTO;
>>   	}
>>   @@ -663,8 +681,8 @@ static int ct_handle_response(struct intel_guc_ct  
>> *ct, const u32 *msg)
>>   			continue;
>>   		}
>>   		if (unlikely(datalen > req->response_len)) {
>> -			DRM_ERROR("CT: response %u too long %*ph\n",
>> -				  req->fence, msgsize, msg);
>> +			CT_ERROR(ct, "Response for %u is too long %*ph\n",
>> +				 req->fence, msgsize, msg);
>>   			datalen = 0;
>>   		}
>>   		if (datalen)
>> @@ -677,7 +695,7 @@ static int ct_handle_response(struct intel_guc_ct  
>> *ct, const u32 *msg)
>>   	spin_unlock(&ct->requests.lock);
>>     	if (!found)
>> -		DRM_ERROR("CT: unsolicited response %*ph\n", msgsize, msg);
>> +		CT_ERROR(ct, "Unsolicited response %*ph\n", msgsize, msg);
>>   	return 0;
>>   }
>>   @@ -698,8 +716,8 @@ static void ct_process_request(struct  
>> intel_guc_ct *ct,
>>     	default:
>>   fail_unexpected:
>> -		DRM_ERROR("CT: unexpected request %x %*ph\n",
>> -			  action, 4 * len, payload);
>> +		CT_ERROR(ct, "Unexpected request %x %*ph\n",
>> +			 action, 4 * len, payload);
>>   		break;
>>   	}
>>   }
>> @@ -775,7 +793,7 @@ static int ct_handle_request(struct intel_guc_ct  
>> *ct, const u32 *msg)
>>     	request = kmalloc(sizeof(*request) + msgsize, GFP_ATOMIC);
>>   	if (unlikely(!request)) {
>> -		DRM_ERROR("CT: dropping request %*ph\n", msgsize, msg);
>> +		CT_ERROR(ct, "Dropping request %*ph\n", msgsize, msg);
>>   		return 0; /* XXX: -ENOMEM ? */
>>   	}
>>   	memcpy(request->msg, msg, msgsize);
>> @@ -815,7 +833,7 @@ void intel_guc_ct_event_handler(struct intel_guc_ct  
>> *ct)
>>   	} while (!err);
>>     	if (GEM_WARN_ON(err == -EPROTO)) {
>> -		DRM_ERROR("CT: corrupted message detected!\n");
>> +		CT_ERROR(ct, "Corrupted message: %#x\n", msg[0]);
>>   		ctb->desc->is_in_error = 1;
>>   	}
>>   }
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 2/4] drm/i915/guc: Introduce CT_ERROR

[Daniele Ceraolo Spurio]

On 1/13/2020 12:52 PM, Michal Wajdeczko wrote:
> On Mon, 13 Jan 2020 21:20:25 +0100, Daniele Ceraolo Spurio 
> <daniele.ceraolospurio@intel.com> wrote:
>
>>
>>
>> On 1/11/2020 3:11 PM, Michal Wajdeczko wrote:
>>> We should start using dev variants of error logging and
>>> to simplify that introduce helper macro that will do any
>>> necessary conversions to obtain pointer to device struct.
>>>
>>> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
>>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 46 
>>> ++++++++++++++++-------
>>>   1 file changed, 32 insertions(+), 14 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> index 4aa07a53a9cf..eb123543392a 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> @@ -5,7 +5,10 @@
>>>     #include "i915_drv.h"
>>>   #include "intel_guc_ct.h"
>>> +#include "gt/intel_gt.h"
>>>   +#define CT_ERROR(_ct, _fmt, ...) \
>>> +    DRM_DEV_ERROR(ct_to_dev(_ct), "CT: " _fmt, ##__VA_ARGS__)
>>>   #ifdef CONFIG_DRM_I915_DEBUG_GUC
>>>   #define CT_DEBUG_DRIVER(...) DRM_DEBUG_DRIVER(__VA_ARGS__)
>>
>> I'm not convinced by the fact that CT_ERROR and CT_DEBUG_DRIVER now 
>> have different styles. Maybe we should go with something like:
>>
>> #define __CT_MSG(level, _ct, _fmt, ...) \
>>     DRM_DEV_##level(ct_to_dev(_ct), "CT: " _fmt, ##__VA_ARGS__)
>>
>> #define CT_ERROR(_ct, _fmt, ...) __CT_MSG(ERROR, _ct, _fmt, 
>> ##__VA_ARGS__)
>>
>> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>> #define CT_DEBUG(_ct, _fmt, ...) \
>>     __CT_MSG(DEBUG_DRIVER, _ct, _fmt, ##__VA_ARGS__)
>> #else
>> #define CT_DEBUG(...)  do { } while (0)
>> #endif
>>
>>
>> Thoughts?
>
> This is on my todo-list: I'm planning to add CT_DEBUG (with unified
> style) after completing some other necessary refactoring to get 'ct'
> in all places where we would like to replace old CT_DEBUG_DRIVER (as
> you may notice now in some places we don't have ct/dev handy)
>

If you're committing to land those other reworks in a reasonable time 
after this is merged, then:

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

> Michal
>
>>
>> Daniele
>>
>>>   #else
>>> @@ -48,6 +51,21 @@ static inline struct intel_guc *ct_to_guc(struct 
>>> intel_guc_ct *ct)
>>>       return container_of(ct, struct intel_guc, ct);
>>>   }
>>>   +static inline struct intel_gt *ct_to_gt(struct intel_guc_ct *ct)
>>> +{
>>> +    return guc_to_gt(ct_to_guc(ct));
>>> +}
>>> +
>>> +static inline struct drm_i915_private *ct_to_i915(struct 
>>> intel_guc_ct *ct)
>>> +{
>>> +    return ct_to_gt(ct)->i915;
>>> +}
>>> +
>>> +static inline struct device *ct_to_dev(struct intel_guc_ct *ct)
>>> +{
>>> +    return ct_to_i915(ct)->drm.dev;
>>> +}
>>> +
>>>   static inline const char *guc_ct_buffer_type_to_str(u32 type)
>>>   {
>>>       switch (type) {
>>> @@ -157,8 +175,8 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
>>>        */
>>>         err = intel_guc_allocate_and_map_vma(guc, PAGE_SIZE, 
>>> &ct->vma, &blob);
>>> -    if (err) {
>>> -        DRM_ERROR("CT: channel allocation failed; err=%d\n", err);
>>> +    if (unlikely(err)) {
>>> +        CT_ERROR(ct, "Failed to allocate CT channel (err=%d)\n", err);
>>>           return err;
>>>       }
>>>   @@ -240,7 +258,7 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
>>>       guc_action_deregister_ct_buffer(guc,
>>>                       INTEL_GUC_CT_BUFFER_TYPE_RECV);
>>>   err_out:
>>> -    DRM_ERROR("CT: can't open channel; err=%d\n", err);
>>> +    CT_ERROR(ct, "Failed to open open CT channel (err=%d)\n", err);
>>>       return err;
>>>   }
>>>   @@ -526,8 +544,8 @@ int intel_guc_ct_send(struct intel_guc_ct *ct, 
>>> const u32 *action, u32 len,
>>>         ret = ct_send(ct, action, len, response_buf, 
>>> response_buf_size, &status);
>>>       if (unlikely(ret < 0)) {
>>> -        DRM_ERROR("CT: send action %#X failed; err=%d status=%#X\n",
>>> -              action[0], ret, status);
>>> +        CT_ERROR(ct, "Sending action %#x failed (err=%d 
>>> status=%#X)\n",
>>> +             action[0], ret, status);
>>>       } else if (unlikely(ret)) {
>>>           CT_DEBUG_DRIVER("CT: send action %#x returned %d (%#x)\n",
>>>                   action[0], ret, ret);
>>> @@ -639,7 +657,7 @@ static int ct_handle_response(struct 
>>> intel_guc_ct *ct, const u32 *msg)
>>>         /* Response payload shall at least include fence and status */
>>>       if (unlikely(len < 2)) {
>>> -        DRM_ERROR("CT: corrupted response %*ph\n", msgsize, msg);
>>> +        CT_ERROR(ct, "Corrupted response %*ph\n", msgsize, msg);
>>>           return -EPROTO;
>>>       }
>>>   @@ -649,7 +667,7 @@ static int ct_handle_response(struct 
>>> intel_guc_ct *ct, const u32 *msg)
>>>         /* Format of the status follows RESPONSE message */
>>>       if (unlikely(!INTEL_GUC_MSG_IS_RESPONSE(status))) {
>>> -        DRM_ERROR("CT: corrupted response %*ph\n", msgsize, msg);
>>> +        CT_ERROR(ct, "Corrupted response %*ph\n", msgsize, msg);
>>>           return -EPROTO;
>>>       }
>>>   @@ -663,8 +681,8 @@ static int ct_handle_response(struct 
>>> intel_guc_ct *ct, const u32 *msg)
>>>               continue;
>>>           }
>>>           if (unlikely(datalen > req->response_len)) {
>>> -            DRM_ERROR("CT: response %u too long %*ph\n",
>>> -                  req->fence, msgsize, msg);
>>> +            CT_ERROR(ct, "Response for %u is too long %*ph\n",
>>> +                 req->fence, msgsize, msg);
>>>               datalen = 0;
>>>           }
>>>           if (datalen)
>>> @@ -677,7 +695,7 @@ static int ct_handle_response(struct 
>>> intel_guc_ct *ct, const u32 *msg)
>>>       spin_unlock(&ct->requests.lock);
>>>         if (!found)
>>> -        DRM_ERROR("CT: unsolicited response %*ph\n", msgsize, msg);
>>> +        CT_ERROR(ct, "Unsolicited response %*ph\n", msgsize, msg);
>>>       return 0;
>>>   }
>>>   @@ -698,8 +716,8 @@ static void ct_process_request(struct 
>>> intel_guc_ct *ct,
>>>         default:
>>>   fail_unexpected:
>>> -        DRM_ERROR("CT: unexpected request %x %*ph\n",
>>> -              action, 4 * len, payload);
>>> +        CT_ERROR(ct, "Unexpected request %x %*ph\n",
>>> +             action, 4 * len, payload);
>>>           break;
>>>       }
>>>   }
>>> @@ -775,7 +793,7 @@ static int ct_handle_request(struct intel_guc_ct 
>>> *ct, const u32 *msg)
>>>         request = kmalloc(sizeof(*request) + msgsize, GFP_ATOMIC);
>>>       if (unlikely(!request)) {
>>> -        DRM_ERROR("CT: dropping request %*ph\n", msgsize, msg);
>>> +        CT_ERROR(ct, "Dropping request %*ph\n", msgsize, msg);
>>>           return 0; /* XXX: -ENOMEM ? */
>>>       }
>>>       memcpy(request->msg, msg, msgsize);
>>> @@ -815,7 +833,7 @@ void intel_guc_ct_event_handler(struct 
>>> intel_guc_ct *ct)
>>>       } while (!err);
>>>         if (GEM_WARN_ON(err == -EPROTO)) {
>>> -        DRM_ERROR("CT: corrupted message detected!\n");
>>> +        CT_ERROR(ct, "Corrupted message: %#x\n", msg[0]);
>>>           ctb->desc->is_in_error = 1;
>>>       }
>>>   }

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 2/4] drm/i915/guc: Introduce CT_ERROR

[Michal Wajdeczko]

On Mon, 13 Jan 2020 22:59:46 +0100, Daniele Ceraolo Spurio  
<daniele.ceraolospurio@intel.com> wrote:

>
>
> On 1/13/2020 12:52 PM, Michal Wajdeczko wrote:
>> On Mon, 13 Jan 2020 21:20:25 +0100, Daniele Ceraolo Spurio  
>> <daniele.ceraolospurio@intel.com> wrote:
>>
>>>
>>>
>>> On 1/11/2020 3:11 PM, Michal Wajdeczko wrote:
>>>> We should start using dev variants of error logging and
>>>> to simplify that introduce helper macro that will do any
>>>> necessary conversions to obtain pointer to device struct.
>>>>
>>>> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
>>>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>>>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>>> ---
>>>>   drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 46  
>>>> ++++++++++++++++-------
>>>>   1 file changed, 32 insertions(+), 14 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c  
>>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>> index 4aa07a53a9cf..eb123543392a 100644
>>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>> @@ -5,7 +5,10 @@
>>>>     #include "i915_drv.h"
>>>>   #include "intel_guc_ct.h"
>>>> +#include "gt/intel_gt.h"
>>>>   +#define CT_ERROR(_ct, _fmt, ...) \
>>>> +    DRM_DEV_ERROR(ct_to_dev(_ct), "CT: " _fmt, ##__VA_ARGS__)
>>>>   #ifdef CONFIG_DRM_I915_DEBUG_GUC
>>>>   #define CT_DEBUG_DRIVER(...) DRM_DEBUG_DRIVER(__VA_ARGS__)
>>>
>>> I'm not convinced by the fact that CT_ERROR and CT_DEBUG_DRIVER now  
>>> have different styles. Maybe we should go with something like:
>>>
>>> #define __CT_MSG(level, _ct, _fmt, ...) \
>>>     DRM_DEV_##level(ct_to_dev(_ct), "CT: " _fmt, ##__VA_ARGS__)
>>>
>>> #define CT_ERROR(_ct, _fmt, ...) __CT_MSG(ERROR, _ct, _fmt,  
>>> ##__VA_ARGS__)
>>>
>>> #ifdef CONFIG_DRM_I915_DEBUG_GUC
>>> #define CT_DEBUG(_ct, _fmt, ...) \
>>>     __CT_MSG(DEBUG_DRIVER, _ct, _fmt, ##__VA_ARGS__)
>>> #else
>>> #define CT_DEBUG(...)  do { } while (0)
>>> #endif
>>>
>>>
>>> Thoughts?
>>
>> This is on my todo-list: I'm planning to add CT_DEBUG (with unified
>> style) after completing some other necessary refactoring to get 'ct'
>> in all places where we would like to replace old CT_DEBUG_DRIVER (as
>> you may notice now in some places we don't have ct/dev handy)
>>
>
> If you're committing to land those other reworks in a reasonable time  
> after this is merged, then:
>
> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>
> Daniele
>

You can count on me

>> Michal
>>
>>>
>>> Daniele
>>>
>>>>   #else
>>>> @@ -48,6 +51,21 @@ static inline struct intel_guc *ct_to_guc(struct  
>>>> intel_guc_ct *ct)
>>>>       return container_of(ct, struct intel_guc, ct);
>>>>   }
>>>>   +static inline struct intel_gt *ct_to_gt(struct intel_guc_ct *ct)
>>>> +{
>>>> +    return guc_to_gt(ct_to_guc(ct));
>>>> +}
>>>> +
>>>> +static inline struct drm_i915_private *ct_to_i915(struct  
>>>> intel_guc_ct *ct)
>>>> +{
>>>> +    return ct_to_gt(ct)->i915;
>>>> +}
>>>> +
>>>> +static inline struct device *ct_to_dev(struct intel_guc_ct *ct)
>>>> +{
>>>> +    return ct_to_i915(ct)->drm.dev;
>>>> +}
>>>> +
>>>>   static inline const char *guc_ct_buffer_type_to_str(u32 type)
>>>>   {
>>>>       switch (type) {
>>>> @@ -157,8 +175,8 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
>>>>        */
>>>>         err = intel_guc_allocate_and_map_vma(guc, PAGE_SIZE,  
>>>> &ct->vma, &blob);
>>>> -    if (err) {
>>>> -        DRM_ERROR("CT: channel allocation failed; err=%d\n", err);
>>>> +    if (unlikely(err)) {
>>>> +        CT_ERROR(ct, "Failed to allocate CT channel (err=%d)\n",  
>>>> err);
>>>>           return err;
>>>>       }
>>>>   @@ -240,7 +258,7 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
>>>>       guc_action_deregister_ct_buffer(guc,
>>>>                       INTEL_GUC_CT_BUFFER_TYPE_RECV);
>>>>   err_out:
>>>> -    DRM_ERROR("CT: can't open channel; err=%d\n", err);
>>>> +    CT_ERROR(ct, "Failed to open open CT channel (err=%d)\n", err);
>>>>       return err;
>>>>   }
>>>>   @@ -526,8 +544,8 @@ int intel_guc_ct_send(struct intel_guc_ct *ct,  
>>>> const u32 *action, u32 len,
>>>>         ret = ct_send(ct, action, len, response_buf,  
>>>> response_buf_size, &status);
>>>>       if (unlikely(ret < 0)) {
>>>> -        DRM_ERROR("CT: send action %#X failed; err=%d status=%#X\n",
>>>> -              action[0], ret, status);
>>>> +        CT_ERROR(ct, "Sending action %#x failed (err=%d  
>>>> status=%#X)\n",
>>>> +             action[0], ret, status);
>>>>       } else if (unlikely(ret)) {
>>>>           CT_DEBUG_DRIVER("CT: send action %#x returned %d (%#x)\n",
>>>>                   action[0], ret, ret);
>>>> @@ -639,7 +657,7 @@ static int ct_handle_response(struct intel_guc_ct  
>>>> *ct, const u32 *msg)
>>>>         /* Response payload shall at least include fence and status */
>>>>       if (unlikely(len < 2)) {
>>>> -        DRM_ERROR("CT: corrupted response %*ph\n", msgsize, msg);
>>>> +        CT_ERROR(ct, "Corrupted response %*ph\n", msgsize, msg);
>>>>           return -EPROTO;
>>>>       }
>>>>   @@ -649,7 +667,7 @@ static int ct_handle_response(struct  
>>>> intel_guc_ct *ct, const u32 *msg)
>>>>         /* Format of the status follows RESPONSE message */
>>>>       if (unlikely(!INTEL_GUC_MSG_IS_RESPONSE(status))) {
>>>> -        DRM_ERROR("CT: corrupted response %*ph\n", msgsize, msg);
>>>> +        CT_ERROR(ct, "Corrupted response %*ph\n", msgsize, msg);
>>>>           return -EPROTO;
>>>>       }
>>>>   @@ -663,8 +681,8 @@ static int ct_handle_response(struct  
>>>> intel_guc_ct *ct, const u32 *msg)
>>>>               continue;
>>>>           }
>>>>           if (unlikely(datalen > req->response_len)) {
>>>> -            DRM_ERROR("CT: response %u too long %*ph\n",
>>>> -                  req->fence, msgsize, msg);
>>>> +            CT_ERROR(ct, "Response for %u is too long %*ph\n",
>>>> +                 req->fence, msgsize, msg);
>>>>               datalen = 0;
>>>>           }
>>>>           if (datalen)
>>>> @@ -677,7 +695,7 @@ static int ct_handle_response(struct intel_guc_ct  
>>>> *ct, const u32 *msg)
>>>>       spin_unlock(&ct->requests.lock);
>>>>         if (!found)
>>>> -        DRM_ERROR("CT: unsolicited response %*ph\n", msgsize, msg);
>>>> +        CT_ERROR(ct, "Unsolicited response %*ph\n", msgsize, msg);
>>>>       return 0;
>>>>   }
>>>>   @@ -698,8 +716,8 @@ static void ct_process_request(struct  
>>>> intel_guc_ct *ct,
>>>>         default:
>>>>   fail_unexpected:
>>>> -        DRM_ERROR("CT: unexpected request %x %*ph\n",
>>>> -              action, 4 * len, payload);
>>>> +        CT_ERROR(ct, "Unexpected request %x %*ph\n",
>>>> +             action, 4 * len, payload);
>>>>           break;
>>>>       }
>>>>   }
>>>> @@ -775,7 +793,7 @@ static int ct_handle_request(struct intel_guc_ct  
>>>> *ct, const u32 *msg)
>>>>         request = kmalloc(sizeof(*request) + msgsize, GFP_ATOMIC);
>>>>       if (unlikely(!request)) {
>>>> -        DRM_ERROR("CT: dropping request %*ph\n", msgsize, msg);
>>>> +        CT_ERROR(ct, "Dropping request %*ph\n", msgsize, msg);
>>>>           return 0; /* XXX: -ENOMEM ? */
>>>>       }
>>>>       memcpy(request->msg, msg, msgsize);
>>>> @@ -815,7 +833,7 @@ void intel_guc_ct_event_handler(struct  
>>>> intel_guc_ct *ct)
>>>>       } while (!err);
>>>>         if (GEM_WARN_ON(err == -EPROTO)) {
>>>> -        DRM_ERROR("CT: corrupted message detected!\n");
>>>> +        CT_ERROR(ct, "Corrupted message: %#x\n", msg[0]);
>>>>           ctb->desc->is_in_error = 1;
>>>>       }
>>>>   }
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 3/4] drm/i915/guc: Update CTB helpers to use CT_ERROR

[Michal Wajdeczko]

Update GuC CTB action helpers to benefit from new CT_ERROR macro.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 57 ++++++++++++-----------
 1 file changed, 31 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index eb123543392a..1da69425029b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -107,31 +107,40 @@ static int guc_action_register_ct_buffer(struct intel_guc *guc,
 		sizeof(struct guc_ct_buffer_desc),
 		type
 	};
-	int err;
 
 	/* Can't use generic send(), CT registration must go over MMIO */
-	err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
-	if (err)
-		DRM_ERROR("CT: register %s buffer failed; err=%d\n",
-			  guc_ct_buffer_type_to_str(type), err);
+	return intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
+}
+
+static int ct_register_buffer(struct intel_guc_ct *ct, u32 desc_addr, u32 type)
+{
+	int err = guc_action_register_ct_buffer(ct_to_guc(ct), desc_addr, type);
+
+	if (unlikely(err))
+		CT_ERROR(ct, "Failed to register %s buffer (err=%d)\n",
+			 guc_ct_buffer_type_to_str(type), err);
 	return err;
 }
 
-static int guc_action_deregister_ct_buffer(struct intel_guc *guc,
-					   u32 type)
+static int guc_action_deregister_ct_buffer(struct intel_guc *guc, u32 type)
 {
 	u32 action[] = {
 		INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER,
 		CTB_OWNER_HOST,
 		type
 	};
-	int err;
 
 	/* Can't use generic send(), CT deregistration must go over MMIO */
-	err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
-	if (err)
-		DRM_ERROR("CT: deregister %s buffer failed; err=%d\n",
-			  guc_ct_buffer_type_to_str(type), err);
+	return intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
+}
+
+static int ct_deregister_buffer(struct intel_guc_ct *ct, u32 type)
+{
+	int err = guc_action_deregister_ct_buffer(ct_to_guc(ct), type);
+
+	if (unlikely(err))
+		CT_ERROR(ct, "Failed to deregister %s buffer (err=%d)\n",
+			 guc_ct_buffer_type_to_str(type), err);
 	return err;
 }
 
@@ -235,18 +244,17 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
 					PAGE_SIZE/4);
 	}
 
-	/* register buffers, starting wirh RECV buffer
-	 * descriptors are in first half of the blob
+	/*
+	 * Register both CT buffers starting with RECV buffer.
+	 * Descriptors are in first half of the blob.
 	 */
-	err = guc_action_register_ct_buffer(guc,
-					    base + PAGE_SIZE/4 * CTB_RECV,
-					    INTEL_GUC_CT_BUFFER_TYPE_RECV);
+	err = ct_register_buffer(ct, base + PAGE_SIZE/4 * CTB_RECV,
+				 INTEL_GUC_CT_BUFFER_TYPE_RECV);
 	if (unlikely(err))
 		goto err_out;
 
-	err = guc_action_register_ct_buffer(guc,
-					    base + PAGE_SIZE/4 * CTB_SEND,
-					    INTEL_GUC_CT_BUFFER_TYPE_SEND);
+	err = ct_register_buffer(ct, base + PAGE_SIZE/4 * CTB_SEND,
+				 INTEL_GUC_CT_BUFFER_TYPE_SEND);
 	if (unlikely(err))
 		goto err_deregister;
 
@@ -255,8 +263,7 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
 	return 0;
 
 err_deregister:
-	guc_action_deregister_ct_buffer(guc,
-					INTEL_GUC_CT_BUFFER_TYPE_RECV);
+	ct_deregister_buffer(ct, INTEL_GUC_CT_BUFFER_TYPE_RECV);
 err_out:
 	CT_ERROR(ct, "Failed to open open CT channel (err=%d)\n", err);
 	return err;
@@ -275,10 +282,8 @@ void intel_guc_ct_disable(struct intel_guc_ct *ct)
 	ct->enabled = false;
 
 	if (intel_guc_is_running(guc)) {
-		guc_action_deregister_ct_buffer(guc,
-						INTEL_GUC_CT_BUFFER_TYPE_SEND);
-		guc_action_deregister_ct_buffer(guc,
-						INTEL_GUC_CT_BUFFER_TYPE_RECV);
+		ct_deregister_buffer(ct, INTEL_GUC_CT_BUFFER_TYPE_SEND);
+		ct_deregister_buffer(ct, INTEL_GUC_CT_BUFFER_TYPE_RECV);
 	}
 }
 
-- 
2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 3/4] drm/i915/guc: Update CTB helpers to use CT_ERROR

[Daniele Ceraolo Spurio]

On 1/11/2020 3:11 PM, Michal Wajdeczko wrote:
> Update GuC CTB action helpers to benefit from new CT_ERROR macro.
>
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 57 ++++++++++++-----------
>   1 file changed, 31 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index eb123543392a..1da69425029b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -107,31 +107,40 @@ static int guc_action_register_ct_buffer(struct intel_guc *guc,
>   		sizeof(struct guc_ct_buffer_desc),
>   		type
>   	};
> -	int err;
>   
>   	/* Can't use generic send(), CT registration must go over MMIO */
> -	err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
> -	if (err)
> -		DRM_ERROR("CT: register %s buffer failed; err=%d\n",
> -			  guc_ct_buffer_type_to_str(type), err);
> +	return intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
> +}
> +
> +static int ct_register_buffer(struct intel_guc_ct *ct, u32 desc_addr, u32 type)
> +{
> +	int err = guc_action_register_ct_buffer(ct_to_guc(ct), desc_addr, type);
> +
> +	if (unlikely(err))
> +		CT_ERROR(ct, "Failed to register %s buffer (err=%d)\n",
> +			 guc_ct_buffer_type_to_str(type), err);
>   	return err;
>   }

Now that we're passing ct to this I'm wondering if it makes sense to 
move some of the math from outside in here, e.g:

const u32 i915_ct_to_guc_ct_type [] = {
	[CTB_RECV] = INTEL_GUC_CT_BUFFER_TYPE_RECV;
	[CTB_SEND] = INTEL_GUC_CT_BUFFER_TYPE_SEND;
}

#define CT_DESC_OFFSET 0
#define CT_DESC_SIZE (PAGE_SIZE / 4)
#define CT_BUF_OFFSET (PAGE_SIZE / 2)
#define CT_BUF_SIZE (PAGE_SIZE / 4)
static int ct_register_buffer(struct intel_guc_ct *ct, u32 type)
{
	struct intel_guc *guc = ct_to_guc(ct);
	u32 base = intel_guc_ggtt_offset(guc, ct->vma);
	u32 desc_addr = base + CT_DESC_OFFSET + CT_DESC_SIZE * type;
	u32 buf_addr = base + CT_BUF_OFFSET + CT_BUF_SIZE * type;
	int err;

	ct_buffer_desc_init(ct->ctbs[type].desc, buf_addr, CT_BUF_SIZE);

	err = guc_action_register_ct_buffer(guc, desc_addr,
					    i915_ct_to_guc_ct_type[type]);
	if (unlikely(err))
		CT_ERROR(ct, "Failed to register %s buffer (err=%d)\n",
			 guc_ct_buffer_type_to_str(type), err);
  	return err;
}


And then just call:

      err = ct_register_buffer(ct, CTB_RECV);


Or maybe it's overkill?
With or without the above changes:

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

>   
> -static int guc_action_deregister_ct_buffer(struct intel_guc *guc,
> -					   u32 type)
> +static int guc_action_deregister_ct_buffer(struct intel_guc *guc, u32 type)
>   {
>   	u32 action[] = {
>   		INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER,
>   		CTB_OWNER_HOST,
>   		type
>   	};
> -	int err;
>   
>   	/* Can't use generic send(), CT deregistration must go over MMIO */
> -	err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
> -	if (err)
> -		DRM_ERROR("CT: deregister %s buffer failed; err=%d\n",
> -			  guc_ct_buffer_type_to_str(type), err);
> +	return intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
> +}
> +
> +static int ct_deregister_buffer(struct intel_guc_ct *ct, u32 type)
> +{
> +	int err = guc_action_deregister_ct_buffer(ct_to_guc(ct), type);
> +
> +	if (unlikely(err))
> +		CT_ERROR(ct, "Failed to deregister %s buffer (err=%d)\n",
> +			 guc_ct_buffer_type_to_str(type), err);
>   	return err;
>   }
>   
> @@ -235,18 +244,17 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
>   					PAGE_SIZE/4);
>   	}
>   
> -	/* register buffers, starting wirh RECV buffer
> -	 * descriptors are in first half of the blob
> +	/*
> +	 * Register both CT buffers starting with RECV buffer.
> +	 * Descriptors are in first half of the blob.
>   	 */
> -	err = guc_action_register_ct_buffer(guc,
> -					    base + PAGE_SIZE/4 * CTB_RECV,
> -					    INTEL_GUC_CT_BUFFER_TYPE_RECV);
> +	err = ct_register_buffer(ct, base + PAGE_SIZE/4 * CTB_RECV,
> +				 INTEL_GUC_CT_BUFFER_TYPE_RECV);
>   	if (unlikely(err))
>   		goto err_out;
>   
> -	err = guc_action_register_ct_buffer(guc,
> -					    base + PAGE_SIZE/4 * CTB_SEND,
> -					    INTEL_GUC_CT_BUFFER_TYPE_SEND);
> +	err = ct_register_buffer(ct, base + PAGE_SIZE/4 * CTB_SEND,
> +				 INTEL_GUC_CT_BUFFER_TYPE_SEND);
>   	if (unlikely(err))
>   		goto err_deregister;
>   
> @@ -255,8 +263,7 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
>   	return 0;
>   
>   err_deregister:
> -	guc_action_deregister_ct_buffer(guc,
> -					INTEL_GUC_CT_BUFFER_TYPE_RECV);
> +	ct_deregister_buffer(ct, INTEL_GUC_CT_BUFFER_TYPE_RECV);
>   err_out:
>   	CT_ERROR(ct, "Failed to open open CT channel (err=%d)\n", err);
>   	return err;
> @@ -275,10 +282,8 @@ void intel_guc_ct_disable(struct intel_guc_ct *ct)
>   	ct->enabled = false;
>   
>   	if (intel_guc_is_running(guc)) {
> -		guc_action_deregister_ct_buffer(guc,
> -						INTEL_GUC_CT_BUFFER_TYPE_SEND);
> -		guc_action_deregister_ct_buffer(guc,
> -						INTEL_GUC_CT_BUFFER_TYPE_RECV);
> +		ct_deregister_buffer(ct, INTEL_GUC_CT_BUFFER_TYPE_SEND);
> +		ct_deregister_buffer(ct, INTEL_GUC_CT_BUFFER_TYPE_RECV);
>   	}
>   }
>   

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 4/4] drm/i915/guc: Use correct name for last CT fence

[Michal Wajdeczko]

While we have function that returns "next fence" that can be used
by new CT request, we internally store value of the last used fence.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 2 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 1da69425029b..73f617cbcf55 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -290,7 +290,7 @@ void intel_guc_ct_disable(struct intel_guc_ct *ct)
 static u32 ct_get_next_fence(struct intel_guc_ct *ct)
 {
 	/* For now it's trivial */
-	return ++ct->requests.next_fence;
+	return ++ct->requests.last_fence;
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
index 3e7fe237cfa5..97913bbb8be3 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
@@ -49,7 +49,7 @@ struct intel_guc_ct {
 	struct intel_guc_ct_buffer ctbs[2];
 
 	struct {
-		u32 next_fence; /* fence to be used with next request to send */
+		u32 last_fence; /* last fence used to send request */
 
 		spinlock_t lock; /* protects pending requests list */
 		struct list_head pending; /* requests waiting for response */
-- 
2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 4/4] drm/i915/guc: Use correct name for last CT fence

[Daniele Ceraolo Spurio]

On 1/11/2020 3:11 PM, Michal Wajdeczko wrote:
> While we have function that returns "next fence" that can be used
> by new CT request, we internally store value of the last used fence.
>
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

> ---
>   drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 2 +-
>   drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 2 +-
>   2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index 1da69425029b..73f617cbcf55 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -290,7 +290,7 @@ void intel_guc_ct_disable(struct intel_guc_ct *ct)
>   static u32 ct_get_next_fence(struct intel_guc_ct *ct)
>   {
>   	/* For now it's trivial */
> -	return ++ct->requests.next_fence;
> +	return ++ct->requests.last_fence;
>   }
>   
>   /**
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> index 3e7fe237cfa5..97913bbb8be3 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> @@ -49,7 +49,7 @@ struct intel_guc_ct {
>   	struct intel_guc_ct_buffer ctbs[2];
>   
>   	struct {
> -		u32 next_fence; /* fence to be used with next request to send */
> +		u32 last_fence; /* last fence used to send request */
>   
>   		spinlock_t lock; /* protects pending requests list */
>   		struct list_head pending; /* requests waiting for response */

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Misc GuC CT improvements

[Patchwork]

== Series Details ==

Series: Misc GuC CT improvements
URL   : https://patchwork.freedesktop.org/series/71927/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
fcb6ad56e500 drm/i915/guc: Simpler CT message size calculation
3de4fca5641b drm/i915/guc: Introduce CT_ERROR
e65db0f0de6a drm/i915/guc: Update CTB helpers to use CT_ERROR
-:82: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#82: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:251:
+	err = ct_register_buffer(ct, base + PAGE_SIZE/4 * CTB_RECV,
 	                                             ^

-:90: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#90: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:256:
+	err = ct_register_buffer(ct, base + PAGE_SIZE/4 * CTB_SEND,
 	                                             ^

total: 0 errors, 0 warnings, 2 checks, 98 lines checked
78fc81508a2a drm/i915/guc: Use correct name for last CT fence

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for Misc GuC CT improvements

[Patchwork]

== Series Details ==

Series: Misc GuC CT improvements
URL   : https://patchwork.freedesktop.org/series/71927/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7725 -> Patchwork_16067
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/index.html

Known issues
------------

  Here are the changes found in Patchwork_16067 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_module_load@reload-with-fault-injection:
    - fi-skl-lmem:        [PASS][1] -> [INCOMPLETE][2] ([i915#671])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/fi-skl-lmem/igt@i915_module_load@reload-with-fault-injection.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/fi-skl-lmem/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_selftest@live_blt:
    - fi-hsw-4770r:       [PASS][3] -> [DMESG-FAIL][4] ([i915#563])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/fi-hsw-4770r/igt@i915_selftest@live_blt.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/fi-hsw-4770r/igt@i915_selftest@live_blt.html

  
#### Possible fixes ####

  * igt@gem_close_race@basic-threads:
    - fi-byt-n2820:       [TIMEOUT][5] ([i915#816]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/fi-byt-n2820/igt@gem_close_race@basic-threads.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/fi-byt-n2820/igt@gem_close_race@basic-threads.html

  * igt@gem_exec_fence@basic-wait-default:
    - {fi-ehl-1}:         [INCOMPLETE][7] ([i915#937] / [i915#949]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/fi-ehl-1/igt@gem_exec_fence@basic-wait-default.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/fi-ehl-1/igt@gem_exec_fence@basic-wait-default.html

  * igt@gem_render_linear_blits@basic:
    - fi-icl-dsi:         [DMESG-WARN][9] ([i915#109]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/fi-icl-dsi/igt@gem_render_linear_blits@basic.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/fi-icl-dsi/igt@gem_render_linear_blits@basic.html

  
#### Warnings ####

  * igt@i915_selftest@live_blt:
    - fi-hsw-4770:        [DMESG-FAIL][11] ([i915#553] / [i915#725]) -> [DMESG-FAIL][12] ([i915#563])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/fi-hsw-4770/igt@i915_selftest@live_blt.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/fi-hsw-4770/igt@i915_selftest@live_blt.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
  [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
  [i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
  [i915#671]: https://gitlab.freedesktop.org/drm/intel/issues/671
  [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
  [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816
  [i915#937]: https://gitlab.freedesktop.org/drm/intel/issues/937
  [i915#949]: https://gitlab.freedesktop.org/drm/intel/issues/949


Participating hosts (43 -> 38)
------------------------------

  Additional (4): fi-byt-j1900 fi-glk-dsi fi-kbl-7500u fi-snb-2600 
  Missing    (9): fi-hsw-4200u fi-hsw-peppy fi-skl-6770hq fi-byt-squawks fi-ctg-p8600 fi-gdg-551 fi-elk-e7500 fi-kbl-7560u fi-byt-clapper 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7725 -> Patchwork_16067

  CI-20190529: 20190529
  CI_DRM_7725: 122b7c0d39d109d83b44be0ed515e53d39bfc0fa @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5364: b7cb6ffdb65cbd233f5ddee2f2dabf97b34fa640 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16067: 78fc81508a2aedd739a4e8f4d317d12a9204345d @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

78fc81508a2a drm/i915/guc: Use correct name for last CT fence
e65db0f0de6a drm/i915/guc: Update CTB helpers to use CT_ERROR
3de4fca5641b drm/i915/guc: Introduce CT_ERROR
fcb6ad56e500 drm/i915/guc: Simpler CT message size calculation

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for Misc GuC CT improvements

[Patchwork]

== Series Details ==

Series: Misc GuC CT improvements
URL   : https://patchwork.freedesktop.org/series/71927/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7725_full -> Patchwork_16067_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_16067_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_persistence@vcs1-mixed-process:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-iclb4/igt@gem_ctx_persistence@vcs1-mixed-process.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-iclb5/igt@gem_ctx_persistence@vcs1-mixed-process.html

  * igt@gem_ctx_shared@q-smoketest-vebox:
    - shard-tglb:         [PASS][3] -> [INCOMPLETE][4] ([fdo#111735])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-tglb7/igt@gem_ctx_shared@q-smoketest-vebox.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-tglb9/igt@gem_ctx_shared@q-smoketest-vebox.html

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#110854])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-iclb2/igt@gem_exec_balancer@smoke.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-iclb6/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_gttfill@basic:
    - shard-tglb:         [PASS][7] -> [INCOMPLETE][8] ([fdo#111593] / [i915#472]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-tglb4/igt@gem_exec_gttfill@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-tglb8/igt@gem_exec_gttfill@basic.html

  * igt@gem_exec_schedule@preempt-contexts-bsd2:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#109276]) +16 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-iclb4/igt@gem_exec_schedule@preempt-contexts-bsd2.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-iclb7/igt@gem_exec_schedule@preempt-contexts-bsd2.html

  * igt@gem_exec_schedule@preempt-queue-blt:
    - shard-tglb:         [PASS][11] -> [INCOMPLETE][12] ([fdo#111677] / [i915#472])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-tglb5/igt@gem_exec_schedule@preempt-queue-blt.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-tglb6/igt@gem_exec_schedule@preempt-queue-blt.html

  * igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd:
    - shard-iclb:         [PASS][13] -> [SKIP][14] ([fdo#112146])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-iclb3/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-iclb2/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd.html

  * igt@gem_exec_schedule@smoketest-bsd2:
    - shard-tglb:         [PASS][15] -> [INCOMPLETE][16] ([i915#472] / [i915#707])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-tglb2/igt@gem_exec_schedule@smoketest-bsd2.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-tglb6/igt@gem_exec_schedule@smoketest-bsd2.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-tglb:         [PASS][17] -> [INCOMPLETE][18] ([i915#472]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-tglb4/igt@gem_exec_suspend@basic-s0.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-tglb6/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_persistent_relocs@forked-interruptible-thrashing:
    - shard-kbl:          [PASS][19] -> [FAIL][20] ([i915#520])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-kbl3/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-kbl7/igt@gem_persistent_relocs@forked-interruptible-thrashing.html

  * igt@gem_ppgtt@blt-vs-render-ctxn:
    - shard-tglb:         [PASS][21] -> [INCOMPLETE][22] ([i915#470] / [i915#475])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-tglb4/igt@gem_ppgtt@blt-vs-render-ctxn.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-tglb6/igt@gem_ppgtt@blt-vs-render-ctxn.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-glk:          [PASS][23] -> [FAIL][24] ([i915#644])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-glk3/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-glk9/igt@gem_ppgtt@flink-and-close-vma-leak.html
    - shard-skl:          [PASS][25] -> [FAIL][26] ([i915#644])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-skl10/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-skl2/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@i915_pm_rps@reset:
    - shard-iclb:         [PASS][27] -> [FAIL][28] ([i915#413])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-iclb2/igt@i915_pm_rps@reset.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-iclb8/igt@i915_pm_rps@reset.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [PASS][29] -> [FAIL][30] ([i915#79])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-skl6/igt@kms_flip@flip-vs-expired-vblank.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-skl10/igt@kms_flip@flip-vs-expired-vblank.html
    - shard-glk:          [PASS][31] -> [FAIL][32] ([i915#79])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-glk8/igt@kms_flip@flip-vs-expired-vblank.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-glk3/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@plain-flip-fb-recreate:
    - shard-skl:          [PASS][33] -> [FAIL][34] ([i915#34])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-skl1/igt@kms_flip@plain-flip-fb-recreate.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-skl4/igt@kms_flip@plain-flip-fb-recreate.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite:
    - shard-tglb:         [PASS][35] -> [FAIL][36] ([i915#49])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-apl:          [PASS][37] -> [DMESG-WARN][38] ([i915#180]) +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-apl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_psr@psr2_cursor_plane_move:
    - shard-iclb:         [PASS][39] -> [SKIP][40] ([fdo#109441]) +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-iclb8/igt@kms_psr@psr2_cursor_plane_move.html

  * igt@kms_setmode@basic:
    - shard-skl:          [PASS][41] -> [FAIL][42] ([i915#31])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-skl2/igt@kms_setmode@basic.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-skl1/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [PASS][43] -> [DMESG-WARN][44] ([i915#180]) +7 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@perf_pmu@busy-no-semaphores-vcs1:
    - shard-iclb:         [PASS][45] -> [SKIP][46] ([fdo#112080]) +8 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-iclb2/igt@perf_pmu@busy-no-semaphores-vcs1.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-iclb8/igt@perf_pmu@busy-no-semaphores-vcs1.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@vecs0-s3:
    - shard-iclb:         [DMESG-WARN][47] ([fdo#111764]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-iclb3/igt@gem_ctx_isolation@vecs0-s3.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-iclb3/igt@gem_ctx_isolation@vecs0-s3.html

  * igt@gem_ctx_persistence@vcs1-mixed:
    - shard-iclb:         [SKIP][49] ([fdo#109276] / [fdo#112080]) -> [PASS][50] +2 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-iclb6/igt@gem_ctx_persistence@vcs1-mixed.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-iclb2/igt@gem_ctx_persistence@vcs1-mixed.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [SKIP][51] ([fdo#110841]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_exec_parallel@basic:
    - shard-tglb:         [INCOMPLETE][53] ([i915#472] / [i915#476]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-tglb6/igt@gem_exec_parallel@basic.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-tglb5/igt@gem_exec_parallel@basic.html

  * igt@gem_exec_parallel@vecs0:
    - shard-tglb:         [INCOMPLETE][55] ([fdo#111736] / [i915#472]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-tglb1/igt@gem_exec_parallel@vecs0.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-tglb4/igt@gem_exec_parallel@vecs0.html

  * igt@gem_exec_schedule@pi-common-bsd:
    - shard-iclb:         [SKIP][57] ([i915#677]) -> [PASS][58] +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-iclb4/igt@gem_exec_schedule@pi-common-bsd.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-iclb5/igt@gem_exec_schedule@pi-common-bsd.html

  * igt@gem_exec_schedule@preempt-queue-contexts-bsd1:
    - shard-tglb:         [INCOMPLETE][59] ([fdo#111606] / [fdo#111677] / [i915#472]) -> [PASS][60] +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-bsd1.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-tglb2/igt@gem_exec_schedule@preempt-queue-contexts-bsd1.html

  * igt@gem_exec_schedule@promotion-bsd1:
    - shard-iclb:         [SKIP][61] ([fdo#109276]) -> [PASS][62] +13 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-iclb7/igt@gem_exec_schedule@promotion-bsd1.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-iclb2/igt@gem_exec_schedule@promotion-bsd1.html

  * igt@gem_exec_schedule@reorder-wide-bsd:
    - shard-iclb:         [SKIP][63] ([fdo#112146]) -> [PASS][64] +5 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-iclb2/igt@gem_exec_schedule@reorder-wide-bsd.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-iclb8/igt@gem_exec_schedule@reorder-wide-bsd.html

  * igt@gem_persistent_relocs@forked-thrashing:
    - shard-apl:          [INCOMPLETE][65] ([CI#80] / [fdo#103927]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-apl2/igt@gem_persistent_relocs@forked-thrashing.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-apl7/igt@gem_persistent_relocs@forked-thrashing.html
    - shard-skl:          [TIMEOUT][67] ([fdo#112271] / [i915#530]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-skl3/igt@gem_persistent_relocs@forked-thrashing.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-skl6/igt@gem_persistent_relocs@forked-thrashing.html

  * igt@gem_sync@basic-all:
    - shard-tglb:         [INCOMPLETE][69] ([i915#470] / [i915#472]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-tglb9/igt@gem_sync@basic-all.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-tglb2/igt@gem_sync@basic-all.html

  * igt@gem_tiled_blits@interruptible:
    - shard-tglb:         [INCOMPLETE][71] -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-tglb1/igt@gem_tiled_blits@interruptible.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-tglb4/igt@gem_tiled_blits@interruptible.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-iclb:         [FAIL][73] ([i915#454]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-iclb2/igt@i915_pm_dc@dc6-dpms.html

  * igt@kms_color@pipe-b-ctm-negative:
    - shard-skl:          [DMESG-WARN][75] ([i915#109]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-skl7/igt@kms_color@pipe-b-ctm-negative.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-skl10/igt@kms_color@pipe-b-ctm-negative.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-skl:          [INCOMPLETE][77] ([i915#221]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-skl7/igt@kms_flip@flip-vs-suspend.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-skl10/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@plain-flip-ts-check-interruptible:
    - shard-skl:          [FAIL][79] ([i915#34]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-skl6/igt@kms_flip@plain-flip-ts-check-interruptible.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-skl2/igt@kms_flip@plain-flip-ts-check-interruptible.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
    - shard-tglb:         [FAIL][81] ([i915#49]) -> [PASS][82] +2 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [DMESG-WARN][83] ([i915#180]) -> [PASS][84] +5 similar issues
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-apl:          [DMESG-WARN][85] ([i915#180]) -> [PASS][86] +2 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          [FAIL][87] ([fdo#108145]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][89] ([fdo#108145] / [i915#265]) -> [PASS][90]
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [SKIP][91] ([fdo#109642] / [fdo#111068]) -> [PASS][92]
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-iclb6/igt@kms_psr2_su@frontbuffer.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-iclb2/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_dpms:
    - shard-iclb:         [SKIP][93] ([fdo#109441]) -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-iclb3/igt@kms_psr@psr2_dpms.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-iclb2/igt@kms_psr@psr2_dpms.html

  * igt@perf_pmu@idle-vcs1:
    - shard-iclb:         [SKIP][95] ([fdo#112080]) -> [PASS][96] +6 similar issues
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-iclb7/igt@perf_pmu@idle-vcs1.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-iclb2/igt@perf_pmu@idle-vcs1.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv-switch:
    - shard-iclb:         [SKIP][97] ([fdo#109276] / [fdo#112080]) -> [FAIL][98] ([IGT#28])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-iclb8/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html

  * igt@gem_ctx_isolation@vcs2-clean:
    - shard-tglb:         [SKIP][99] ([fdo#111912] / [fdo#112080]) -> [SKIP][100] ([fdo#112080])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-tglb5/igt@gem_ctx_isolation@vcs2-clean.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-tglb9/igt@gem_ctx_isolation@vcs2-clean.html

  * igt@gem_ctx_isolation@vcs2-nonpriv:
    - shard-tglb:         [SKIP][101] ([fdo#112080]) -> [SKIP][102] ([fdo#111912] / [fdo#112080])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-tglb9/igt@gem_ctx_isolation@vcs2-nonpriv.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-tglb5/igt@gem_ctx_isolation@vcs2-nonpriv.html

  * igt@kms_atomic_transition@6x-modeset-transitions-fencing:
    - shard-tglb:         [SKIP][103] ([fdo#112021]) -> [SKIP][104] ([fdo#112016] / [fdo#112021])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-tglb9/igt@kms_atomic_transition@6x-modeset-transitions-fencing.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-tglb5/igt@kms_atomic_transition@6x-modeset-transitions-fencing.html

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         [DMESG-WARN][105] ([fdo#107724]) -> [SKIP][106] ([fdo#109349])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7725/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/shard-iclb8/igt@kms_dp_dsc@basic-dsc-enable-edp.html

  
  [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
  [IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
  [fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606
  [fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
  [fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
  [fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
  [fdo#111912]: https://bugs.freedesktop.org/show_bug.cgi?id=111912
  [fdo#112016]: https://bugs.freedesktop.org/show_bug.cgi?id=112016
  [fdo#112021]: https://bugs.freedesktop.org/show_bug.cgi?id=112021
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
  [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
  [i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470
  [i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
  [i915#475]: https://gitlab.freedesktop.org/drm/intel/issues/475
  [i915#476]: https://gitlab.freedesktop.org/drm/intel/issues/476
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#520]: https://gitlab.freedesktop.org/drm/intel/issues/520
  [i915#530]: https://gitlab.freedesktop.org/drm/intel/issues/530
  [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
  [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
  [i915#707]: https://gitlab.freedesktop.org/drm/intel/issues/707
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79


Participating hosts (10 -> 11)
------------------------------

  Additional (1): pig-hsw-4770r 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7725 -> Patchwork_16067

  CI-20190529: 20190529
  CI_DRM_7725: 122b7c0d39d109d83b44be0ed515e53d39bfc0fa @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5364: b7cb6ffdb65cbd233f5ddee2f2dabf97b34fa640 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16067: 78fc81508a2aedd739a4e8f4d317d12a9204345d @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16067/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx