Re: [PATCH] drm/i915/perf: fix ICL perf register offsets

[Lionel Landwerlin <lionel.g.landwerlin@intel.com>]

On 10/06/2019 18:25, Kenneth Graunke wrote:
> On Monday, June 10, 2019 1:19:14 AM PDT Lionel Landwerlin wrote:
>> We got the wrong offsets (could they have changed?). New values were
>> computed off an error state by looking up the register offset in the
>> context image as written by the HW.
>>
>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> Fixes: 1de401c08fa805 ("drm/i915/perf: enable perf support on ICL")
>> ---
>>   drivers/gpu/drm/i915/i915_perf.c | 10 +++++++---
>>   1 file changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
>> index 4a767087de27..6c85191fc6c9 100644
>> --- a/drivers/gpu/drm/i915/i915_perf.c
>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>> @@ -3612,9 +3612,13 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
>>   			dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set;
>>   			dev_priv->perf.oa.ops.disable_metric_set = gen10_disable_metric_set;
>>   
>> -			dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128;
>> -			dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de;
>> -
>> +			if (IS_GEN(dev_priv, 10)) {
>> +				dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128;
>> +				dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de;
>> +			} else {
>> +				dev_priv->perf.oa.ctx_oactxctrl_offset = 0x124;
>> +				dev_priv->perf.oa.ctx_flexeu0_offset = 0x78e;
>> +			}
>>   			dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
>>   		}
>>   	}
>>
> Sounds believable.
>
> Acked-by: Kenneth Graunke <kenneth@whitecape.org>

Thanks Ken.


This was confirmed to fix the issue seen in performance queries.

Is a Acked-by enough to land this?

Could someone else maybe review?


Thanks a lot,

-Lionel

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