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From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
To: Kenneth Graunke <kenneth@whitecape.org>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/perf: fix ICL perf register offsets
Date: Mon, 17 Jun 2019 20:23:42 +0300	[thread overview]
Message-ID: <2a7ebfb1-02ac-ae1c-84fc-8971d5866bad@intel.com> (raw)
In-Reply-To: <b3f2f339-2108-a1ff-c319-130c47fb16b5@intel.com>

On 12/06/2019 09:53, Lionel Landwerlin wrote:
> On 10/06/2019 18:25, Kenneth Graunke wrote:
>> On Monday, June 10, 2019 1:19:14 AM PDT Lionel Landwerlin wrote:
>>> We got the wrong offsets (could they have changed?). New values were
>>> computed off an error state by looking up the register offset in the
>>> context image as written by the HW.
>>>
>>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>>> Fixes: 1de401c08fa805 ("drm/i915/perf: enable perf support on ICL")
>>> ---
>>>   drivers/gpu/drm/i915/i915_perf.c | 10 +++++++---
>>>   1 file changed, 7 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_perf.c 
>>> b/drivers/gpu/drm/i915/i915_perf.c
>>> index 4a767087de27..6c85191fc6c9 100644
>>> --- a/drivers/gpu/drm/i915/i915_perf.c
>>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>>> @@ -3612,9 +3612,13 @@ void i915_perf_init(struct drm_i915_private 
>>> *dev_priv)
>>>               dev_priv->perf.oa.ops.enable_metric_set = 
>>> gen8_enable_metric_set;
>>>               dev_priv->perf.oa.ops.disable_metric_set = 
>>> gen10_disable_metric_set;
>>>   -            dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128;
>>> -            dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de;
>>> -
>>> +            if (IS_GEN(dev_priv, 10)) {
>>> +                dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128;
>>> +                dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de;
>>> +            } else {
>>> +                dev_priv->perf.oa.ctx_oactxctrl_offset = 0x124;
>>> +                dev_priv->perf.oa.ctx_flexeu0_offset = 0x78e;
>>> +            }
>>>               dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
>>>           }
>>>       }
>>>
>> Sounds believable.
>>
>> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
>
> Thanks Ken.
>
>
> This was confirmed to fix the issue seen in performance queries.
>
> Is a Acked-by enough to land this?
>
> Could someone else maybe review?
>
>
> Thanks a lot,
>
> -Lionel
>
Ping?

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  reply	other threads:[~2019-06-17 17:23 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-10  8:19 [PATCH] drm/i915/perf: fix ICL perf register offsets Lionel Landwerlin
2019-06-10 12:39 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-06-10 15:25 ` [PATCH] " Kenneth Graunke
2019-06-12  6:53   ` Lionel Landwerlin
2019-06-17 17:23     ` Lionel Landwerlin [this message]
2019-06-11  4:00 ` ✓ Fi.CI.IGT: success for " Patchwork
2019-06-25 19:15 ` [PATCH] " Umesh Nerlige Ramappa

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