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From: Chris Wilson <chris@chris-wilson.co.uk>
To: Carl Worth <cworth@cworth.org>, intel-gfx@lists.freedesktop.org
Subject: Re: [bisected] commit 176f28eb breaks my Sandybridge
Date: Thu, 04 Nov 2010 23:41:45 +0000	[thread overview]
Message-ID: <b9dded$h02sp9@orsmga002.jf.intel.com> (raw)
In-Reply-To: <87k4kspu7i.fsf@yoom.home.cworth.org>

On Thu, 04 Nov 2010 16:03:45 -0700, Carl Worth <cworth@cworth.org> wrote:
> The commit below causes my Sandybridge system to fail at initial KMS
> initialization:
> 
> Aug 27 18:58:04 livid kernel: [    9.099032] i915 0000:00:02.0: irq 42 for MSI/M
> SI-X
> Aug 27 18:58:04 livid kernel: [    9.099086] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 00000000 head 00000000 tail 00000000 start 00000000
> 
> Chris, what can I do to help debug what the correct solution is here?

Find a hw engineer, and ask him nicely why his ringbuffer registers return
0 *most* of the time. You can comment out the check as we have a
workaround in place (auto-reporting of the HEAD) and under certain
circumstances /sys/kernel/debug/dri/0/i915_*ringbuffer_info do report the
correct values. I haven't worked out when they do report the correct
values, it appears to be only when the rings themselves are busy (but not
always). Having the error there was to make sure people noticed and I
could find out just how many SNB revisions failed. I presume you have a
rev 8?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

  reply	other threads:[~2010-11-04 23:41 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-11-04 23:03 [bisected] commit 176f28eb breaks my Sandybridge Carl Worth
2010-11-04 23:41 ` Chris Wilson [this message]
2010-11-04 23:52   ` Carl Worth
2010-11-07 13:09     ` Zhenyu Wang
2010-11-07 13:22       ` Chris Wilson

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