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From: Animesh Manna <animesh.manna@intel.com>
To: "Sharma, Shashank" <shashank.sharma@intel.com>,
	intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>
Subject: Re: [PATCH v3 05/11] drm/i915/dsb: Register definition of DSB registers.
Date: Thu, 29 Aug 2019 18:54:12 +0530	[thread overview]
Message-ID: <bf71bf10-aab7-8b92-1ef5-566a4c8f991a@intel.com> (raw)
In-Reply-To: <55e0f2a6-08f3-2a63-ff83-c2129fd3e80f@intel.com>

Hi,


On 8/28/2019 10:32 PM, Sharma, Shashank wrote:
>
> On 8/28/2019 12:40 AM, Animesh Manna wrote:
>> Added key register definitions of DSB.
>>
>> dsb-ctrl register is required to enable dsb-engine.
>>
>> head-ptr register hold the head of buffer address from where the
>> execution will start.
>>
>> Programming tail-ptr register is a trigger point to start execution.
>>
>> Cc: Uma Shankar <uma.shankar@intel.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++++++
>>   1 file changed, 15 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 02e1ef10c47e..71c6c2380443 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -11564,4 +11564,19 @@ enum skl_power_gate {
>>   #define PORT_TX_DFLEXDPCSSS(fia)        _MMIO_FIA((fia), 0x00894)
>>   #define   DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)        (1 << (tc_port))
>>   +/* This register controls the Display State Buffer (DSB) engines. */
>> +#define _DSBSL_INSTANCE_BASE        0x70B00
>> +#define DSBSL_INSTANCE(pipe, id)    (_DSBSL_INSTANCE_BASE + \
>> +                     (pipe) * 0x1000 + (id) * 100)
>> +#define DSB_HEAD(pipe, id)        _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
>> +#define DSB_TAIL(pipe, id)        _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
>> +#define DSB_CTRL(pipe, id)        _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
>> +#define   DSB_ENABLE            (1 << 31)
>> +#define   DSB_BUFFER_REITERATE        (1 << 29)
>> +#define   DSB_WAIT_FOR_VBLANK        (1 << 28)
>> +#define   DSB_WAIT_FOR_LINE_IN_RANGE    (1 << 27)
>> +#define   DSB_HALT            (1 << 16)
>> +#define   DSB_NON_POSTED_ENABLE        (1 << 8)
>> +#define   DSB_STATUS            (1 << 0)
>> +
>
> Again, this patch is just adding the header definitions, please merge 
> this patch in the patch where these definitions are being used.

Ok.

Regards,
Animesh
>
> - Shashank
>
>>   #endif /* _I915_REG_H_ */

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  reply	other threads:[~2019-08-29 13:24 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-27 19:10 [PATCH v3 00/11] DSB enablement Animesh Manna
2019-08-27 19:10 ` [PATCH v3 01/11] drm/i915/dsb: feature flag added for display state buffer Animesh Manna
2019-08-28 14:01   ` Sharma, Shashank
2019-08-29  7:10     ` Animesh Manna
2019-08-27 19:10 ` [PATCH v3 02/11] drm/i915/dsb: DSB context creation Animesh Manna
2019-08-28 14:39   ` Sharma, Shashank
2019-08-29 10:40     ` Animesh Manna
2019-08-27 19:10 ` [PATCH v3 03/11] drm/i915/dsb: single register write function for DSB Animesh Manna
2019-08-28 15:16   ` Sharma, Shashank
2019-08-29 13:09     ` Animesh Manna
2019-08-27 19:10 ` [PATCH v3 04/11] drm/i915/dsb: Indexed " Animesh Manna
2019-08-28 16:46   ` Sharma, Shashank
2019-08-29 13:23     ` Animesh Manna
2019-08-27 19:10 ` [PATCH v3 05/11] drm/i915/dsb: Register definition of DSB registers Animesh Manna
2019-08-28 17:02   ` Sharma, Shashank
2019-08-29 13:24     ` Animesh Manna [this message]
2019-08-27 19:10 ` [PATCH v3 06/11] drm/i915/dsb: Check DSB engine status Animesh Manna
2019-08-27 19:10 ` [PATCH v3 07/11] drm/i915/dsb: functions to enable/disable DSB engine Animesh Manna
2019-08-28 17:07   ` Sharma, Shashank
2019-08-29 13:45     ` Animesh Manna
2019-08-27 19:10 ` [PATCH v3 08/11] drm/i915/dsb: function to trigger workload execution of DSB Animesh Manna
2019-08-28 17:21   ` Sharma, Shashank
2019-08-27 19:10 ` [PATCH v3 09/11] drm/i915/dsb: Documentation for DSB Animesh Manna
2019-08-28 17:23   ` Sharma, Shashank
2019-08-27 19:10 ` [PATCH v3 10/11] drm/i915/dsb: Enable gamma lut programming using DSB Animesh Manna
2019-08-28 18:15   ` Sharma, Shashank
2019-08-29 13:48     ` Animesh Manna
2019-08-27 19:10 ` [PATCH v3 11/11] drm/i915/dsb: Enable DSB for gen12 Animesh Manna
2019-08-27 19:44 ` ✗ Fi.CI.CHECKPATCH: warning for DSB enablement. (rev3) Patchwork
2019-08-27 19:45 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-08-27 20:11 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-29  9:17 ` ✓ Fi.CI.IGT: " Patchwork

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