From: "Teres Alexis, Alan Previn" <alan.previn.teres.alexis@intel.com>
To: "Ceraolo Spurio, Daniele" <daniele.ceraolospurio@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v2 1/7] drm/i915/pxp: Make gt and pxp init/fini aware of PXP-owning-GT
Date: Fri, 21 Oct 2022 08:16:57 +0000 [thread overview]
Message-ID: <c910350b310179948deed7e8f7f636fecb9c5a85.camel@intel.com> (raw)
In-Reply-To: <ca3929d15d31d18f5aa95b8612a7dc5e62932e08.camel@intel.com>
On Mon, 2022-10-17 at 10:03 -0700, Alan Previn Teres Alexis wrote:
> >
> > On Thu, 2022-10-13 at 13:48 -0700, Ceraolo Spurio, Daniele wrote:
> > > >
> > > > On 10/5/2022 9:38 PM, Alan Previn wrote:
> > > > > > In preparation for future MTL-PXP feature support, PXP control
> > > > > > context should only valid on the correct gt tile. Depending on the
> > > > > > device-info this mat not necessarily be the root GT tile and
> > > > > > depends on which tile owns the VEBOX and KCR.
> > > > > >
> > Alan:[snip]
> > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > > > > index b367cfff48d5..e61f6c5ed440 100644
> > > > > > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > > > > @@ -850,6 +850,10 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
> > > > > > gt->name = "Primary GT";
> > > > > > gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
> > > > > >
> > > > > > + /* device config determines which GT owns the global pxp-tee context */
> > > > > > + if (VDBOX_MASK(gt) && !INTEL_INFO(i915)->has_nonroot_pxpgt)
> > > > > > + gt->pxptee_iface_owner = true;
> > > > > > +
> > > >
> > > > I'm not convinced that we need dedicated has_nonroot_pxpgt and
> > > > pxptee_iface_owner flags. MTL moves the GSC inside a GT and the owner of
> > > > PXP is the GT where the GSC engine resides. So we could have a checker like:
> > > >
> > > > bool intel_pxp_supported(struct intel_gt *gt)
> > > > {
> > > > /* we only support HECI PXP from the root GT */
> > > > if (HAS_HECI_PXP(gt->i915))
> > > > return gt_is_root(gt);
> > > >
> > > > return HAS_ENGINE(gt, GSC);
> > > > }
> > > >
> > > > I'm aware that the GSC engine code is still not available, but we can
> > > > special case for MTL for now and then replace it when the GSC code lands:
> > > >
> > > > bool intel_pxp_supported(struct intel_gt *gt)
> > > > {
> > > > /* we only support HECI PXP from the root GT */
> > > > if (HAS_HECI_PXP(gt->i915))
> > > > return gt_is_root(gt);
> > > >
> > > > /* TODO: replace with GSC check */
> > > > return IS_METEORLAKE(gt->i915) && !gt_is_root(gt);
> > > > }
> > > >
> > > > Then we can use intel_pxp_supported(gt) instead of
> > > > gt->pxptee_iface_owner and we can drop has_nonroot_pxpgt. Might also be
> > > > worth merging this with HAS_PXP for a unified check, but that can come
> > > > later.
> > > >
> > > > Daniele
> >
> > As per offline conversations, we know above combination may not work for the DG2 case, but i'll go ahead and re-rev this
> > after i look for another way to avoid creating another device info variable- i'll try to get a karnaugh map going to
> > ensure we have a good combination of existing device-config info that are reliable for all current and MTL usages else
> > we may need a new device-config after all (maybe a better named one if needed).
Alan: Looks like the original intel_pxp_init (with only the change to HAS_PXP to take in gt as input) might be
sufficient for all cases we have with today's hw - without the need for the pxptee_iface_owner or has_nonroot_pxpgt:
* for HW without PXP/GSC-HuC-Authent: will fail on either HAS_PXP and _gt_needs_teelink
* for adl/tgl: HAS_PXP will PASS
* for dg2: HAS_PXP will fail, but _gt_needs_teelink will pass
* for mtl: HAS_PXP will pass for 2nd tile only due to VDBOX mask
the only open would be if kernel was being built without CONFIG_MEI_PXP and we are running on MTL
so that might require some "TODO .. MTL..." comments
next prev parent reply other threads:[~2022-10-21 8:17 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-06 4:38 [Intel-gfx] [PATCH v2 0/7] drm/i915/pxp: Prepare intel_pxp entry points for MTL Alan Previn
2022-10-06 4:38 ` [Intel-gfx] [PATCH v2 1/7] drm/i915/pxp: Make gt and pxp init/fini aware of PXP-owning-GT Alan Previn
2022-10-13 20:48 ` Ceraolo Spurio, Daniele
2022-10-17 17:01 ` Teres Alexis, Alan Previn
2022-10-21 3:54 ` Teres Alexis, Alan Previn
2022-10-21 8:16 ` Teres Alexis, Alan Previn [this message]
2022-10-06 4:38 ` [Intel-gfx] [PATCH v2 2/7] drm/i915/pxp: Make intel_pxp_is_enabled implicitly sort PXP-owning-GT Alan Previn
2022-10-13 21:10 ` Ceraolo Spurio, Daniele
2022-10-17 17:12 ` Teres Alexis, Alan Previn
2022-10-06 4:38 ` [Intel-gfx] [PATCH v2 3/7] drm/i915/pxp: Make intel_pxp_is_active " Alan Previn
2022-10-06 4:38 ` [Intel-gfx] [PATCH v2 4/7] drm/i915/pxp: Make PXP tee component bind/unbind aware of PXP-owning-GT Alan Previn
2022-10-06 4:38 ` [Intel-gfx] [PATCH v2 5/7] drm/i915/pxp: Make intel_pxp_start implicitly sort PXP-owning-GT Alan Previn
2022-10-06 4:38 ` [Intel-gfx] [PATCH v2 6/7] drm/i915/pxp: Make intel_pxp_key_check " Alan Previn
2022-10-06 4:38 ` [Intel-gfx] [PATCH v2 7/7] drm/i915/pxp: Make intel_pxp power management " Alan Previn
2022-10-21 16:29 ` Teres Alexis, Alan Previn
2022-10-06 5:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/pxp: Prepare intel_pxp entry points for MTL (rev2) Patchwork
2022-10-06 5:09 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-06 5:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-06 18:19 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-10-10 19:05 ` Teres Alexis, Alan Previn
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