Re: [Intel-gfx] [PATCH v6 6/6] drm: Add arch arm64 for drm_clflush_virt_range

[Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>]

On 07/02/2022 20:11, Michael Cheng wrote:
> Use flush_tlb_kernel_range when invoking drm_clflush_virt_range on
> arm64 platforms. Using flush_tlb_kernel_range will:
> 
> 1. Make sure prior page-table updates have been completed
> 2. Invalidate the TLB
> 3. Check if the TLB invalidation has been completed

Arm does not have a clflush equivalent but invalidating TLBs there 
includes flushing caches?

Regards,

Tvrtko

> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
> ---
>   drivers/gpu/drm/drm_cache.c | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
> index f19d9acbe959..d2506060a7c8 100644
> --- a/drivers/gpu/drm/drm_cache.c
> +++ b/drivers/gpu/drm/drm_cache.c
> @@ -176,6 +176,10 @@ drm_clflush_virt_range(void *addr, unsigned long length)
>   
>   	if (wbinvd_on_all_cpus())
>   		pr_err("Timed out waiting for cache flush\n");
> +
> +#elif defined(CONFIG_ARM64)
> +	void *end = addr + length;
> +	flush_tlb_kernel_range(*addr, *end);
>   #else
>   	pr_err("Architecture has no drm_cache.c support\n");
>   	WARN_ON_ONCE(1);