[PATCH v2 0/7] drm/i915/dp: link config compute refactoring

[PATCH v2 0/7] drm/i915/dp: link config compute refactoring

[Jani Nikula]

v2 of https://patchwork.freedesktop.org/series/41215/

Jani Nikula (7):
  drm/i915/dp: remove stale comment about bw constants
  drm/i915/dp: move link_bw and rate_select debugging where used
  drm/i915/dp: abstract dp link config computation from the rest
  drm/i915/dp: move eDP VBT bpp clamping code to intel_dp_compute_bpp()
  drm/i915/dp: group link config limits in a struct
  drm/i915/dp: abstract link config selection
  drm/i915/dp: fix compliance test adjustments

 drivers/gpu/drm/i915/intel_dp.c               | 277 +++++++++++++++-----------
 drivers/gpu/drm/i915/intel_dp_link_training.c |   5 +
 2 files changed, 169 insertions(+), 113 deletions(-)

-- 
2.11.0

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[PATCH v2 1/7] drm/i915/dp: remove stale comment about bw constants

[Jani Nikula]

We haven't used the DP bw constants here for a while. No functional
changes.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 62f82c4298ac..5f4b30faf6a2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1701,7 +1701,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	int lane_count, clock;
 	int min_lane_count = 1;
 	int max_lane_count = intel_dp_max_lane_count(intel_dp);
-	/* Conveniently, the link BW constants become indices with a shift...*/
 	int min_clock = 0;
 	int max_clock;
 	int bpp, mode_rate;
-- 
2.11.0

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[PATCH v2 2/7] drm/i915/dp: move link_bw and rate_select debugging where used

[Jani Nikula]

We call intel_dp_compute_rate() in intel_dp_compute_config() only to be
able to debug log the link_bw and rate_select parameters; we don't use
the parameters here for anything else. We call intel_dp_compute_rate()
again during link training where we actually need and use the
parameters.

Move the debug logging of link_bw and rate_select to
intel_dp_link_training_clock_recovery(), and clean up the extra
intel_dp_compute_rate() call and extra clutter from the already
overcrowded intel_dp_compute_config().

v2: Rewrote commit message (Rodrigo, Manasi)

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c               | 9 ++-------
 drivers/gpu/drm/i915/intel_dp_link_training.c | 5 +++++
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5f4b30faf6a2..81cf363e71af 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1706,7 +1706,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	int bpp, mode_rate;
 	int link_avail, link_clock;
 	int common_len;
-	uint8_t link_bw, rate_select;
 	bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
 					   DP_DPCD_QUIRK_LIMITED_M_N);
 
@@ -1852,12 +1851,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	pipe_config->pipe_bpp = bpp;
 	pipe_config->port_clock = intel_dp->common_rates[clock];
 
-	intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
-			      &link_bw, &rate_select);
-
-	DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
-		      link_bw, rate_select, pipe_config->lane_count,
-		      pipe_config->port_clock, bpp);
+	DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
+		      pipe_config->lane_count, pipe_config->port_clock, bpp);
 	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 		      mode_rate, link_avail);
 
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
index f59b59bb0a21..3fcaa98b9055 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -139,6 +139,11 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 	intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
 			      &link_bw, &rate_select);
 
+	if (link_bw)
+		DRM_DEBUG_KMS("Using LINK_BW_SET value %02x\n", link_bw);
+	else
+		DRM_DEBUG_KMS("Using LINK_RATE_SET value %02x\n", rate_select);
+
 	/* Write the link configuration data */
 	link_config[0] = link_bw;
 	link_config[1] = intel_dp->lane_count;
-- 
2.11.0

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[PATCH v2 3/7] drm/i915/dp: abstract dp link config computation from the rest

[Jani Nikula]

Abstract a new intel_dp_compute_link_config() from
intel_dp_compute_config(), with the parts related to link configuration,
i.e. bpp, link rate, and lane count selection. No functional changes.

v2: Fix a checkpatch warn about spacing.

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 161 ++++++++++++++++++++++------------------
 1 file changed, 88 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 81cf363e71af..81da96b9ef33 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1685,19 +1685,14 @@ static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
 	return bres;
 }
 
-bool
-intel_dp_compute_config(struct intel_encoder *encoder,
-			struct intel_crtc_state *pipe_config,
-			struct drm_connector_state *conn_state)
+static bool
+intel_dp_compute_link_config(struct intel_encoder *encoder,
+			     struct intel_crtc_state *pipe_config)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
-	enum port port = encoder->port;
-	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
-	struct intel_digital_connector_state *intel_conn_state =
-		to_intel_digital_connector_state(conn_state);
 	int lane_count, clock;
 	int min_lane_count = 1;
 	int max_lane_count = intel_dp_max_lane_count(intel_dp);
@@ -1706,9 +1701,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	int bpp, mode_rate;
 	int link_avail, link_clock;
 	int common_len;
-	bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
-					   DP_DPCD_QUIRK_LIMITED_M_N);
-
 	common_len = intel_dp_common_len_rate_limit(intel_dp,
 						    intel_dp->max_link_rate);
 
@@ -1717,51 +1709,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
 	max_clock = common_len - 1;
 
-	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
-		pipe_config->has_pch_encoder = true;
-
-	pipe_config->has_drrs = false;
-	if (IS_G4X(dev_priv) || port == PORT_A)
-		pipe_config->has_audio = false;
-	else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
-		pipe_config->has_audio = intel_dp->has_audio;
-	else
-		pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
-
-	if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
-		struct drm_display_mode *panel_mode =
-			intel_connector->panel.alt_fixed_mode;
-		struct drm_display_mode *req_mode = &pipe_config->base.mode;
-
-		if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
-			panel_mode = intel_connector->panel.fixed_mode;
-
-		drm_mode_debug_printmodeline(panel_mode);
-
-		intel_fixed_panel_mode(panel_mode, adjusted_mode);
-
-		if (INTEL_GEN(dev_priv) >= 9) {
-			int ret;
-			ret = skl_update_scaler_crtc(pipe_config);
-			if (ret)
-				return ret;
-		}
-
-		if (HAS_GMCH_DISPLAY(dev_priv))
-			intel_gmch_panel_fitting(intel_crtc, pipe_config,
-						 conn_state->scaling_mode);
-		else
-			intel_pch_panel_fitting(intel_crtc, pipe_config,
-						conn_state->scaling_mode);
-	}
-
-	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
-	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
-		return false;
-
-	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
-		return false;
-
 	/* Use values requested by Compliance Test Request */
 	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
 		int index;
@@ -1831,6 +1778,83 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	return false;
 
 found:
+	pipe_config->lane_count = lane_count;
+	pipe_config->pipe_bpp = bpp;
+	pipe_config->port_clock = intel_dp->common_rates[clock];
+
+	DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
+		      pipe_config->lane_count, pipe_config->port_clock, bpp);
+	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
+		      mode_rate, link_avail);
+
+	return true;
+}
+
+bool
+intel_dp_compute_config(struct intel_encoder *encoder,
+			struct intel_crtc_state *pipe_config,
+			struct drm_connector_state *conn_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+	enum port port = encoder->port;
+	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_connector *intel_connector = intel_dp->attached_connector;
+	struct intel_digital_connector_state *intel_conn_state =
+		to_intel_digital_connector_state(conn_state);
+	bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
+					   DP_DPCD_QUIRK_LIMITED_M_N);
+
+	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
+		pipe_config->has_pch_encoder = true;
+
+	pipe_config->has_drrs = false;
+	if (IS_G4X(dev_priv) || port == PORT_A)
+		pipe_config->has_audio = false;
+	else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
+		pipe_config->has_audio = intel_dp->has_audio;
+	else
+		pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
+
+	if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
+		struct drm_display_mode *panel_mode =
+			intel_connector->panel.alt_fixed_mode;
+		struct drm_display_mode *req_mode = &pipe_config->base.mode;
+
+		if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
+			panel_mode = intel_connector->panel.fixed_mode;
+
+		drm_mode_debug_printmodeline(panel_mode);
+
+		intel_fixed_panel_mode(panel_mode, adjusted_mode);
+
+		if (INTEL_GEN(dev_priv) >= 9) {
+			int ret;
+
+			ret = skl_update_scaler_crtc(pipe_config);
+			if (ret)
+				return ret;
+		}
+
+		if (HAS_GMCH_DISPLAY(dev_priv))
+			intel_gmch_panel_fitting(intel_crtc, pipe_config,
+						 conn_state->scaling_mode);
+		else
+			intel_pch_panel_fitting(intel_crtc, pipe_config,
+						conn_state->scaling_mode);
+	}
+
+	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
+	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
+		return false;
+
+	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
+		return false;
+
+	if (!intel_dp_compute_link_config(encoder, pipe_config))
+		return false;
+
 	if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
 		/*
 		 * See:
@@ -1838,7 +1862,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 		 */
 		pipe_config->limited_color_range =
-			bpp != 18 &&
+			pipe_config->pipe_bpp != 18 &&
 			drm_default_rgb_quant_range(adjusted_mode) ==
 			HDMI_QUANTIZATION_RANGE_LIMITED;
 	} else {
@@ -1846,17 +1870,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 			intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
 	}
 
-	pipe_config->lane_count = lane_count;
-
-	pipe_config->pipe_bpp = bpp;
-	pipe_config->port_clock = intel_dp->common_rates[clock];
-
-	DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
-		      pipe_config->lane_count, pipe_config->port_clock, bpp);
-	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
-		      mode_rate, link_avail);
-
-	intel_link_compute_m_n(bpp, lane_count,
+	intel_link_compute_m_n(pipe_config->pipe_bpp, pipe_config->lane_count,
 			       adjusted_mode->crtc_clock,
 			       pipe_config->port_clock,
 			       &pipe_config->dp_m_n,
@@ -1865,11 +1879,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	if (intel_connector->panel.downclock_mode != NULL &&
 		dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
 			pipe_config->has_drrs = true;
-			intel_link_compute_m_n(bpp, lane_count,
-				intel_connector->panel.downclock_mode->clock,
-				pipe_config->port_clock,
-				&pipe_config->dp_m2_n2,
-				reduce_m_n);
+			intel_link_compute_m_n(pipe_config->pipe_bpp,
+					       pipe_config->lane_count,
+					       intel_connector->panel.downclock_mode->clock,
+					       pipe_config->port_clock,
+					       &pipe_config->dp_m2_n2,
+					       reduce_m_n);
 	}
 
 	/*
-- 
2.11.0

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[PATCH v2 4/7] drm/i915/dp: move eDP VBT bpp clamping code to intel_dp_compute_bpp()

[Jani Nikula]

Keep related things together. No functional changes.

v2: Fix a typo in patch subject, fix a checkpatch alignment warning.

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 24 +++++++++++++-----------
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 81da96b9ef33..430c206e77fc 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1650,6 +1650,8 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
 				struct intel_crtc_state *pipe_config)
 {
+	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
+	struct intel_connector *intel_connector = intel_dp->attached_connector;
 	int bpp, bpc;
 
 	bpp = pipe_config->pipe_bpp;
@@ -1665,6 +1667,17 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
 		DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
 			      pipe_config->pipe_bpp);
 	}
+
+	if (intel_dp_is_edp(intel_dp)) {
+		/* Get bpp from vbt only for panels that dont have bpp in edid */
+		if (intel_connector->base.display_info.bpc == 0 &&
+		    dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
+			DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
+				      dev_priv->vbt.edp.bpp);
+			bpp = dev_priv->vbt.edp.bpp;
+		}
+	}
+
 	return bpp;
 }
 
@@ -1689,10 +1702,8 @@ static bool
 intel_dp_compute_link_config(struct intel_encoder *encoder,
 			     struct intel_crtc_state *pipe_config)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
-	struct intel_connector *intel_connector = intel_dp->attached_connector;
 	int lane_count, clock;
 	int min_lane_count = 1;
 	int max_lane_count = intel_dp_max_lane_count(intel_dp);
@@ -1735,15 +1746,6 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 	 * bpc in between. */
 	bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
 	if (intel_dp_is_edp(intel_dp)) {
-
-		/* Get bpp from vbt only for panels that dont have bpp in edid */
-		if (intel_connector->base.display_info.bpc == 0 &&
-			(dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
-			DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
-				      dev_priv->vbt.edp.bpp);
-			bpp = dev_priv->vbt.edp.bpp;
-		}
-
 		/*
 		 * Use the maximum clock and number of lanes the eDP panel
 		 * advertizes being capable of. The panels are generally
-- 
2.11.0

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[PATCH v2 5/7] drm/i915/dp: group link config limits in a struct

[Jani Nikula]

Also use same min/max model for bpp, and adjust debug logging while at
it.

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 57 ++++++++++++++++++++++++-----------------
 1 file changed, 33 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 430c206e77fc..9ef29b63b237 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1647,6 +1647,12 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
 	}
 }
 
+struct link_config_limits {
+	int min_clock, max_clock;
+	int min_lane_count, max_lane_count;
+	int min_bpp, max_bpp;
+};
+
 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
 				struct intel_crtc_state *pipe_config)
 {
@@ -1704,21 +1710,25 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 {
 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
-	int lane_count, clock;
-	int min_lane_count = 1;
-	int max_lane_count = intel_dp_max_lane_count(intel_dp);
-	int min_clock = 0;
-	int max_clock;
-	int bpp, mode_rate;
-	int link_avail, link_clock;
+	struct link_config_limits limits;
+	int bpp, clock, lane_count;
+	int mode_rate, link_avail, link_clock;
 	int common_len;
+
 	common_len = intel_dp_common_len_rate_limit(intel_dp,
 						    intel_dp->max_link_rate);
 
 	/* No common link rates between source and sink */
 	WARN_ON(common_len <= 0);
 
-	max_clock = common_len - 1;
+	limits.min_clock = 0;
+	limits.max_clock = common_len - 1;
+
+	limits.min_lane_count = 1;
+	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
+
+	limits.min_bpp = 6 * 3;
+	limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
 
 	/* Use values requested by Compliance Test Request */
 	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
@@ -1733,18 +1743,11 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 						    intel_dp->num_common_rates,
 						    intel_dp->compliance.test_link_rate);
 			if (index >= 0)
-				min_clock = max_clock = index;
-			min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
+				limits.min_clock = limits.max_clock = index;
+			limits.min_lane_count = limits.max_lane_count = intel_dp->compliance.test_lane_count;
 		}
 	}
-	DRM_DEBUG_KMS("DP link computation with max lane count %i "
-		      "max bw %d pixel clock %iKHz\n",
-		      max_lane_count, intel_dp->common_rates[max_clock],
-		      adjusted_mode->crtc_clock);
 
-	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
-	 * bpc in between. */
-	bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
 	if (intel_dp_is_edp(intel_dp)) {
 		/*
 		 * Use the maximum clock and number of lanes the eDP panel
@@ -1753,18 +1756,24 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 		 * configuration, and typically these values correspond to the
 		 * native resolution of the panel.
 		 */
-		min_lane_count = max_lane_count;
-		min_clock = max_clock;
+		limits.min_lane_count = limits.max_lane_count;
+		limits.min_clock = limits.max_clock;
 	}
 
-	for (; bpp >= 6*3; bpp -= 2*3) {
+	DRM_DEBUG_KMS("DP link computation with max lane count %i "
+		      "max rate %d max bpp %d pixel clock %iKHz\n",
+		      limits.max_lane_count,
+		      intel_dp->common_rates[limits.max_clock],
+		      limits.max_bpp, adjusted_mode->crtc_clock);
+
+	for (bpp = limits.max_bpp; bpp >= limits.min_bpp; bpp -= 2 * 3) {
 		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 						   bpp);
 
-		for (clock = min_clock; clock <= max_clock; clock++) {
-			for (lane_count = min_lane_count;
-				lane_count <= max_lane_count;
-				lane_count <<= 1) {
+		for (clock = limits.min_clock; clock <= limits.max_clock; clock++) {
+			for (lane_count = limits.min_lane_count;
+			     lane_count <= limits.max_lane_count;
+			     lane_count <<= 1) {
 
 				link_clock = intel_dp->common_rates[clock];
 				link_avail = intel_dp_max_data_rate(link_clock,
-- 
2.11.0

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[PATCH v2 6/7] drm/i915/dp: abstract link config selection

[Jani Nikula]

For now, there's just the one link config selection, optimizing for slow
and wide link. No functional changes.

Keep the debug logging in the caller, to avoid duplication later on if
alternative link confing selection gets added.

v2: Improved commit message

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 81 +++++++++++++++++++++++++----------------
 1 file changed, 50 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9ef29b63b237..d622db76b9c3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1704,6 +1704,42 @@ static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
 	return bres;
 }
 
+/* Optimize link config in order: max bpp, min clock, min lanes */
+static bool
+intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
+				  struct intel_crtc_state *pipe_config,
+				  const struct link_config_limits *limits)
+{
+	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	int bpp, clock, lane_count;
+	int mode_rate, link_clock, link_avail;
+
+	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
+		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
+						   bpp);
+
+		for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
+			for (lane_count = limits->min_lane_count;
+			     lane_count <= limits->max_lane_count;
+			     lane_count <<= 1) {
+				link_clock = intel_dp->common_rates[clock];
+				link_avail = intel_dp_max_data_rate(link_clock,
+								    lane_count);
+
+				if (mode_rate <= link_avail) {
+					pipe_config->lane_count = lane_count;
+					pipe_config->pipe_bpp = bpp;
+					pipe_config->port_clock = link_clock;
+
+					return true;
+				}
+			}
+		}
+	}
+
+	return false;
+}
+
 static bool
 intel_dp_compute_link_config(struct intel_encoder *encoder,
 			     struct intel_crtc_state *pipe_config)
@@ -1711,8 +1747,6 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	struct link_config_limits limits;
-	int bpp, clock, lane_count;
-	int mode_rate, link_avail, link_clock;
 	int common_len;
 
 	common_len = intel_dp_common_len_rate_limit(intel_dp,
@@ -1766,37 +1800,22 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 		      intel_dp->common_rates[limits.max_clock],
 		      limits.max_bpp, adjusted_mode->crtc_clock);
 
-	for (bpp = limits.max_bpp; bpp >= limits.min_bpp; bpp -= 2 * 3) {
-		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
-						   bpp);
-
-		for (clock = limits.min_clock; clock <= limits.max_clock; clock++) {
-			for (lane_count = limits.min_lane_count;
-			     lane_count <= limits.max_lane_count;
-			     lane_count <<= 1) {
-
-				link_clock = intel_dp->common_rates[clock];
-				link_avail = intel_dp_max_data_rate(link_clock,
-								    lane_count);
-
-				if (mode_rate <= link_avail) {
-					goto found;
-				}
-			}
-		}
-	}
-
-	return false;
-
-found:
-	pipe_config->lane_count = lane_count;
-	pipe_config->pipe_bpp = bpp;
-	pipe_config->port_clock = intel_dp->common_rates[clock];
+	/*
+	 * Optimize for slow and wide. This is the place to add alternative
+	 * optimization policy.
+	 */
+	if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits))
+		return false;
 
 	DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
-		      pipe_config->lane_count, pipe_config->port_clock, bpp);
-	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
-		      mode_rate, link_avail);
+		      pipe_config->lane_count, pipe_config->port_clock,
+		      pipe_config->pipe_bpp);
+
+	DRM_DEBUG_KMS("DP link rate required %i available %i\n",
+		      intel_dp_link_required(adjusted_mode->crtc_clock,
+					     pipe_config->pipe_bpp),
+		      intel_dp_max_data_rate(pipe_config->port_clock,
+					     pipe_config->lane_count));
 
 	return true;
 }
-- 
2.11.0

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[PATCH v2 7/7] drm/i915/dp: fix compliance test adjustments

[Jani Nikula]

Abstract compliance test adjustments to a single function. Also make the
bpc adjustments affect the limits, actually forcing the bpc. Seems like
directly changing the pipe_bpp in the past could not have been
effective.

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 64 ++++++++++++++++++++++++-----------------
 1 file changed, 38 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d622db76b9c3..83da50b13d81 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1666,14 +1666,6 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
 	if (bpc > 0)
 		bpp = min(bpp, 3*bpc);
 
-	/* For DP Compliance we override the computed bpp for the pipe */
-	if (intel_dp->compliance.test_data.bpc != 0) {
-		pipe_config->pipe_bpp =	3*intel_dp->compliance.test_data.bpc;
-		pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3;
-		DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
-			      pipe_config->pipe_bpp);
-	}
-
 	if (intel_dp_is_edp(intel_dp)) {
 		/* Get bpp from vbt only for panels that dont have bpp in edid */
 		if (intel_connector->base.display_info.bpc == 0 &&
@@ -1704,6 +1696,42 @@ static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
 	return bres;
 }
 
+/* Adjust link config limits based on compliance test requests. */
+static void
+intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
+				  struct intel_crtc_state *pipe_config,
+				  struct link_config_limits *limits)
+{
+	/* For DP Compliance we override the computed bpp for the pipe */
+	if (intel_dp->compliance.test_data.bpc != 0) {
+		int bpp = 3 * intel_dp->compliance.test_data.bpc;
+
+		limits->min_bpp = limits->max_bpp = bpp;
+		pipe_config->dither_force_disable = bpp == 6 * 3;
+
+		DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
+	}
+
+	/* Use values requested by Compliance Test Request */
+	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
+		int index;
+
+		/* Validate the compliance test data since max values
+		 * might have changed due to link train fallback.
+		 */
+		if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
+					       intel_dp->compliance.test_lane_count)) {
+			index = intel_dp_rate_index(intel_dp->common_rates,
+						    intel_dp->num_common_rates,
+						    intel_dp->compliance.test_link_rate);
+			if (index >= 0)
+				limits->min_clock = limits->max_clock = index;
+			limits->min_lane_count = limits->max_lane_count =
+				intel_dp->compliance.test_lane_count;
+		}
+	}
+}
+
 /* Optimize link config in order: max bpp, min clock, min lanes */
 static bool
 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
@@ -1764,24 +1792,6 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 	limits.min_bpp = 6 * 3;
 	limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
 
-	/* Use values requested by Compliance Test Request */
-	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
-		int index;
-
-		/* Validate the compliance test data since max values
-		 * might have changed due to link train fallback.
-		 */
-		if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
-					       intel_dp->compliance.test_lane_count)) {
-			index = intel_dp_rate_index(intel_dp->common_rates,
-						    intel_dp->num_common_rates,
-						    intel_dp->compliance.test_link_rate);
-			if (index >= 0)
-				limits.min_clock = limits.max_clock = index;
-			limits.min_lane_count = limits.max_lane_count = intel_dp->compliance.test_lane_count;
-		}
-	}
-
 	if (intel_dp_is_edp(intel_dp)) {
 		/*
 		 * Use the maximum clock and number of lanes the eDP panel
@@ -1794,6 +1804,8 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 		limits.min_clock = limits.max_clock;
 	}
 
+	intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
+
 	DRM_DEBUG_KMS("DP link computation with max lane count %i "
 		      "max rate %d max bpp %d pixel clock %iKHz\n",
 		      limits.max_lane_count,
-- 
2.11.0

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✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: link config compute refactoring (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: link config compute refactoring (rev2)
URL   : https://patchwork.freedesktop.org/series/41215/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
8226b468bdc1 drm/i915/dp: remove stale comment about bw constants
77ae7b48939b drm/i915/dp: move link_bw and rate_select debugging where used
4f3c34480f92 drm/i915/dp: abstract dp link config computation from the rest
ff5c64d21d93 drm/i915/dp: move eDP VBT bpp clamping code to intel_dp_compute_bpp()
d8ade2bdaa7a drm/i915/dp: group link config limits in a struct
-:69: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#69: FILE: drivers/gpu/drm/i915/intel_dp.c:1746:
+				limits.min_clock = limits.max_clock = index;

-:70: WARNING:LONG_LINE: line over 100 characters
#70: FILE: drivers/gpu/drm/i915/intel_dp.c:1747:
+			limits.min_lane_count = limits.max_lane_count = intel_dp->compliance.test_lane_count;

-:70: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#70: FILE: drivers/gpu/drm/i915/intel_dp.c:1747:
+			limits.min_lane_count = limits.max_lane_count = intel_dp->compliance.test_lane_count;

total: 0 errors, 1 warnings, 2 checks, 96 lines checked
3f113e6072d7 drm/i915/dp: abstract link config selection
57809a508243 drm/i915/dp: fix compliance test adjustments
-:47: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#47: FILE: drivers/gpu/drm/i915/intel_dp.c:1709:
+		limits->min_bpp = limits->max_bpp = bpp;

-:66: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#66: FILE: drivers/gpu/drm/i915/intel_dp.c:1728:
+				limits->min_clock = limits->max_clock = index;

-:67: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#67: FILE: drivers/gpu/drm/i915/intel_dp.c:1729:
+			limits->min_lane_count = limits->max_lane_count =

total: 0 errors, 0 warnings, 3 checks, 88 lines checked

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✗ Fi.CI.SPARSE: warning for drm/i915/dp: link config compute refactoring (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: link config compute refactoring (rev2)
URL   : https://patchwork.freedesktop.org/series/41215/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/dp: remove stale comment about bw constants
Okay!

Commit: drm/i915/dp: move link_bw and rate_select debugging where used
Okay!

Commit: drm/i915/dp: abstract dp link config computation from the rest
Okay!

Commit: drm/i915/dp: move eDP VBT bpp clamping code to intel_dp_compute_bpp()
Okay!

Commit: drm/i915/dp: group link config limits in a struct
Okay!

Commit: drm/i915/dp: abstract link config selection
Okay!

Commit: drm/i915/dp: fix compliance test adjustments
-O:drivers/gpu/drm/i915/intel_dp.c:1667:23: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dp.c:1667:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1667:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1667:23: warning: expression using sizeof(void)

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✗ Fi.CI.BAT: failure for drm/i915/dp: link config compute refactoring (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: link config compute refactoring (rev2)
URL   : https://patchwork.freedesktop.org/series/41215/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4100 -> Patchwork_8807 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_8807 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8807, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/41215/revisions/2/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8807:

  === IGT changes ===

    ==== Possible regressions ====

    igt@debugfs_test@read_all_entries:
      fi-kbl-7560u:       PASS -> INCOMPLETE

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-kbl-7567u:       PASS -> FAIL

    
== Known issues ==

  Here are the changes found in Patchwork_8807 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-ivb-3520m:       PASS -> DMESG-WARN (fdo#106084)

    
    ==== Possible fixes ====

    igt@debugfs_test@read_all_entries:
      fi-snb-2520m:       INCOMPLETE (fdo#103713) -> PASS

    igt@kms_flip@basic-flip-vs-dpms:
      fi-bxt-dsi:         INCOMPLETE (fdo#103927) -> PASS

    
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084


== Participating hosts (37 -> 35) ==

  Missing    (2): fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4100 -> Patchwork_8807

  CI_DRM_4100: 05cc701ce9d22b01f2f4afa9fddd521b931ed163 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4449: 0350f0e7f6a0e07281445fc3082aa70419f4aac7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8807: 57809a508243f1af959fa08ef562b900425fe19d @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4449: ad8992d3fb27fd604b9ab15e7963c42421ced85c @ git://anongit.freedesktop.org/piglit


== Linux commits ==

57809a508243 drm/i915/dp: fix compliance test adjustments
3f113e6072d7 drm/i915/dp: abstract link config selection
d8ade2bdaa7a drm/i915/dp: group link config limits in a struct
ff5c64d21d93 drm/i915/dp: move eDP VBT bpp clamping code to intel_dp_compute_bpp()
4f3c34480f92 drm/i915/dp: abstract dp link config computation from the rest
77ae7b48939b drm/i915/dp: move link_bw and rate_select debugging where used
8226b468bdc1 drm/i915/dp: remove stale comment about bw constants

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8807/issues.html
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✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: link config compute refactoring (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: link config compute refactoring (rev2)
URL   : https://patchwork.freedesktop.org/series/41215/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
e404413cc8c9 drm/i915/dp: remove stale comment about bw constants
ff040231fec8 drm/i915/dp: move link_bw and rate_select debugging where used
612c61de1aa6 drm/i915/dp: abstract dp link config computation from the rest
a1d4ab2f8138 drm/i915/dp: move eDP VBT bpp clamping code to intel_dp_compute_bpp()
25d6751364a6 drm/i915/dp: group link config limits in a struct
-:69: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#69: FILE: drivers/gpu/drm/i915/intel_dp.c:1746:
+				limits.min_clock = limits.max_clock = index;

-:70: WARNING:LONG_LINE: line over 100 characters
#70: FILE: drivers/gpu/drm/i915/intel_dp.c:1747:
+			limits.min_lane_count = limits.max_lane_count = intel_dp->compliance.test_lane_count;

-:70: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#70: FILE: drivers/gpu/drm/i915/intel_dp.c:1747:
+			limits.min_lane_count = limits.max_lane_count = intel_dp->compliance.test_lane_count;

total: 0 errors, 1 warnings, 2 checks, 96 lines checked
23a3db24b5ca drm/i915/dp: abstract link config selection
1e9bea0cb9c8 drm/i915/dp: fix compliance test adjustments
-:47: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#47: FILE: drivers/gpu/drm/i915/intel_dp.c:1709:
+		limits->min_bpp = limits->max_bpp = bpp;

-:66: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#66: FILE: drivers/gpu/drm/i915/intel_dp.c:1728:
+				limits->min_clock = limits->max_clock = index;

-:67: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#67: FILE: drivers/gpu/drm/i915/intel_dp.c:1729:
+			limits->min_lane_count = limits->max_lane_count =

total: 0 errors, 0 warnings, 3 checks, 88 lines checked

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✗ Fi.CI.SPARSE: warning for drm/i915/dp: link config compute refactoring (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: link config compute refactoring (rev2)
URL   : https://patchwork.freedesktop.org/series/41215/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/dp: remove stale comment about bw constants
Okay!

Commit: drm/i915/dp: move link_bw and rate_select debugging where used
Okay!

Commit: drm/i915/dp: abstract dp link config computation from the rest
Okay!

Commit: drm/i915/dp: move eDP VBT bpp clamping code to intel_dp_compute_bpp()
Okay!

Commit: drm/i915/dp: group link config limits in a struct
Okay!

Commit: drm/i915/dp: abstract link config selection
Okay!

Commit: drm/i915/dp: fix compliance test adjustments
-O:drivers/gpu/drm/i915/intel_dp.c:1667:23: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dp.c:1667:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1667:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1667:23: warning: expression using sizeof(void)

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✓ Fi.CI.BAT: success for drm/i915/dp: link config compute refactoring (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: link config compute refactoring (rev2)
URL   : https://patchwork.freedesktop.org/series/41215/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4103 -> Patchwork_8810 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/41215/revisions/2/mbox/

== Known issues ==

  Here are the changes found in Patchwork_8810 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_suspend@basic-s3:
      fi-ivb-3520m:       PASS -> DMESG-WARN (fdo#106084)

    igt@gem_mmap_gtt@basic-small-bo-tiledx:
      fi-gdg-551:         PASS -> FAIL (fdo#102575)

    igt@gem_ringfill@basic-default-hang:
      fi-pnv-d510:        NOTRUN -> DMESG-WARN (fdo#101600)

    
    ==== Possible fixes ====

    igt@gem_exec_suspend@basic-s4-devices:
      fi-kbl-7500u:       DMESG-WARN (fdo#105128) -> PASS

    igt@kms_flip@basic-flip-vs-wf_vblank:
      fi-elk-e7500:       DMESG-WARN (fdo#103989, fdo#105225) -> PASS

    igt@kms_flip@basic-plain-flip:
      fi-elk-e7500:       DMESG-WARN (fdo#105225) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-ivb-3520m:       DMESG-WARN (fdo#106084) -> PASS

    
  fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
  fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
  fdo#105225 https://bugs.freedesktop.org/show_bug.cgi?id=105225
  fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084


== Participating hosts (38 -> 35) ==

  Additional (1): fi-pnv-d510 
  Missing    (4): fi-byt-j1900 fi-ctg-p8600 fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4103 -> Patchwork_8810

  CI_DRM_4103: 96d389ab8f2f1e05b9ba5feacef7185f59a129db @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4449: 0350f0e7f6a0e07281445fc3082aa70419f4aac7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8810: 1e9bea0cb9c8bbc98e77ff536ec9942a58802ff8 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4449: ad8992d3fb27fd604b9ab15e7963c42421ced85c @ git://anongit.freedesktop.org/piglit


== Linux commits ==

1e9bea0cb9c8 drm/i915/dp: fix compliance test adjustments
23a3db24b5ca drm/i915/dp: abstract link config selection
25d6751364a6 drm/i915/dp: group link config limits in a struct
a1d4ab2f8138 drm/i915/dp: move eDP VBT bpp clamping code to intel_dp_compute_bpp()
612c61de1aa6 drm/i915/dp: abstract dp link config computation from the rest
ff040231fec8 drm/i915/dp: move link_bw and rate_select debugging where used
e404413cc8c9 drm/i915/dp: remove stale comment about bw constants

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8810/issues.html
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✓ Fi.CI.IGT: success for drm/i915/dp: link config compute refactoring (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: link config compute refactoring (rev2)
URL   : https://patchwork.freedesktop.org/series/41215/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4103_full -> Patchwork_8810_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_8810_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8810_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/41215/revisions/2/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8810_full:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_mocs_settings@mocs-rc6-bsd1:
      shard-kbl:          SKIP -> PASS +1

    igt@gem_mocs_settings@mocs-rc6-vebox:
      shard-kbl:          PASS -> SKIP +1

    
== Known issues ==

  Here are the changes found in Patchwork_8810_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_chv_cursor_fail@pipe-b-64x64-bottom-edge:
      shard-apl:          PASS -> FAIL (fdo#104671)

    igt@kms_flip@blocking-wf_vblank:
      shard-hsw:          PASS -> FAIL (fdo#103928)

    igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
      shard-apl:          PASS -> FAIL (fdo#100368)

    igt@kms_flip@flip-vs-expired-vblank-interruptible:
      shard-glk:          PASS -> FAIL (fdo#105363, fdo#102887)

    igt@kms_flip@wf_vblank-ts-check-interruptible:
      shard-glk:          PASS -> FAIL (fdo#100368)

    igt@kms_rotation_crc@primary-rotation-180:
      shard-apl:          PASS -> DMESG-WARN (fdo#105127)

    igt@kms_vblank@pipe-a-accuracy-idle:
      shard-hsw:          PASS -> FAIL (fdo#102583)

    
    ==== Possible fixes ====

    igt@kms_flip@2x-wf_vblank-ts-check:
      shard-hsw:          FAIL (fdo#103928) -> PASS

    igt@kms_setmode@basic:
      shard-kbl:          FAIL (fdo#99912) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671
  fdo#105127 https://bugs.freedesktop.org/show_bug.cgi?id=105127
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 5) ==

  Missing    (1): shard-glkb 


== Build changes ==

    * Linux: CI_DRM_4103 -> Patchwork_8810

  CI_DRM_4103: 96d389ab8f2f1e05b9ba5feacef7185f59a129db @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4449: 0350f0e7f6a0e07281445fc3082aa70419f4aac7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8810: 1e9bea0cb9c8bbc98e77ff536ec9942a58802ff8 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4449: ad8992d3fb27fd604b9ab15e7963c42421ced85c @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8810/shards.html
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Re: [PATCH v2 0/7] drm/i915/dp: link config compute refactoring

[Jani Nikula]

On Thu, 26 Apr 2018, Jani Nikula <jani.nikula@intel.com> wrote:
> v2 of https://patchwork.freedesktop.org/series/41215/

And pushed the lot after the CI results. Thanks for the review!

BR,
Jani.

>
> Jani Nikula (7):
>   drm/i915/dp: remove stale comment about bw constants
>   drm/i915/dp: move link_bw and rate_select debugging where used
>   drm/i915/dp: abstract dp link config computation from the rest
>   drm/i915/dp: move eDP VBT bpp clamping code to intel_dp_compute_bpp()
>   drm/i915/dp: group link config limits in a struct
>   drm/i915/dp: abstract link config selection
>   drm/i915/dp: fix compliance test adjustments
>
>  drivers/gpu/drm/i915/intel_dp.c               | 277 +++++++++++++++-----------
>  drivers/gpu/drm/i915/intel_dp_link_training.c |   5 +
>  2 files changed, 169 insertions(+), 113 deletions(-)

-- 
Jani Nikula, Intel Open Source Technology Center
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