* [PATCH v2 0/6] drm/i915/display: power conversion to struct intel_display
@ 2024-11-28 15:38 Jani Nikula
2024-11-28 15:38 ` [PATCH v2 1/6] drm/i915/display: convert for_each_power_well() " Jani Nikula
` (11 more replies)
0 siblings, 12 replies; 17+ messages in thread
From: Jani Nikula @ 2024-11-28 15:38 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: imre.deak, jani.nikula
This is v2 of [1] with patch 1 dropped, and some minor checkpatch issues
fixed.
[1] https://lore.kernel.org/r/cover.1732727056.git.jani.nikula@intel.com
Jani Nikula (6):
drm/i915/display: convert for_each_power_well() to struct
intel_display
drm/i915/display: convert for_each_power_domain_well() to struct
intel_display
drm/i915/display: convert power wells to struct intel_display
drm/i915/display: convert power domain code internally to struct
intel_display
drm/i915/display: convert high level power interfaces to struct
intel_display
drm/i915/display: convert power map to struct intel_display
.../drm/i915/display/intel_display_debugfs.c | 3 +-
.../drm/i915/display/intel_display_driver.c | 8 +-
.../gpu/drm/i915/display/intel_display_irq.c | 3 +-
.../drm/i915/display/intel_display_power.c | 948 +++++++++---------
.../drm/i915/display/intel_display_power.h | 31 +-
.../i915/display/intel_display_power_map.c | 56 +-
.../i915/display/intel_display_power_well.c | 548 +++++-----
.../i915/display/intel_display_power_well.h | 35 +-
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 7 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
.../drm/i915/display/intel_modeset_setup.c | 2 +-
drivers/gpu/drm/i915/display/intel_pps.c | 4 +-
drivers/gpu/drm/i915/display/intel_psr.c | 6 +-
drivers/gpu/drm/i915/i915_driver.c | 32 +-
drivers/gpu/drm/xe/display/xe_display.c | 28 +-
15 files changed, 870 insertions(+), 843 deletions(-)
--
2.39.5
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 1/6] drm/i915/display: convert for_each_power_well() to struct intel_display
2024-11-28 15:38 [PATCH v2 0/6] drm/i915/display: power conversion to struct intel_display Jani Nikula
@ 2024-11-28 15:38 ` Jani Nikula
2024-11-28 15:38 ` [PATCH v2 2/6] drm/i915/display: convert for_each_power_domain_well() " Jani Nikula
` (10 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Jani Nikula @ 2024-11-28 15:38 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: imre.deak, jani.nikula
Start converting power well code to struct intel_display. Start off with
for_each_power_well() and the reverse variant.
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_display_power.c | 16 ++++++++++------
.../drm/i915/display/intel_display_power_well.c | 3 ++-
.../drm/i915/display/intel_display_power_well.h | 16 ++++++++--------
3 files changed, 20 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 59dee2dc0552..2e9d9f4d3ef8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -29,11 +29,11 @@
#include "vlv_sideband.h"
#define for_each_power_domain_well(__dev_priv, __power_well, __domain) \
- for_each_power_well(__dev_priv, __power_well) \
+ for_each_power_well(&(__dev_priv)->display, __power_well) \
for_each_if(test_bit((__domain), (__power_well)->domains.bits))
#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain) \
- for_each_power_well_reverse(__dev_priv, __power_well) \
+ for_each_power_well_reverse(&(__dev_priv)->display, __power_well) \
for_each_if(test_bit((__domain), (__power_well)->domains.bits))
static const char *
@@ -1028,11 +1028,12 @@ void intel_power_domains_cleanup(struct drm_i915_private *dev_priv)
static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct i915_power_well *power_well;
mutex_lock(&power_domains->lock);
- for_each_power_well(dev_priv, power_well)
+ for_each_power_well(display, power_well)
intel_power_well_sync_hw(dev_priv, power_well);
mutex_unlock(&power_domains->lock);
}
@@ -2003,12 +2004,13 @@ void intel_power_domains_driver_remove(struct drm_i915_private *i915)
*/
void intel_power_domains_sanitize_state(struct drm_i915_private *i915)
{
+ struct intel_display *display = &i915->display;
struct i915_power_domains *power_domains = &i915->display.power.domains;
struct i915_power_well *power_well;
mutex_lock(&power_domains->lock);
- for_each_power_well_reverse(i915, power_well) {
+ for_each_power_well_reverse(display, power_well) {
if (power_well->desc->always_on || power_well->count ||
!intel_power_well_is_enabled(i915, power_well))
continue;
@@ -2146,10 +2148,11 @@ void intel_power_domains_resume(struct drm_i915_private *i915)
static void intel_power_domains_dump_info(struct drm_i915_private *i915)
{
+ struct intel_display *display = &i915->display;
struct i915_power_domains *power_domains = &i915->display.power.domains;
struct i915_power_well *power_well;
- for_each_power_well(i915, power_well) {
+ for_each_power_well(display, power_well) {
enum intel_display_power_domain domain;
drm_dbg(&i915->drm, "%-25s %d\n",
@@ -2174,6 +2177,7 @@ static void intel_power_domains_dump_info(struct drm_i915_private *i915)
*/
static void intel_power_domains_verify_state(struct drm_i915_private *i915)
{
+ struct intel_display *display = &i915->display;
struct i915_power_domains *power_domains = &i915->display.power.domains;
struct i915_power_well *power_well;
bool dump_domain_info;
@@ -2183,7 +2187,7 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
verify_async_put_domains_state(power_domains);
dump_domain_info = false;
- for_each_power_well(i915, power_well) {
+ for_each_power_well(display, power_well) {
enum intel_display_power_domain domain;
int domains_count;
bool enabled;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index bdf6c690a03b..11734951937a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -76,9 +76,10 @@ struct i915_power_well *
lookup_power_well(struct drm_i915_private *i915,
enum i915_power_well_id power_well_id)
{
+ struct intel_display *display = &i915->display;
struct i915_power_well *power_well;
- for_each_power_well(i915, power_well)
+ for_each_power_well(display, power_well)
if (i915_power_well_instance(power_well)->id == power_well_id)
return power_well;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index 93559f7c6100..0c12ca46dfc8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -15,16 +15,16 @@ struct i915_power_well_ops;
struct intel_display;
struct intel_encoder;
-#define for_each_power_well(__dev_priv, __power_well) \
- for ((__power_well) = (__dev_priv)->display.power.domains.power_wells; \
- (__power_well) - (__dev_priv)->display.power.domains.power_wells < \
- (__dev_priv)->display.power.domains.power_well_count; \
+#define for_each_power_well(___display, __power_well) \
+ for ((__power_well) = (___display)->power.domains.power_wells; \
+ (__power_well) - (___display)->power.domains.power_wells < \
+ (___display)->power.domains.power_well_count; \
(__power_well)++)
-#define for_each_power_well_reverse(__dev_priv, __power_well) \
- for ((__power_well) = (__dev_priv)->display.power.domains.power_wells + \
- (__dev_priv)->display.power.domains.power_well_count - 1; \
- (__power_well) - (__dev_priv)->display.power.domains.power_wells >= 0; \
+#define for_each_power_well_reverse(___display, __power_well) \
+ for ((__power_well) = (___display)->power.domains.power_wells + \
+ (___display)->power.domains.power_well_count - 1; \
+ (__power_well) - (___display)->power.domains.power_wells >= 0; \
(__power_well)--)
/*
--
2.39.5
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 2/6] drm/i915/display: convert for_each_power_domain_well() to struct intel_display
2024-11-28 15:38 [PATCH v2 0/6] drm/i915/display: power conversion to struct intel_display Jani Nikula
2024-11-28 15:38 ` [PATCH v2 1/6] drm/i915/display: convert for_each_power_well() " Jani Nikula
@ 2024-11-28 15:38 ` Jani Nikula
2024-11-28 15:38 ` [PATCH v2 3/6] drm/i915/display: convert power wells " Jani Nikula
` (9 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Jani Nikula @ 2024-11-28 15:38 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: imre.deak, jani.nikula
Start converting display power domain code to struct
intel_display. Start off with for_each_power_domain_well() and the
reverse variant.
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_display_power.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 2e9d9f4d3ef8..73843248a04f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -28,12 +28,12 @@
#include "skl_watermark_regs.h"
#include "vlv_sideband.h"
-#define for_each_power_domain_well(__dev_priv, __power_well, __domain) \
- for_each_power_well(&(__dev_priv)->display, __power_well) \
+#define for_each_power_domain_well(__display, __power_well, __domain) \
+ for_each_power_well((__display), __power_well) \
for_each_if(test_bit((__domain), (__power_well)->domains.bits))
-#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain) \
- for_each_power_well_reverse(&(__dev_priv)->display, __power_well) \
+#define for_each_power_domain_well_reverse(__display, __power_well, __domain) \
+ for_each_power_well_reverse((__display), __power_well) \
for_each_if(test_bit((__domain), (__power_well)->domains.bits))
static const char *
@@ -201,6 +201,7 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
static bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain)
{
+ struct intel_display *display = &dev_priv->display;
struct i915_power_well *power_well;
bool is_enabled;
@@ -209,7 +210,7 @@ static bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
is_enabled = true;
- for_each_power_domain_well_reverse(dev_priv, power_well, domain) {
+ for_each_power_domain_well_reverse(display, power_well, domain) {
if (intel_power_well_is_always_on(power_well))
continue;
@@ -486,13 +487,14 @@ static void
__intel_display_power_get_domain(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain)
{
+ struct intel_display *display = &dev_priv->display;
struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct i915_power_well *power_well;
if (intel_display_power_grab_async_put_ref(dev_priv, domain))
return;
- for_each_power_domain_well(dev_priv, power_well, domain)
+ for_each_power_domain_well(display, power_well, domain)
intel_power_well_get(dev_priv, power_well);
power_domains->domain_use_count[domain]++;
@@ -570,6 +572,7 @@ static void
__intel_display_power_put_domain(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain)
{
+ struct intel_display *display = &dev_priv->display;
struct i915_power_domains *power_domains;
struct i915_power_well *power_well;
const char *name = intel_display_power_domain_str(domain);
@@ -588,7 +591,7 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
power_domains->domain_use_count[domain]--;
- for_each_power_domain_well_reverse(dev_priv, power_well, domain)
+ for_each_power_domain_well_reverse(display, power_well, domain)
intel_power_well_put(dev_priv, power_well);
}
--
2.39.5
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 3/6] drm/i915/display: convert power wells to struct intel_display
2024-11-28 15:38 [PATCH v2 0/6] drm/i915/display: power conversion to struct intel_display Jani Nikula
2024-11-28 15:38 ` [PATCH v2 1/6] drm/i915/display: convert for_each_power_well() " Jani Nikula
2024-11-28 15:38 ` [PATCH v2 2/6] drm/i915/display: convert for_each_power_domain_well() " Jani Nikula
@ 2024-11-28 15:38 ` Jani Nikula
2024-11-28 15:38 ` [PATCH v2 4/6] drm/i915/display: convert power domain code internally " Jani Nikula
` (8 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Jani Nikula @ 2024-11-28 15:38 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: imre.deak, jani.nikula
Going forward, struct intel_display is the main device data structure
for display. Switch the power well code over to it.
v2: Fix parenthesis alignment
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 3 +-
.../drm/i915/display/intel_display_power.c | 71 +--
.../i915/display/intel_display_power_well.c | 547 +++++++++---------
.../i915/display/intel_display_power_well.h | 19 +-
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 7 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/display/intel_pps.c | 4 +-
7 files changed, 321 insertions(+), 332 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 2874867aae2b..3eb7565cd83c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -730,11 +730,12 @@ static bool
intel_lpsp_power_well_enabled(struct drm_i915_private *i915,
enum i915_power_well_id power_well_id)
{
+ struct intel_display *display = &i915->display;
intel_wakeref_t wakeref;
bool is_enabled;
wakeref = intel_runtime_pm_get(&i915->runtime_pm);
- is_enabled = intel_display_power_well_is_enabled(i915,
+ is_enabled = intel_display_power_well_is_enabled(display,
power_well_id);
intel_runtime_pm_put(&i915->runtime_pm, wakeref);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 73843248a04f..ade7192c0461 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -293,12 +293,13 @@ sanitize_target_dc_state(struct drm_i915_private *i915,
void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
u32 state)
{
+ struct intel_display *display = &dev_priv->display;
struct i915_power_well *power_well;
bool dc_off_enabled;
struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
mutex_lock(&power_domains->lock);
- power_well = lookup_power_well(dev_priv, SKL_DISP_DC_OFF);
+ power_well = lookup_power_well(display, SKL_DISP_DC_OFF);
if (drm_WARN_ON(&dev_priv->drm, !power_well))
goto unlock;
@@ -308,18 +309,18 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
if (state == power_domains->target_dc_state)
goto unlock;
- dc_off_enabled = intel_power_well_is_enabled(dev_priv, power_well);
+ dc_off_enabled = intel_power_well_is_enabled(display, power_well);
/*
* If DC off power well is disabled, need to enable and disable the
* DC off power well to effect target DC state.
*/
if (!dc_off_enabled)
- intel_power_well_enable(dev_priv, power_well);
+ intel_power_well_enable(display, power_well);
power_domains->target_dc_state = state;
if (!dc_off_enabled)
- intel_power_well_disable(dev_priv, power_well);
+ intel_power_well_disable(display, power_well);
unlock:
mutex_unlock(&power_domains->lock);
@@ -495,7 +496,7 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
return;
for_each_power_domain_well(display, power_well, domain)
- intel_power_well_get(dev_priv, power_well);
+ intel_power_well_get(display, power_well);
power_domains->domain_use_count[domain]++;
}
@@ -592,7 +593,7 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
power_domains->domain_use_count[domain]--;
for_each_power_domain_well_reverse(display, power_well, domain)
- intel_power_well_put(dev_priv, power_well);
+ intel_power_well_put(display, power_well);
}
static void __intel_display_power_put(struct drm_i915_private *dev_priv,
@@ -1037,7 +1038,7 @@ static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
mutex_lock(&power_domains->lock);
for_each_power_well(display, power_well)
- intel_power_well_sync_hw(dev_priv, power_well);
+ intel_power_well_sync_hw(display, power_well);
mutex_unlock(&power_domains->lock);
}
@@ -1437,11 +1438,11 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
/* enable PG1 and Misc I/O */
mutex_lock(&power_domains->lock);
- well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
- intel_power_well_enable(dev_priv, well);
+ well = lookup_power_well(display, SKL_DISP_PW_1);
+ intel_power_well_enable(display, well);
- well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
- intel_power_well_enable(dev_priv, well);
+ well = lookup_power_well(display, SKL_DISP_PW_MISC_IO);
+ intel_power_well_enable(display, well);
mutex_unlock(&power_domains->lock);
@@ -1480,8 +1481,8 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
* Note that even though the driver's request is removed power well 1
* may stay enabled after this due to DMC's own request on it.
*/
- well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
- intel_power_well_disable(dev_priv, well);
+ well = lookup_power_well(display, SKL_DISP_PW_1);
+ intel_power_well_disable(display, well);
mutex_unlock(&power_domains->lock);
@@ -1510,8 +1511,8 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
/* Enable PG1 */
mutex_lock(&power_domains->lock);
- well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
- intel_power_well_enable(dev_priv, well);
+ well = lookup_power_well(display, SKL_DISP_PW_1);
+ intel_power_well_enable(display, well);
mutex_unlock(&power_domains->lock);
@@ -1548,8 +1549,8 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
*/
mutex_lock(&power_domains->lock);
- well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
- intel_power_well_disable(dev_priv, well);
+ well = lookup_power_well(display, SKL_DISP_PW_1);
+ intel_power_well_disable(display, well);
mutex_unlock(&power_domains->lock);
@@ -1659,8 +1660,8 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
* The AUX IO power wells will be enabled on demand.
*/
mutex_lock(&power_domains->lock);
- well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
- intel_power_well_enable(dev_priv, well);
+ well = lookup_power_well(display, SKL_DISP_PW_1);
+ intel_power_well_enable(display, well);
mutex_unlock(&power_domains->lock);
if (DISPLAY_VER(dev_priv) == 14)
@@ -1743,8 +1744,8 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
* disabled at this point.
*/
mutex_lock(&power_domains->lock);
- well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
- intel_power_well_disable(dev_priv, well);
+ well = lookup_power_well(display, SKL_DISP_PW_1);
+ intel_power_well_disable(display, well);
mutex_unlock(&power_domains->lock);
/* 5. */
@@ -1753,10 +1754,11 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
static void chv_phy_control_init(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
struct i915_power_well *cmn_bc =
- lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
+ lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);
struct i915_power_well *cmn_d =
- lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
+ lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D);
/*
* DISPLAY_PHY_CONTROL can get corrupted if read. As a
@@ -1779,7 +1781,7 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
* override and set the lane powerdown bits accding to the
* current lane status.
*/
- if (intel_power_well_is_enabled(dev_priv, cmn_bc)) {
+ if (intel_power_well_is_enabled(display, cmn_bc)) {
u32 status = intel_de_read(dev_priv, DPLL(dev_priv, PIPE_A));
unsigned int mask;
@@ -1810,7 +1812,7 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = true;
}
- if (intel_power_well_is_enabled(dev_priv, cmn_d)) {
+ if (intel_power_well_is_enabled(display, cmn_d)) {
u32 status = intel_de_read(dev_priv, DPIO_PHY_STATUS);
unsigned int mask;
@@ -1840,21 +1842,22 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
struct i915_power_well *cmn =
- lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
+ lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);
struct i915_power_well *disp2d =
- lookup_power_well(dev_priv, VLV_DISP_PW_DISP2D);
+ lookup_power_well(display, VLV_DISP_PW_DISP2D);
/* If the display might be already active skip this */
- if (intel_power_well_is_enabled(dev_priv, cmn) &&
- intel_power_well_is_enabled(dev_priv, disp2d) &&
+ if (intel_power_well_is_enabled(display, cmn) &&
+ intel_power_well_is_enabled(display, disp2d) &&
intel_de_read(dev_priv, DPIO_CTL) & DPIO_CMNRST)
return;
drm_dbg_kms(&dev_priv->drm, "toggling display PHY side reset\n");
/* cmnlane needs DPLL registers */
- intel_power_well_enable(dev_priv, disp2d);
+ intel_power_well_enable(display, disp2d);
/*
* From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
@@ -1863,7 +1866,7 @@ static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
* Simply ungating isn't enough to reset the PHY enough to get
* ports and lanes running.
*/
- intel_power_well_disable(dev_priv, cmn);
+ intel_power_well_disable(display, cmn);
}
static bool vlv_punit_is_power_gated(struct drm_i915_private *dev_priv, u32 reg0)
@@ -2015,13 +2018,13 @@ void intel_power_domains_sanitize_state(struct drm_i915_private *i915)
for_each_power_well_reverse(display, power_well) {
if (power_well->desc->always_on || power_well->count ||
- !intel_power_well_is_enabled(i915, power_well))
+ !intel_power_well_is_enabled(display, power_well))
continue;
drm_dbg_kms(&i915->drm,
"BIOS left unused %s power well enabled, disabling it\n",
intel_power_well_name(power_well));
- intel_power_well_disable(i915, power_well);
+ intel_power_well_disable(display, power_well);
}
mutex_unlock(&power_domains->lock);
@@ -2195,7 +2198,7 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
int domains_count;
bool enabled;
- enabled = intel_power_well_is_enabled(i915, power_well);
+ enabled = intel_power_well_is_enabled(display, power_well);
if ((intel_power_well_refcount(power_well) ||
intel_power_well_is_always_on(power_well)) !=
enabled)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 11734951937a..f45a4f9ba23c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -46,23 +46,23 @@ struct i915_power_well_ops {
* during driver init and resume time, possibly after first calling
* the enable/disable handlers.
*/
- void (*sync_hw)(struct drm_i915_private *i915,
+ void (*sync_hw)(struct intel_display *display,
struct i915_power_well *power_well);
/*
* Enable the well and resources that depend on it (for example
* interrupts located on the well). Called after the 0->1 refcount
* transition.
*/
- void (*enable)(struct drm_i915_private *i915,
+ void (*enable)(struct intel_display *display,
struct i915_power_well *power_well);
/*
* Disable the well and resources that depend on it. Called after
* the 1->0 refcount transition.
*/
- void (*disable)(struct drm_i915_private *i915,
+ void (*disable)(struct intel_display *display,
struct i915_power_well *power_well);
/* Returns the hw enabled state. */
- bool (*is_enabled)(struct drm_i915_private *i915,
+ bool (*is_enabled)(struct intel_display *display,
struct i915_power_well *power_well);
};
@@ -73,10 +73,9 @@ i915_power_well_instance(const struct i915_power_well *power_well)
}
struct i915_power_well *
-lookup_power_well(struct drm_i915_private *i915,
+lookup_power_well(struct intel_display *display,
enum i915_power_well_id power_well_id)
{
- struct intel_display *display = &i915->display;
struct i915_power_well *power_well;
for_each_power_well(display, power_well)
@@ -90,58 +89,57 @@ lookup_power_well(struct drm_i915_private *i915,
* the first power well and hope the WARN gets reported so we can fix
* our driver.
*/
- drm_WARN(&i915->drm, 1,
+ drm_WARN(display->drm, 1,
"Power well %d not defined for this platform\n",
power_well_id);
- return &i915->display.power.domains.power_wells[0];
+ return &display->power.domains.power_wells[0];
}
-void intel_power_well_enable(struct drm_i915_private *i915,
+void intel_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well)
{
- drm_dbg_kms(&i915->drm, "enabling %s\n", intel_power_well_name(power_well));
- power_well->desc->ops->enable(i915, power_well);
+ drm_dbg_kms(display->drm, "enabling %s\n", intel_power_well_name(power_well));
+ power_well->desc->ops->enable(display, power_well);
power_well->hw_enabled = true;
}
-void intel_power_well_disable(struct drm_i915_private *i915,
+void intel_power_well_disable(struct intel_display *display,
struct i915_power_well *power_well)
{
- drm_dbg_kms(&i915->drm, "disabling %s\n", intel_power_well_name(power_well));
+ drm_dbg_kms(display->drm, "disabling %s\n", intel_power_well_name(power_well));
power_well->hw_enabled = false;
- power_well->desc->ops->disable(i915, power_well);
+ power_well->desc->ops->disable(display, power_well);
}
-void intel_power_well_sync_hw(struct drm_i915_private *i915,
+void intel_power_well_sync_hw(struct intel_display *display,
struct i915_power_well *power_well)
{
- power_well->desc->ops->sync_hw(i915, power_well);
- power_well->hw_enabled =
- power_well->desc->ops->is_enabled(i915, power_well);
+ power_well->desc->ops->sync_hw(display, power_well);
+ power_well->hw_enabled = power_well->desc->ops->is_enabled(display, power_well);
}
-void intel_power_well_get(struct drm_i915_private *i915,
+void intel_power_well_get(struct intel_display *display,
struct i915_power_well *power_well)
{
if (!power_well->count++)
- intel_power_well_enable(i915, power_well);
+ intel_power_well_enable(display, power_well);
}
-void intel_power_well_put(struct drm_i915_private *i915,
+void intel_power_well_put(struct intel_display *display,
struct i915_power_well *power_well)
{
- drm_WARN(&i915->drm, !power_well->count,
+ drm_WARN(display->drm, !power_well->count,
"Use count on power well %s is already zero",
i915_power_well_instance(power_well)->name);
if (!--power_well->count)
- intel_power_well_disable(i915, power_well);
+ intel_power_well_disable(display, power_well);
}
-bool intel_power_well_is_enabled(struct drm_i915_private *i915,
+bool intel_power_well_is_enabled(struct intel_display *display,
struct i915_power_well *power_well)
{
- return power_well->desc->ops->is_enabled(i915, power_well);
+ return power_well->desc->ops->is_enabled(display, power_well);
}
bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well)
@@ -149,14 +147,14 @@ bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well)
return power_well->hw_enabled;
}
-bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
+bool intel_display_power_well_is_enabled(struct intel_display *display,
enum i915_power_well_id power_well_id)
{
struct i915_power_well *power_well;
- power_well = lookup_power_well(dev_priv, power_well_id);
+ power_well = lookup_power_well(display, power_well_id);
- return intel_power_well_is_enabled(dev_priv, power_well);
+ return intel_power_well_is_enabled(display, power_well);
}
bool intel_power_well_is_always_on(struct i915_power_well *power_well)
@@ -185,10 +183,10 @@ int intel_power_well_refcount(struct i915_power_well *power_well)
* to be enabled, and it will only be disabled if none of the registers is
* requesting it to be enabled.
*/
-static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
+static void hsw_power_well_post_enable(struct intel_display *display,
u8 irq_pipe_mask, bool has_vga)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
if (has_vga)
intel_vga_reset_io_mem(display);
@@ -197,9 +195,11 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
}
-static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
+static void hsw_power_well_pre_disable(struct intel_display *display,
u8 irq_pipe_mask)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
if (irq_pipe_mask)
gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
}
@@ -222,12 +222,12 @@ static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well)
}
static struct intel_digital_port *
-aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
+aux_ch_to_digital_port(struct intel_display *display,
enum aux_ch aux_ch)
{
struct intel_encoder *encoder;
- for_each_intel_encoder(&dev_priv->drm, encoder) {
+ for_each_intel_encoder(display->drm, encoder) {
struct intel_digital_port *dig_port;
/* We'll check the MST primary port */
@@ -243,11 +243,11 @@ aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
return NULL;
}
-static enum phy icl_aux_pw_to_phy(struct drm_i915_private *i915,
+static enum phy icl_aux_pw_to_phy(struct intel_display *display,
const struct i915_power_well *power_well)
{
enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
- struct intel_digital_port *dig_port = aux_ch_to_digital_port(i915, aux_ch);
+ struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);
/*
* FIXME should we care about the (VBT defined) dig_port->aux_ch
@@ -259,7 +259,7 @@ static enum phy icl_aux_pw_to_phy(struct drm_i915_private *i915,
return dig_port ? intel_encoder_to_phy(&dig_port->base) : PHY_NONE;
}
-static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
+static void hsw_wait_for_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well,
bool timeout_expected)
{
@@ -272,39 +272,39 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
* an ack, but rather just wait a fixed amount of time and then
* proceed. This is only used on DG2.
*/
- if (IS_DG2(dev_priv) && power_well->desc->fixed_enable_delay) {
+ if (display->platform.dg2 && power_well->desc->fixed_enable_delay) {
usleep_range(600, 1200);
return;
}
/* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
- if (intel_de_wait_for_set(dev_priv, regs->driver,
+ if (intel_de_wait_for_set(display, regs->driver,
HSW_PWR_WELL_CTL_STATE(pw_idx), timeout)) {
- drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n",
+ drm_dbg_kms(display->drm, "%s power well enable timeout\n",
intel_power_well_name(power_well));
- drm_WARN_ON(&dev_priv->drm, !timeout_expected);
+ drm_WARN_ON(display->drm, !timeout_expected);
}
}
-static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,
+static u32 hsw_power_well_requesters(struct intel_display *display,
const struct i915_power_well_regs *regs,
int pw_idx)
{
u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
u32 ret;
- ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0;
- ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 : 0;
+ ret = intel_de_read(display, regs->bios) & req_mask ? 1 : 0;
+ ret |= intel_de_read(display, regs->driver) & req_mask ? 2 : 0;
if (regs->kvmr.reg)
- ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ? 4 : 0;
- ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0;
+ ret |= intel_de_read(display, regs->kvmr) & req_mask ? 4 : 0;
+ ret |= intel_de_read(display, regs->debug) & req_mask ? 8 : 0;
return ret;
}
-static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
+static void hsw_wait_for_power_well_disable(struct intel_display *display,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
@@ -321,28 +321,28 @@ static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
* Skip the wait in case any of the request bits are set and print a
* diagnostic message.
*/
- wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) &
+ wait_for((disabled = !(intel_de_read(display, regs->driver) &
HSW_PWR_WELL_CTL_STATE(pw_idx))) ||
- (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1);
+ (reqs = hsw_power_well_requesters(display, regs, pw_idx)), 1);
if (disabled)
return;
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n",
intel_power_well_name(power_well),
!!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
}
-static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
+static void gen9_wait_for_power_well_fuses(struct intel_display *display,
enum skl_power_gate pg)
{
/* Timeout 5us for PG#0, for other PGs 1us */
- drm_WARN_ON(&dev_priv->drm,
- intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS,
+ drm_WARN_ON(display->drm,
+ intel_de_wait_for_set(display, SKL_FUSE_STATUS,
SKL_FUSE_PG_DIST_STATUS(pg), 1));
}
-static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
+static void hsw_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
@@ -351,12 +351,12 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
if (power_well->desc->has_fuses) {
enum skl_power_gate pg;
- pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
+ pg = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
SKL_PW_CTL_IDX_TO_PG(pw_idx);
/* Wa_16013190616:adlp */
- if (IS_ALDERLAKE_P(dev_priv) && pg == SKL_PG1)
- intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC);
+ if (display->platform.alderlake_p && pg == SKL_PG1)
+ intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC);
/*
* For PW1 we have to wait both for the PW0/PG0 fuse state
@@ -366,112 +366,112 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
* after the enabling.
*/
if (pg == SKL_PG1)
- gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0);
+ gen9_wait_for_power_well_fuses(display, SKL_PG0);
}
- intel_de_rmw(dev_priv, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx));
+ intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx));
- hsw_wait_for_power_well_enable(dev_priv, power_well, false);
+ hsw_wait_for_power_well_enable(display, power_well, false);
if (power_well->desc->has_fuses) {
enum skl_power_gate pg;
- pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
+ pg = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
SKL_PW_CTL_IDX_TO_PG(pw_idx);
- gen9_wait_for_power_well_fuses(dev_priv, pg);
+ gen9_wait_for_power_well_fuses(display, pg);
}
- hsw_power_well_post_enable(dev_priv,
+ hsw_power_well_post_enable(display,
power_well->desc->irq_pipe_mask,
power_well->desc->has_vga);
}
-static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
+static void hsw_power_well_disable(struct intel_display *display,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
- hsw_power_well_pre_disable(dev_priv,
+ hsw_power_well_pre_disable(display,
power_well->desc->irq_pipe_mask);
- intel_de_rmw(dev_priv, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0);
- hsw_wait_for_power_well_disable(dev_priv, power_well);
+ intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0);
+ hsw_wait_for_power_well_disable(display, power_well);
}
-static bool intel_aux_ch_is_edp(struct drm_i915_private *i915, enum aux_ch aux_ch)
+static bool intel_aux_ch_is_edp(struct intel_display *display, enum aux_ch aux_ch)
{
- struct intel_digital_port *dig_port = aux_ch_to_digital_port(i915, aux_ch);
+ struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);
return dig_port && dig_port->base.type == INTEL_OUTPUT_EDP;
}
static void
-icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
+icl_combo_phy_aux_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
- drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
+ drm_WARN_ON(display->drm, !display->platform.icelake);
- intel_de_rmw(dev_priv, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx));
+ intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx));
/*
* FIXME not sure if we should derive the PHY from the pw_idx, or
* from the VBT defined AUX_CH->DDI->PHY mapping.
*/
- intel_de_rmw(dev_priv, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)),
+ intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)),
0, ICL_LANE_ENABLE_AUX);
- hsw_wait_for_power_well_enable(dev_priv, power_well, false);
+ hsw_wait_for_power_well_enable(display, power_well, false);
/* Display WA #1178: icl */
if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
- !intel_aux_ch_is_edp(dev_priv, ICL_AUX_PW_TO_CH(pw_idx)))
- intel_de_rmw(dev_priv, ICL_PORT_TX_DW6_AUX(ICL_AUX_PW_TO_PHY(pw_idx)),
+ !intel_aux_ch_is_edp(display, ICL_AUX_PW_TO_CH(pw_idx)))
+ intel_de_rmw(display, ICL_PORT_TX_DW6_AUX(ICL_AUX_PW_TO_PHY(pw_idx)),
0, O_FUNC_OVRD_EN | O_LDO_BYPASS_CRI);
}
static void
-icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
+icl_combo_phy_aux_power_well_disable(struct intel_display *display,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
- drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
+ drm_WARN_ON(display->drm, !display->platform.icelake);
/*
* FIXME not sure if we should derive the PHY from the pw_idx, or
* from the VBT defined AUX_CH->DDI->PHY mapping.
*/
- intel_de_rmw(dev_priv, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)),
+ intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)),
ICL_LANE_ENABLE_AUX, 0);
- intel_de_rmw(dev_priv, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0);
+ intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0);
- hsw_wait_for_power_well_disable(dev_priv, power_well);
+ hsw_wait_for_power_well_disable(display, power_well);
}
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
-static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
+static void icl_tc_port_assert_ref_held(struct intel_display *display,
struct i915_power_well *power_well,
struct intel_digital_port *dig_port)
{
- if (drm_WARN_ON(&dev_priv->drm, !dig_port))
+ if (drm_WARN_ON(display->drm, !dig_port))
return;
- if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port))
+ if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port))
return;
- drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port));
+ drm_WARN_ON(display->drm, !intel_tc_port_ref_held(dig_port));
}
#else
-static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
+static void icl_tc_port_assert_ref_held(struct intel_display *display,
struct i915_power_well *power_well,
struct intel_digital_port *dig_port)
{
@@ -481,8 +481,9 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
#define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1)
-static void icl_tc_cold_exit(struct drm_i915_private *i915)
+static void icl_tc_cold_exit(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
int ret, tries = 0;
while (1) {
@@ -503,21 +504,22 @@ static void icl_tc_cold_exit(struct drm_i915_private *i915)
}
static void
-icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
+icl_tc_phy_aux_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
- struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
+ struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
bool is_tbt = power_well->desc->is_tc_tbt;
bool timeout_expected;
- icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
+ icl_tc_port_assert_ref_held(display, power_well, dig_port);
- intel_de_rmw(dev_priv, DP_AUX_CH_CTL(aux_ch),
+ intel_de_rmw(display, DP_AUX_CH_CTL(aux_ch),
DP_AUX_CH_CTL_TBT_IO, is_tbt ? DP_AUX_CH_CTL_TBT_IO : 0);
- intel_de_rmw(dev_priv, regs->driver,
+ intel_de_rmw(display, regs->driver,
0,
HSW_PWR_WELL_CTL_REQ(i915_power_well_instance(power_well)->hsw.idx));
@@ -527,51 +529,53 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
* exit sequence.
*/
timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port);
- if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port))
- icl_tc_cold_exit(dev_priv);
+ if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port))
+ icl_tc_cold_exit(display);
- hsw_wait_for_power_well_enable(dev_priv, power_well, timeout_expected);
+ hsw_wait_for_power_well_enable(display, power_well, timeout_expected);
- if (DISPLAY_VER(dev_priv) >= 12 && !is_tbt) {
+ if (DISPLAY_VER(display) >= 12 && !is_tbt) {
enum tc_port tc_port;
tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx);
if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port)) &
DKL_CMN_UC_DW27_UC_HEALTH, 1))
- drm_warn(&dev_priv->drm,
+ drm_warn(display->drm,
"Timeout waiting TC uC health\n");
}
}
static void
-icl_aux_power_well_enable(struct drm_i915_private *dev_priv,
+icl_aux_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well)
{
- enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+ enum phy phy = icl_aux_pw_to_phy(display, power_well);
if (intel_phy_is_tc(dev_priv, phy))
- return icl_tc_phy_aux_power_well_enable(dev_priv, power_well);
- else if (IS_ICELAKE(dev_priv))
- return icl_combo_phy_aux_power_well_enable(dev_priv,
+ return icl_tc_phy_aux_power_well_enable(display, power_well);
+ else if (display->platform.icelake)
+ return icl_combo_phy_aux_power_well_enable(display,
power_well);
else
- return hsw_power_well_enable(dev_priv, power_well);
+ return hsw_power_well_enable(display, power_well);
}
static void
-icl_aux_power_well_disable(struct drm_i915_private *dev_priv,
+icl_aux_power_well_disable(struct intel_display *display,
struct i915_power_well *power_well)
{
- enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+ enum phy phy = icl_aux_pw_to_phy(display, power_well);
if (intel_phy_is_tc(dev_priv, phy))
- return hsw_power_well_disable(dev_priv, power_well);
- else if (IS_ICELAKE(dev_priv))
- return icl_combo_phy_aux_power_well_disable(dev_priv,
+ return hsw_power_well_disable(display, power_well);
+ else if (display->platform.icelake)
+ return icl_combo_phy_aux_power_well_disable(display,
power_well);
else
- return hsw_power_well_disable(dev_priv, power_well);
+ return hsw_power_well_disable(display, power_well);
}
/*
@@ -579,7 +583,7 @@ icl_aux_power_well_disable(struct drm_i915_private *dev_priv,
* enable it, so check if it's enabled and also check if we've requested it to
* be enabled.
*/
-static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
+static bool hsw_power_well_enabled(struct intel_display *display,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
@@ -589,7 +593,7 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
HSW_PWR_WELL_CTL_STATE(pw_idx);
u32 val;
- val = intel_de_read(dev_priv, regs->driver);
+ val = intel_de_read(display, regs->driver);
/*
* On GEN9 big core due to a DMC bug the driver's request bits for PW1
@@ -597,9 +601,9 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
* BIOS's own request bits, which are forced-on for these power wells
* when exiting DC5/6.
*/
- if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
+ if (DISPLAY_VER(display) == 9 && !display->platform.broxton &&
(id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO))
- val |= intel_de_read(dev_priv, regs->bios);
+ val |= intel_de_read(display, regs->bios);
return (val & mask) == mask;
}
@@ -692,7 +696,6 @@ static void gen9_write_dc_state(struct intel_display *display,
static u32 gen9_dc_mask(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 mask;
mask = DC_STATE_EN_UPTO_DC5;
@@ -702,7 +705,7 @@ static u32 gen9_dc_mask(struct intel_display *display)
| DC_STATE_EN_DC9;
else if (DISPLAY_VER(display) == 11)
mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
- else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
+ else if (display->platform.geminilake || display->platform.broxton)
mask |= DC_STATE_EN_DC9;
else
mask |= DC_STATE_EN_UPTO_DC6;
@@ -799,7 +802,7 @@ static void tgl_disable_dc3co(struct intel_display *display)
static void assert_can_enable_dc5(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
+ struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm);
enum i915_power_well_id high_pg;
/* Power wells at this level and above must be disabled for DC5 entry */
@@ -809,7 +812,7 @@ static void assert_can_enable_dc5(struct intel_display *display)
high_pg = SKL_DISP_PW_2;
drm_WARN_ONCE(display->drm,
- intel_display_power_well_is_enabled(dev_priv, high_pg),
+ intel_display_power_well_is_enabled(display, high_pg),
"Power wells above platform's DC5 limit still enabled.\n");
drm_WARN_ONCE(display->drm,
@@ -823,14 +826,12 @@ static void assert_can_enable_dc5(struct intel_display *display)
void gen9_enable_dc5(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
-
assert_can_enable_dc5(display);
drm_dbg_kms(display->drm, "Enabling DC5\n");
/* Wa Display #1183: skl,kbl,cfl */
- if (DISPLAY_VER(display) == 9 && !IS_BROXTON(dev_priv))
+ if (DISPLAY_VER(display) == 9 && !display->platform.broxton)
intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,
0, SKL_SELECT_ALTERNATE_DC_EXIT);
@@ -856,14 +857,12 @@ static void assert_can_enable_dc6(struct intel_display *display)
void skl_enable_dc6(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
-
assert_can_enable_dc6(display);
drm_dbg_kms(display->drm, "Enabling DC6\n");
/* Wa Display #1183: skl,kbl,cfl */
- if (DISPLAY_VER(display) == 9 && !IS_BROXTON(dev_priv))
+ if (DISPLAY_VER(display) == 9 && !display->platform.broxton)
intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,
0, SKL_SELECT_ALTERNATE_DC_EXIT);
@@ -874,8 +873,6 @@ void skl_enable_dc6(struct intel_display *display)
void bxt_enable_dc9(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
-
assert_can_enable_dc9(display);
drm_dbg_kms(display->drm, "Enabling DC9\n");
@@ -883,7 +880,7 @@ void bxt_enable_dc9(struct intel_display *display)
* Power sequencer reset is needed on BXT/GLK, because the PPS registers
* aren't always on, unlike with South Display Engine on PCH.
*/
- if (IS_BROXTON(dev_priv) || IS_GEMINILAKE(dev_priv))
+ if (display->platform.broxton || display->platform.geminilake)
bxt_pps_reset_all(display);
gen9_set_dc_state(display, DC_STATE_EN_DC9);
}
@@ -899,63 +896,56 @@ void bxt_disable_dc9(struct intel_display *display)
intel_pps_unlock_regs_wa(display);
}
-static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
+static void hsw_power_well_sync_hw(struct intel_display *display,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
- u32 bios_req = intel_de_read(dev_priv, regs->bios);
+ u32 bios_req = intel_de_read(display, regs->bios);
/* Take over the request bit if set by BIOS. */
if (bios_req & mask) {
- u32 drv_req = intel_de_read(dev_priv, regs->driver);
+ u32 drv_req = intel_de_read(display, regs->driver);
if (!(drv_req & mask))
- intel_de_write(dev_priv, regs->driver, drv_req | mask);
- intel_de_write(dev_priv, regs->bios, bios_req & ~mask);
+ intel_de_write(display, regs->driver, drv_req | mask);
+ intel_de_write(display, regs->bios, bios_req & ~mask);
}
}
-static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
+static void bxt_dpio_cmn_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well)
{
- struct intel_display *display = &dev_priv->display;
-
bxt_dpio_phy_init(display, i915_power_well_instance(power_well)->bxt.phy);
}
-static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
+static void bxt_dpio_cmn_power_well_disable(struct intel_display *display,
struct i915_power_well *power_well)
{
- struct intel_display *display = &dev_priv->display;
-
bxt_dpio_phy_uninit(display, i915_power_well_instance(power_well)->bxt.phy);
}
-static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
+static bool bxt_dpio_cmn_power_well_enabled(struct intel_display *display,
struct i915_power_well *power_well)
{
- struct intel_display *display = &dev_priv->display;
-
return bxt_dpio_phy_is_enabled(display, i915_power_well_instance(power_well)->bxt.phy);
}
-static void bxt_verify_dpio_phy_power_wells(struct drm_i915_private *dev_priv)
+static void bxt_verify_dpio_phy_power_wells(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
struct i915_power_well *power_well;
- power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);
+ power_well = lookup_power_well(display, BXT_DISP_PW_DPIO_CMN_A);
if (intel_power_well_refcount(power_well) > 0)
bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy);
- power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
+ power_well = lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);
if (intel_power_well_refcount(power_well) > 0)
bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy);
- if (IS_GEMINILAKE(dev_priv)) {
- power_well = lookup_power_well(dev_priv,
+ if (display->platform.geminilake) {
+ power_well = lookup_power_well(display,
GLK_DISP_PW_DPIO_CMN_C);
if (intel_power_well_refcount(power_well) > 0)
bxt_dpio_phy_verify_state(display,
@@ -963,21 +953,20 @@ static void bxt_verify_dpio_phy_power_wells(struct drm_i915_private *dev_priv)
}
}
-static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
+static bool gen9_dc_off_power_well_enabled(struct intel_display *display,
struct i915_power_well *power_well)
{
- struct intel_display *display = &dev_priv->display;
-
return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
(intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
}
-static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
+static void gen9_assert_dbuf_enabled(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv);
- u8 enabled_dbuf_slices = dev_priv->display.dbuf.enabled_slices;
+ u8 enabled_dbuf_slices = display->dbuf.enabled_slices;
- drm_WARN(&dev_priv->drm,
+ drm_WARN(display->drm,
hw_enabled_dbuf_slices != enabled_dbuf_slices,
"Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n",
hw_enabled_dbuf_slices,
@@ -1015,10 +1004,10 @@ void gen9_disable_dc_states(struct intel_display *display)
intel_cdclk_clock_changed(&display->cdclk.hw,
&cdclk_config));
- gen9_assert_dbuf_enabled(dev_priv);
+ gen9_assert_dbuf_enabled(display);
- if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- bxt_verify_dpio_phy_power_wells(dev_priv);
+ if (display->platform.geminilake || display->platform.broxton)
+ bxt_verify_dpio_phy_power_wells(display);
if (DISPLAY_VER(display) >= 11)
/*
@@ -1029,18 +1018,15 @@ void gen9_disable_dc_states(struct intel_display *display)
intel_combo_phy_init(dev_priv);
}
-static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
+static void gen9_dc_off_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well)
{
- struct intel_display *display = &dev_priv->display;
-
gen9_disable_dc_states(display);
}
-static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
+static void gen9_dc_off_power_well_disable(struct intel_display *display,
struct i915_power_well *power_well)
{
- struct intel_display *display = &dev_priv->display;
struct i915_power_domains *power_domains = &display->power.domains;
if (!intel_dmc_has_payload(display))
@@ -1059,63 +1045,58 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
}
}
-static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
+static void i9xx_power_well_sync_hw_noop(struct intel_display *display,
struct i915_power_well *power_well)
{
}
-static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
+static void i9xx_always_on_power_well_noop(struct intel_display *display,
struct i915_power_well *power_well)
{
}
-static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
+static bool i9xx_always_on_power_well_enabled(struct intel_display *display,
+ struct i915_power_well *power_well)
{
return true;
}
-static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv,
+static void i830_pipes_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well)
{
- struct intel_display *display = &dev_priv->display;
-
- if ((intel_de_read(display, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE) == 0)
+ if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0)
i830_enable_pipe(display, PIPE_A);
- if ((intel_de_read(display, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE) == 0)
+ if ((intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE) == 0)
i830_enable_pipe(display, PIPE_B);
}
-static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv,
+static void i830_pipes_power_well_disable(struct intel_display *display,
struct i915_power_well *power_well)
{
- struct intel_display *display = &dev_priv->display;
-
i830_disable_pipe(display, PIPE_B);
i830_disable_pipe(display, PIPE_A);
}
-static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv,
+static bool i830_pipes_power_well_enabled(struct intel_display *display,
struct i915_power_well *power_well)
{
- struct intel_display *display = &dev_priv->display;
-
- return intel_de_read(display, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE &&
- intel_de_read(display, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE;
+ return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE &&
+ intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE;
}
-static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
+static void i830_pipes_power_well_sync_hw(struct intel_display *display,
struct i915_power_well *power_well)
{
if (intel_power_well_refcount(power_well) > 0)
- i830_pipes_power_well_enable(dev_priv, power_well);
+ i830_pipes_power_well_enable(display, power_well);
else
- i830_pipes_power_well_disable(dev_priv, power_well);
+ i830_pipes_power_well_disable(display, power_well);
}
-static void vlv_set_power_well(struct drm_i915_private *dev_priv,
+static void vlv_set_power_well(struct intel_display *display,
struct i915_power_well *power_well, bool enable)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
int pw_idx = i915_power_well_instance(power_well)->vlv.idx;
u32 mask;
u32 state;
@@ -1139,7 +1120,7 @@ static void vlv_set_power_well(struct drm_i915_private *dev_priv,
vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
if (wait_for(COND, 100))
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"timeout setting power well state %08x (%08x)\n",
state,
vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
@@ -1150,21 +1131,22 @@ static void vlv_set_power_well(struct drm_i915_private *dev_priv,
vlv_punit_put(dev_priv);
}
-static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
+static void vlv_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well)
{
- vlv_set_power_well(dev_priv, power_well, true);
+ vlv_set_power_well(display, power_well, true);
}
-static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
+static void vlv_power_well_disable(struct intel_display *display,
struct i915_power_well *power_well)
{
- vlv_set_power_well(dev_priv, power_well, false);
+ vlv_set_power_well(display, power_well, false);
}
-static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
+static bool vlv_power_well_enabled(struct intel_display *display,
struct i915_power_well *power_well)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
int pw_idx = i915_power_well_instance(power_well)->vlv.idx;
bool enabled = false;
u32 mask;
@@ -1181,7 +1163,7 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
* We only ever set the power-on and power-gate states, anything
* else is unexpected.
*/
- drm_WARN_ON(&dev_priv->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) &&
+ drm_WARN_ON(display->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) &&
state != PUNIT_PWRGT_PWR_GATE(pw_idx));
if (state == ctrl)
enabled = true;
@@ -1191,14 +1173,14 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
* is poking at the power controls too.
*/
ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
- drm_WARN_ON(&dev_priv->drm, ctrl != state);
+ drm_WARN_ON(display->drm, ctrl != state);
vlv_punit_put(dev_priv);
return enabled;
}
-static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
+static void vlv_init_display_clock_gating(struct intel_display *display)
{
/*
* On driver load, a pipe may be active and driving a DSI display.
@@ -1206,25 +1188,25 @@ static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
* (and never recovering) in this case. intel_dsi_post_disable() will
* clear it when we turn off the display.
*/
- intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv),
+ intel_de_rmw(display, DSPCLK_GATE_D(display),
~DPOUNIT_CLOCK_GATE_DISABLE, VRHUNIT_CLOCK_GATE_DISABLE);
/*
* Disable trickle feed and enable pnd deadline calculation
*/
- intel_de_write(dev_priv, MI_ARB_VLV,
+ intel_de_write(display, MI_ARB_VLV,
MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
- intel_de_write(dev_priv, CBR1_VLV, 0);
+ intel_de_write(display, CBR1_VLV, 0);
- drm_WARN_ON(&dev_priv->drm, DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq == 0);
- intel_de_write(dev_priv, RAWCLK_FREQ_VLV,
- DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq,
+ drm_WARN_ON(display->drm, DISPLAY_RUNTIME_INFO(display)->rawclk_freq == 0);
+ intel_de_write(display, RAWCLK_FREQ_VLV,
+ DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(display)->rawclk_freq,
1000));
}
-static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
+static void vlv_display_power_well_init(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_encoder *encoder;
enum pipe pipe;
@@ -1236,17 +1218,17 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
*
* CHV DPLL B/C have some issues if VGA mode is enabled.
*/
- for_each_pipe(dev_priv, pipe) {
- u32 val = intel_de_read(dev_priv, DPLL(dev_priv, pipe));
+ for_each_pipe(display, pipe) {
+ u32 val = intel_de_read(display, DPLL(display, pipe));
val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
if (pipe != PIPE_A)
val |= DPLL_INTEGRATED_CRI_CLK_VLV;
- intel_de_write(dev_priv, DPLL(dev_priv, pipe), val);
+ intel_de_write(display, DPLL(display, pipe), val);
}
- vlv_init_display_clock_gating(dev_priv);
+ vlv_init_display_clock_gating(display);
spin_lock_irq(&dev_priv->irq_lock);
valleyview_enable_display_irqs(dev_priv);
@@ -1256,14 +1238,14 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
* During driver initialization/resume we can avoid restoring the
* part of the HW/SW state that will be inited anyway explicitly.
*/
- if (dev_priv->display.power.domains.initializing)
+ if (display->power.domains.initializing)
return;
intel_hpd_init(dev_priv);
intel_hpd_poll_disable(dev_priv);
/* Re-enable the ADPA, if we have one */
- for_each_intel_encoder(&dev_priv->drm, encoder) {
+ for_each_intel_encoder(display->drm, encoder) {
if (encoder->type == INTEL_OUTPUT_ANALOG)
intel_crt_reset(&encoder->base);
}
@@ -1273,9 +1255,9 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
intel_pps_unlock_regs_wa(display);
}
-static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
+static void vlv_display_power_well_deinit(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
spin_lock_irq(&dev_priv->irq_lock);
valleyview_disable_display_irqs(dev_priv);
@@ -1287,33 +1269,33 @@ static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
vlv_pps_reset_all(display);
/* Prevent us from re-enabling polling on accident in late suspend */
- if (!dev_priv->drm.dev->power.is_suspended)
+ if (!display->drm->dev->power.is_suspended)
intel_hpd_poll_enable(dev_priv);
}
-static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
+static void vlv_display_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well)
{
- vlv_set_power_well(dev_priv, power_well, true);
+ vlv_set_power_well(display, power_well, true);
- vlv_display_power_well_init(dev_priv);
+ vlv_display_power_well_init(display);
}
-static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
+static void vlv_display_power_well_disable(struct intel_display *display,
struct i915_power_well *power_well)
{
- vlv_display_power_well_deinit(dev_priv);
+ vlv_display_power_well_deinit(display);
- vlv_set_power_well(dev_priv, power_well, false);
+ vlv_set_power_well(display, power_well, false);
}
-static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
+static void vlv_dpio_cmn_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well)
{
/* since ref/cri clock was enabled */
udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
- vlv_set_power_well(dev_priv, power_well, true);
+ vlv_set_power_well(display, power_well, true);
/*
* From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
@@ -1326,32 +1308,32 @@ static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
* both PLLs disabled, or we risk losing DPIO and PLL
* synchronization.
*/
- intel_de_rmw(dev_priv, DPIO_CTL, 0, DPIO_CMNRST);
+ intel_de_rmw(display, DPIO_CTL, 0, DPIO_CMNRST);
}
-static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
+static void vlv_dpio_cmn_power_well_disable(struct intel_display *display,
struct i915_power_well *power_well)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
enum pipe pipe;
- for_each_pipe(dev_priv, pipe)
+ for_each_pipe(display, pipe)
assert_pll_disabled(dev_priv, pipe);
/* Assert common reset */
- intel_de_rmw(dev_priv, DPIO_CTL, DPIO_CMNRST, 0);
+ intel_de_rmw(display, DPIO_CTL, DPIO_CMNRST, 0);
- vlv_set_power_well(dev_priv, power_well, false);
+ vlv_set_power_well(display, power_well, false);
}
#define BITS_SET(val, bits) (((val) & (bits)) == (bits))
static void assert_chv_phy_status(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
struct i915_power_well *cmn_bc =
- lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
+ lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);
struct i915_power_well *cmn_d =
- lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
+ lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D);
u32 phy_control = display->power.chv_phy_control;
u32 phy_status = 0;
u32 phy_status_mask = 0xffffffff;
@@ -1376,7 +1358,7 @@ static void assert_chv_phy_status(struct intel_display *display)
PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
- if (intel_power_well_is_enabled(dev_priv, cmn_bc)) {
+ if (intel_power_well_is_enabled(display, cmn_bc)) {
phy_status |= PHY_POWERGOOD(DPIO_PHY0);
/* this assumes override is only used to enable lanes */
@@ -1417,7 +1399,7 @@ static void assert_chv_phy_status(struct intel_display *display)
phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
}
- if (intel_power_well_is_enabled(dev_priv, cmn_d)) {
+ if (intel_power_well_is_enabled(display, cmn_d)) {
phy_status |= PHY_POWERGOOD(DPIO_PHY1);
/* this assumes override is only used to enable lanes */
@@ -1452,10 +1434,10 @@ static void assert_chv_phy_status(struct intel_display *display)
#undef BITS_SET
-static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
+static void chv_dpio_cmn_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
enum dpio_phy phy;
u32 tmp;
@@ -1471,7 +1453,7 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
/* since ref/cri clock was enabled */
udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
- vlv_set_power_well(dev_priv, power_well, true);
+ vlv_set_power_well(display, power_well, true);
/* Poll for phypwrgood signal */
if (intel_de_wait_for_set(display, DISPLAY_PHY_STATUS,
@@ -1515,10 +1497,10 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
assert_chv_phy_status(display);
}
-static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
+static void chv_dpio_cmn_power_well_disable(struct intel_display *display,
struct i915_power_well *power_well)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
enum dpio_phy phy;
@@ -1539,7 +1521,7 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
intel_de_write(display, DISPLAY_PHY_CONTROL,
display->power.chv_phy_control);
- vlv_set_power_well(dev_priv, power_well, false);
+ vlv_set_power_well(display, power_well, false);
drm_dbg_kms(display->drm,
"Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
@@ -1551,9 +1533,10 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
assert_chv_phy_status(display);
}
-static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
+static void assert_chv_phy_powergate(struct intel_display *display, enum dpio_phy phy,
enum dpio_channel ch, bool override, unsigned int mask)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 reg, val, expected, actual;
/*
@@ -1563,7 +1546,7 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi
* reset (ie. the power well has been disabled at
* least once).
*/
- if (!dev_priv->display.power.chv_phy_assert[phy])
+ if (!display->power.chv_phy_assert[phy])
return;
if (ch == DPIO_CH0)
@@ -1606,7 +1589,7 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi
actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH1 |
DPIO_ALLDL_POWERDOWN_CH1, val);
- drm_WARN(&dev_priv->drm, actual != expected,
+ drm_WARN(display->drm, actual != expected,
"Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
!!(actual & DPIO_ALLDL_POWERDOWN),
!!(actual & DPIO_ANYDL_POWERDOWN),
@@ -1615,10 +1598,9 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi
reg, val);
}
-bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
+bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy,
enum dpio_channel ch, bool override)
{
- struct intel_display *display = &dev_priv->display;
struct i915_power_domains *power_domains = &display->power.domains;
bool was_override;
@@ -1653,7 +1635,6 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
bool override, unsigned int mask)
{
struct intel_display *display = to_intel_display(encoder);
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct i915_power_domains *power_domains = &display->power.domains;
enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));
enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
@@ -1677,14 +1658,15 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
assert_chv_phy_status(display);
- assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
+ assert_chv_phy_powergate(display, phy, ch, override, mask);
mutex_unlock(&power_domains->lock);
}
-static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
+static bool chv_pipe_power_well_enabled(struct intel_display *display,
struct i915_power_well *power_well)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
enum pipe pipe = PIPE_A;
bool enabled;
u32 state, ctrl;
@@ -1696,7 +1678,7 @@ static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
* We only ever set the power-on and power-gate states, anything
* else is unexpected.
*/
- drm_WARN_ON(&dev_priv->drm, state != DP_SSS_PWR_ON(pipe) &&
+ drm_WARN_ON(display->drm, state != DP_SSS_PWR_ON(pipe) &&
state != DP_SSS_PWR_GATE(pipe));
enabled = state == DP_SSS_PWR_ON(pipe);
@@ -1705,17 +1687,18 @@ static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
* is poking at the power controls too.
*/
ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe);
- drm_WARN_ON(&dev_priv->drm, ctrl << 16 != state);
+ drm_WARN_ON(display->drm, ctrl << 16 != state);
vlv_punit_put(dev_priv);
return enabled;
}
-static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
+static void chv_set_pipe_power_well(struct intel_display *display,
struct i915_power_well *power_well,
bool enable)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
enum pipe pipe = PIPE_A;
u32 state;
u32 ctrl;
@@ -1736,7 +1719,7 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl);
if (wait_for(COND, 100))
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"timeout setting power well state %08x (%08x)\n",
state,
vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM));
@@ -1747,32 +1730,33 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
vlv_punit_put(dev_priv);
}
-static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
+static void chv_pipe_power_well_sync_hw(struct intel_display *display,
struct i915_power_well *power_well)
{
- intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->display.power.chv_phy_control);
+ intel_de_write(display, DISPLAY_PHY_CONTROL,
+ display->power.chv_phy_control);
}
-static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
+static void chv_pipe_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well)
{
- chv_set_pipe_power_well(dev_priv, power_well, true);
+ chv_set_pipe_power_well(display, power_well, true);
- vlv_display_power_well_init(dev_priv);
+ vlv_display_power_well_init(display);
}
-static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
+static void chv_pipe_power_well_disable(struct intel_display *display,
struct i915_power_well *power_well)
{
- vlv_display_power_well_deinit(dev_priv);
+ vlv_display_power_well_deinit(display);
- chv_set_pipe_power_well(dev_priv, power_well, false);
+ chv_set_pipe_power_well(display, power_well, false);
}
static void
-tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
+tgl_tc_cold_request(struct intel_display *display, bool block)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
u8 tries = 0;
int ret;
@@ -1813,31 +1797,31 @@ tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
}
static void
-tgl_tc_cold_off_power_well_enable(struct drm_i915_private *i915,
+tgl_tc_cold_off_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well)
{
- tgl_tc_cold_request(i915, true);
+ tgl_tc_cold_request(display, true);
}
static void
-tgl_tc_cold_off_power_well_disable(struct drm_i915_private *i915,
+tgl_tc_cold_off_power_well_disable(struct intel_display *display,
struct i915_power_well *power_well)
{
- tgl_tc_cold_request(i915, false);
+ tgl_tc_cold_request(display, false);
}
static void
-tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private *i915,
+tgl_tc_cold_off_power_well_sync_hw(struct intel_display *display,
struct i915_power_well *power_well)
{
if (intel_power_well_refcount(power_well) > 0)
- tgl_tc_cold_off_power_well_enable(i915, power_well);
+ tgl_tc_cold_off_power_well_enable(display, power_well);
else
- tgl_tc_cold_off_power_well_disable(i915, power_well);
+ tgl_tc_cold_off_power_well_disable(display, power_well);
}
static bool
-tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv,
+tgl_tc_cold_off_power_well_is_enabled(struct intel_display *display,
struct i915_power_well *power_well)
{
/*
@@ -1847,17 +1831,18 @@ tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv,
return intel_power_well_refcount(power_well);
}
-static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv,
+static void xelpdp_aux_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
- enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
+ enum phy phy = icl_aux_pw_to_phy(display, power_well);
if (intel_phy_is_tc(dev_priv, phy))
- icl_tc_port_assert_ref_held(dev_priv, power_well,
- aux_ch_to_digital_port(dev_priv, aux_ch));
+ icl_tc_port_assert_ref_held(display, power_well,
+ aux_ch_to_digital_port(display, aux_ch));
- intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(dev_priv, aux_ch),
+ intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
@@ -1870,57 +1855,57 @@ static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv,
usleep_range(600, 1200);
}
-static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv,
+static void xelpdp_aux_power_well_disable(struct intel_display *display,
struct i915_power_well *power_well)
{
enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
- intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(dev_priv, aux_ch),
+ intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
0);
usleep_range(10, 30);
}
-static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv,
+static bool xelpdp_aux_power_well_enabled(struct intel_display *display,
struct i915_power_well *power_well)
{
enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
- return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(dev_priv, aux_ch)) &
+ return intel_de_read(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch)) &
XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
}
-static void xe2lpd_pica_power_well_enable(struct drm_i915_private *dev_priv,
+static void xe2lpd_pica_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well)
{
- intel_de_write(dev_priv, XE2LPD_PICA_PW_CTL,
+ intel_de_write(display, XE2LPD_PICA_PW_CTL,
XE2LPD_PICA_CTL_POWER_REQUEST);
- if (intel_de_wait_for_set(dev_priv, XE2LPD_PICA_PW_CTL,
+ if (intel_de_wait_for_set(display, XE2LPD_PICA_PW_CTL,
XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
- drm_dbg_kms(&dev_priv->drm, "pica power well enable timeout\n");
+ drm_dbg_kms(display->drm, "pica power well enable timeout\n");
- drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when enabled");
+ drm_WARN(display->drm, 1, "Power well PICA timeout when enabled");
}
}
-static void xe2lpd_pica_power_well_disable(struct drm_i915_private *dev_priv,
+static void xe2lpd_pica_power_well_disable(struct intel_display *display,
struct i915_power_well *power_well)
{
- intel_de_write(dev_priv, XE2LPD_PICA_PW_CTL, 0);
+ intel_de_write(display, XE2LPD_PICA_PW_CTL, 0);
- if (intel_de_wait_for_clear(dev_priv, XE2LPD_PICA_PW_CTL,
+ if (intel_de_wait_for_clear(display, XE2LPD_PICA_PW_CTL,
XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
- drm_dbg_kms(&dev_priv->drm, "pica power well disable timeout\n");
+ drm_dbg_kms(display->drm, "pica power well disable timeout\n");
- drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when disabled");
+ drm_WARN(display->drm, 1, "Power well PICA timeout when disabled");
}
}
-static bool xe2lpd_pica_power_well_enabled(struct drm_i915_private *dev_priv,
+static bool xe2lpd_pica_power_well_enabled(struct intel_display *display,
struct i915_power_well *power_well)
{
- return intel_de_read(dev_priv, XE2LPD_PICA_PW_CTL) &
+ return intel_de_read(display, XE2LPD_PICA_PW_CTL) &
XE2LPD_PICA_CTL_POWER_STATUS;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index 0c12ca46dfc8..338379dae44c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -10,7 +10,6 @@
#include "intel_display_power.h"
#include "intel_dpio_phy.h"
-struct drm_i915_private;
struct i915_power_well_ops;
struct intel_display;
struct intel_encoder;
@@ -127,23 +126,23 @@ struct i915_power_well {
u8 instance_idx;
};
-struct i915_power_well *lookup_power_well(struct drm_i915_private *i915,
+struct i915_power_well *lookup_power_well(struct intel_display *display,
enum i915_power_well_id id);
-void intel_power_well_enable(struct drm_i915_private *i915,
+void intel_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well);
-void intel_power_well_disable(struct drm_i915_private *i915,
+void intel_power_well_disable(struct intel_display *display,
struct i915_power_well *power_well);
-void intel_power_well_sync_hw(struct drm_i915_private *i915,
+void intel_power_well_sync_hw(struct intel_display *display,
struct i915_power_well *power_well);
-void intel_power_well_get(struct drm_i915_private *i915,
+void intel_power_well_get(struct intel_display *display,
struct i915_power_well *power_well);
-void intel_power_well_put(struct drm_i915_private *i915,
+void intel_power_well_put(struct intel_display *display,
struct i915_power_well *power_well);
-bool intel_power_well_is_enabled(struct drm_i915_private *i915,
+bool intel_power_well_is_enabled(struct intel_display *display,
struct i915_power_well *power_well);
bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well);
-bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
+bool intel_display_power_well_is_enabled(struct intel_display *display,
enum i915_power_well_id power_well_id);
bool intel_power_well_is_always_on(struct i915_power_well *power_well);
const char *intel_power_well_name(struct i915_power_well *power_well);
@@ -152,7 +151,7 @@ int intel_power_well_refcount(struct i915_power_well *power_well);
void chv_phy_powergate_lanes(struct intel_encoder *encoder,
bool override, unsigned int mask);
-bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
+bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy,
enum dpio_channel ch, bool override);
void gen9_enable_dc5(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 0f12f2c3467c..eb3053ff9afa 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -855,6 +855,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -871,7 +872,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
*/
if (ch == DPIO_CH0 && pipe == PIPE_B)
dig_port->release_cl2_override =
- !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
+ !chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, true);
chv_phy_powergate_lanes(encoder, true, lane_mask);
@@ -1013,11 +1014,11 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
void chv_phy_release_cl2_override(struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
if (dig_port->release_cl2_override) {
- chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
+ chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, false);
dig_port->release_cl2_override = false;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b368584f481d..f6e68a0e3b6d 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -349,7 +349,7 @@ static bool hdcp_key_loadable(struct intel_display *display)
/* PG1 (power well #1) needs to be enabled */
with_intel_runtime_pm(&i915->runtime_pm, wakeref)
- enabled = intel_display_power_well_is_enabled(i915, id);
+ enabled = intel_display_power_well_is_enabled(display, id);
/*
* Another req for hdcp key loadability is enabled state of pll for
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 093fe37a3983..244865e0cc57 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -134,7 +134,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
*/
if (!pll_enabled) {
release_cl_override = display->platform.cherryview &&
- !chv_phy_powergate_ch(dev_priv, phy, ch, true);
+ !chv_phy_powergate_ch(display, phy, ch, true);
if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) {
drm_err(display->drm,
@@ -163,7 +163,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
vlv_force_pll_off(dev_priv, pipe);
if (release_cl_override)
- chv_phy_powergate_ch(dev_priv, phy, ch, false);
+ chv_phy_powergate_ch(display, phy, ch, false);
}
}
--
2.39.5
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 4/6] drm/i915/display: convert power domain code internally to struct intel_display
2024-11-28 15:38 [PATCH v2 0/6] drm/i915/display: power conversion to struct intel_display Jani Nikula
` (2 preceding siblings ...)
2024-11-28 15:38 ` [PATCH v2 3/6] drm/i915/display: convert power wells " Jani Nikula
@ 2024-11-28 15:38 ` Jani Nikula
2024-11-29 14:17 ` Imre Deak
2024-11-28 15:38 ` [PATCH v2 5/6] drm/i915/display: convert high level power interfaces " Jani Nikula
` (7 subsequent siblings)
11 siblings, 1 reply; 17+ messages in thread
From: Jani Nikula @ 2024-11-28 15:38 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: imre.deak, jani.nikula
Going forward, struct intel_display is the main device data structure
for display. Convert intel_display_power.c internally first, leaving
external interfaces for follow-up.
v2: Rebase, checkpatch fixes
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../drm/i915/display/intel_display_power.c | 806 +++++++++---------
1 file changed, 414 insertions(+), 392 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index ade7192c0461..4043d6971c3e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -198,14 +198,13 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
}
}
-static bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
+static bool __intel_display_power_is_enabled(struct intel_display *display,
enum intel_display_power_domain domain)
{
- struct intel_display *display = &dev_priv->display;
struct i915_power_well *power_well;
bool is_enabled;
- if (pm_runtime_suspended(dev_priv->drm.dev))
+ if (pm_runtime_suspended(display->drm->dev))
return false;
is_enabled = true;
@@ -243,23 +242,22 @@ static bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain)
{
- struct i915_power_domains *power_domains;
+ struct intel_display *display = &dev_priv->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
bool ret;
- power_domains = &dev_priv->display.power.domains;
-
mutex_lock(&power_domains->lock);
- ret = __intel_display_power_is_enabled(dev_priv, domain);
+ ret = __intel_display_power_is_enabled(display, domain);
mutex_unlock(&power_domains->lock);
return ret;
}
static u32
-sanitize_target_dc_state(struct drm_i915_private *i915,
+sanitize_target_dc_state(struct intel_display *display,
u32 target_dc_state)
{
- struct i915_power_domains *power_domains = &i915->display.power.domains;
+ struct i915_power_domains *power_domains = &display->power.domains;
static const u32 states[] = {
DC_STATE_EN_UPTO_DC6,
DC_STATE_EN_UPTO_DC5,
@@ -296,15 +294,15 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
struct intel_display *display = &dev_priv->display;
struct i915_power_well *power_well;
bool dc_off_enabled;
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct i915_power_domains *power_domains = &display->power.domains;
mutex_lock(&power_domains->lock);
power_well = lookup_power_well(display, SKL_DISP_DC_OFF);
- if (drm_WARN_ON(&dev_priv->drm, !power_well))
+ if (drm_WARN_ON(display->drm, !power_well))
goto unlock;
- state = sanitize_target_dc_state(dev_priv, state);
+ state = sanitize_target_dc_state(display, state);
if (state == power_domains->target_dc_state)
goto unlock;
@@ -340,11 +338,11 @@ static void __async_put_domains_mask(struct i915_power_domains *power_domains,
static bool
assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
{
- struct drm_i915_private *i915 = container_of(power_domains,
- struct drm_i915_private,
- display.power.domains);
+ struct intel_display *display = container_of(power_domains,
+ struct intel_display,
+ power.domains);
- return !drm_WARN_ON(&i915->drm,
+ return !drm_WARN_ON(display->drm,
bitmap_intersects(power_domains->async_put_domains[0].bits,
power_domains->async_put_domains[1].bits,
POWER_DOMAIN_NUM));
@@ -353,21 +351,21 @@ assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
static bool
__async_put_domains_state_ok(struct i915_power_domains *power_domains)
{
- struct drm_i915_private *i915 = container_of(power_domains,
- struct drm_i915_private,
- display.power.domains);
+ struct intel_display *display = container_of(power_domains,
+ struct intel_display,
+ power.domains);
struct intel_power_domain_mask async_put_mask;
enum intel_display_power_domain domain;
bool err = false;
err |= !assert_async_put_domain_masks_disjoint(power_domains);
__async_put_domains_mask(power_domains, &async_put_mask);
- err |= drm_WARN_ON(&i915->drm,
+ err |= drm_WARN_ON(display->drm,
!!power_domains->async_put_wakeref !=
!bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM));
for_each_power_domain(domain, &async_put_mask)
- err |= drm_WARN_ON(&i915->drm,
+ err |= drm_WARN_ON(display->drm,
power_domains->domain_use_count[domain] != 1);
return !err;
@@ -376,27 +374,27 @@ __async_put_domains_state_ok(struct i915_power_domains *power_domains)
static void print_power_domains(struct i915_power_domains *power_domains,
const char *prefix, struct intel_power_domain_mask *mask)
{
- struct drm_i915_private *i915 = container_of(power_domains,
- struct drm_i915_private,
- display.power.domains);
+ struct intel_display *display = container_of(power_domains,
+ struct intel_display,
+ power.domains);
enum intel_display_power_domain domain;
- drm_dbg(&i915->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM));
+ drm_dbg_kms(display->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM));
for_each_power_domain(domain, mask)
- drm_dbg(&i915->drm, "%s use_count %d\n",
- intel_display_power_domain_str(domain),
- power_domains->domain_use_count[domain]);
+ drm_dbg_kms(display->drm, "%s use_count %d\n",
+ intel_display_power_domain_str(domain),
+ power_domains->domain_use_count[domain]);
}
static void
print_async_put_domains_state(struct i915_power_domains *power_domains)
{
- struct drm_i915_private *i915 = container_of(power_domains,
- struct drm_i915_private,
- display.power.domains);
+ struct intel_display *display = container_of(power_domains,
+ struct intel_display,
+ power.domains);
- drm_dbg(&i915->drm, "async_put_wakeref: %s\n",
- str_yes_no(power_domains->async_put_wakeref));
+ drm_dbg_kms(display->drm, "async_put_wakeref: %s\n",
+ str_yes_no(power_domains->async_put_wakeref));
print_power_domains(power_domains, "async_put_domains[0]",
&power_domains->async_put_domains[0]);
@@ -456,10 +454,11 @@ cancel_async_put_work(struct i915_power_domains *power_domains, bool sync)
}
static bool
-intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv,
+intel_display_power_grab_async_put_ref(struct intel_display *display,
enum intel_display_power_domain domain)
{
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+ struct i915_power_domains *power_domains = &display->power.domains;
struct intel_power_domain_mask async_put_mask;
bool ret = false;
@@ -485,14 +484,13 @@ intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv,
}
static void
-__intel_display_power_get_domain(struct drm_i915_private *dev_priv,
+__intel_display_power_get_domain(struct intel_display *display,
enum intel_display_power_domain domain)
{
- struct intel_display *display = &dev_priv->display;
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *power_well;
- if (intel_display_power_grab_async_put_ref(dev_priv, domain))
+ if (intel_display_power_grab_async_put_ref(display, domain))
return;
for_each_power_domain_well(display, power_well, domain)
@@ -516,11 +514,12 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain)
{
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct intel_display *display = &dev_priv->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
intel_wakeref_t wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
mutex_lock(&power_domains->lock);
- __intel_display_power_get_domain(dev_priv, domain);
+ __intel_display_power_get_domain(display, domain);
mutex_unlock(&power_domains->lock);
return wakeref;
@@ -542,7 +541,8 @@ intel_wakeref_t
intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain)
{
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct intel_display *display = &dev_priv->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
intel_wakeref_t wakeref;
bool is_enabled;
@@ -552,8 +552,8 @@ intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
mutex_lock(&power_domains->lock);
- if (__intel_display_power_is_enabled(dev_priv, domain)) {
- __intel_display_power_get_domain(dev_priv, domain);
+ if (__intel_display_power_is_enabled(display, domain)) {
+ __intel_display_power_get_domain(display, domain);
is_enabled = true;
} else {
is_enabled = false;
@@ -570,22 +570,19 @@ intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
}
static void
-__intel_display_power_put_domain(struct drm_i915_private *dev_priv,
+__intel_display_power_put_domain(struct intel_display *display,
enum intel_display_power_domain domain)
{
- struct intel_display *display = &dev_priv->display;
- struct i915_power_domains *power_domains;
+ struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *power_well;
const char *name = intel_display_power_domain_str(domain);
struct intel_power_domain_mask async_put_mask;
- power_domains = &dev_priv->display.power.domains;
-
- drm_WARN(&dev_priv->drm, !power_domains->domain_use_count[domain],
+ drm_WARN(display->drm, !power_domains->domain_use_count[domain],
"Use count on domain %s is already zero\n",
name);
async_put_domains_mask(power_domains, &async_put_mask);
- drm_WARN(&dev_priv->drm,
+ drm_WARN(display->drm,
test_bit(domain, async_put_mask.bits),
"Async disabling of domain %s is pending\n",
name);
@@ -596,13 +593,13 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
intel_power_well_put(display, power_well);
}
-static void __intel_display_power_put(struct drm_i915_private *dev_priv,
+static void __intel_display_power_put(struct intel_display *display,
enum intel_display_power_domain domain)
{
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct i915_power_domains *power_domains = &display->power.domains;
mutex_lock(&power_domains->lock);
- __intel_display_power_put_domain(dev_priv, domain);
+ __intel_display_power_put_domain(display, domain);
mutex_unlock(&power_domains->lock);
}
@@ -611,23 +608,24 @@ queue_async_put_domains_work(struct i915_power_domains *power_domains,
intel_wakeref_t wakeref,
int delay_ms)
{
- struct drm_i915_private *i915 = container_of(power_domains,
- struct drm_i915_private,
- display.power.domains);
- drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref);
+ struct intel_display *display = container_of(power_domains,
+ struct intel_display,
+ power.domains);
+ drm_WARN_ON(display->drm, power_domains->async_put_wakeref);
power_domains->async_put_wakeref = wakeref;
- drm_WARN_ON(&i915->drm, !queue_delayed_work(system_unbound_wq,
- &power_domains->async_put_work,
- msecs_to_jiffies(delay_ms)));
+ drm_WARN_ON(display->drm, !queue_delayed_work(system_unbound_wq,
+ &power_domains->async_put_work,
+ msecs_to_jiffies(delay_ms)));
}
static void
release_async_put_domains(struct i915_power_domains *power_domains,
struct intel_power_domain_mask *mask)
{
- struct drm_i915_private *dev_priv =
- container_of(power_domains, struct drm_i915_private,
- display.power.domains);
+ struct intel_display *display = container_of(power_domains,
+ struct intel_display,
+ power.domains);
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
enum intel_display_power_domain domain;
intel_wakeref_t wakeref;
@@ -637,7 +635,7 @@ release_async_put_domains(struct i915_power_domains *power_domains,
for_each_power_domain(domain, mask) {
/* Clear before put, so put's sanity check is happy. */
async_put_domains_clear_domain(power_domains, domain);
- __intel_display_power_put_domain(dev_priv, domain);
+ __intel_display_power_put_domain(display, domain);
}
intel_runtime_pm_put(rpm, wakeref);
@@ -646,10 +644,10 @@ release_async_put_domains(struct i915_power_domains *power_domains,
static void
intel_display_power_put_async_work(struct work_struct *work)
{
- struct drm_i915_private *dev_priv =
- container_of(work, struct drm_i915_private,
- display.power.domains.async_put_work.work);
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct intel_display *display = container_of(work, struct intel_display,
+ power.domains.async_put_work.work);
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+ struct i915_power_domains *power_domains = &display->power.domains;
struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
intel_wakeref_t new_work_wakeref = intel_runtime_pm_get_raw(rpm);
intel_wakeref_t old_work_wakeref = NULL;
@@ -715,7 +713,8 @@ void __intel_display_power_put_async(struct drm_i915_private *i915,
intel_wakeref_t wakeref,
int delay_ms)
{
- struct i915_power_domains *power_domains = &i915->display.power.domains;
+ struct intel_display *display = &i915->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
struct intel_runtime_pm *rpm = &i915->runtime_pm;
intel_wakeref_t work_wakeref = intel_runtime_pm_get_raw(rpm);
@@ -724,12 +723,12 @@ void __intel_display_power_put_async(struct drm_i915_private *i915,
mutex_lock(&power_domains->lock);
if (power_domains->domain_use_count[domain] > 1) {
- __intel_display_power_put_domain(i915, domain);
+ __intel_display_power_put_domain(display, domain);
goto out_verify;
}
- drm_WARN_ON(&i915->drm, power_domains->domain_use_count[domain] != 1);
+ drm_WARN_ON(display->drm, power_domains->domain_use_count[domain] != 1);
/* Let a pending work requeue itself or queue a new one. */
if (power_domains->async_put_wakeref) {
@@ -768,7 +767,8 @@ void __intel_display_power_put_async(struct drm_i915_private *i915,
*/
void intel_display_power_flush_work(struct drm_i915_private *i915)
{
- struct i915_power_domains *power_domains = &i915->display.power.domains;
+ struct intel_display *display = &i915->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
struct intel_power_domain_mask async_put_mask;
intel_wakeref_t work_wakeref;
@@ -793,22 +793,23 @@ void intel_display_power_flush_work(struct drm_i915_private *i915)
/**
* intel_display_power_flush_work_sync - flushes and syncs the async display power disabling work
- * @i915: i915 device instance
+ * @display: display device instance
*
* Like intel_display_power_flush_work(), but also ensure that the work
* handler function is not running any more when this function returns.
*/
static void
-intel_display_power_flush_work_sync(struct drm_i915_private *i915)
+intel_display_power_flush_work_sync(struct intel_display *display)
{
- struct i915_power_domains *power_domains = &i915->display.power.domains;
+ struct drm_i915_private *i915 = to_i915(display->drm);
+ struct i915_power_domains *power_domains = &display->power.domains;
intel_display_power_flush_work(i915);
cancel_async_put_work(power_domains, true);
verify_async_put_domains_state(power_domains);
- drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref);
+ drm_WARN_ON(display->drm, power_domains->async_put_wakeref);
}
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
@@ -826,7 +827,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain,
intel_wakeref_t wakeref)
{
- __intel_display_power_put(dev_priv, domain);
+ struct intel_display *display = &dev_priv->display;
+
+ __intel_display_power_put(display, domain);
intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
}
#else
@@ -846,7 +849,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain)
{
- __intel_display_power_put(dev_priv, domain);
+ struct intel_display *display = &dev_priv->display;
+
+ __intel_display_power_put(display, domain);
intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm);
}
#endif
@@ -856,9 +861,10 @@ intel_display_power_get_in_set(struct drm_i915_private *i915,
struct intel_display_power_domain_set *power_domain_set,
enum intel_display_power_domain domain)
{
+ struct intel_display *display = &i915->display;
intel_wakeref_t __maybe_unused wf;
- drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
+ drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits));
wf = intel_display_power_get(i915, domain);
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
@@ -872,9 +878,10 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
struct intel_display_power_domain_set *power_domain_set,
enum intel_display_power_domain domain)
{
+ struct intel_display *display = &i915->display;
intel_wakeref_t wf;
- drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
+ drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits));
wf = intel_display_power_get_if_enabled(i915, domain);
if (!wf)
@@ -893,9 +900,10 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
struct intel_display_power_domain_set *power_domain_set,
struct intel_power_domain_mask *mask)
{
+ struct intel_display *display = &i915->display;
enum intel_display_power_domain domain;
- drm_WARN_ON(&i915->drm,
+ drm_WARN_ON(display->drm,
!bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM));
for_each_power_domain(domain, mask) {
@@ -910,8 +918,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
}
static int
-sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
- int disable_power_well)
+sanitize_disable_power_well_option(int disable_power_well)
{
if (disable_power_well >= 0)
return !!disable_power_well;
@@ -919,27 +926,26 @@ sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
return 1;
}
-static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
- int enable_dc)
+static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc)
{
u32 mask;
int requested_dc;
int max_dc;
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(display))
return 0;
- if (DISPLAY_VER(dev_priv) >= 20)
+ if (DISPLAY_VER(display) >= 20)
max_dc = 2;
- else if (IS_DG2(dev_priv))
+ else if (display->platform.dg2)
max_dc = 1;
- else if (IS_DG1(dev_priv))
+ else if (display->platform.dg1)
max_dc = 3;
- else if (DISPLAY_VER(dev_priv) >= 12)
+ else if (DISPLAY_VER(display) >= 12)
max_dc = 4;
- else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
+ else if (display->platform.geminilake || display->platform.broxton)
max_dc = 1;
- else if (DISPLAY_VER(dev_priv) >= 9)
+ else if (DISPLAY_VER(display) >= 9)
max_dc = 2;
else
max_dc = 0;
@@ -949,11 +955,10 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
* not depending on the DMC firmware. It's needed by system
* suspend/resume, so allow it unconditionally.
*/
- mask = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ||
- DISPLAY_VER(dev_priv) >= 11 ?
- DC_STATE_EN_DC9 : 0;
+ mask = display->platform.geminilake || display->platform.broxton ||
+ DISPLAY_VER(display) >= 11 ? DC_STATE_EN_DC9 : 0;
- if (!dev_priv->display.params.disable_power_well)
+ if (!display->params.disable_power_well)
max_dc = 0;
if (enable_dc >= 0 && enable_dc <= max_dc) {
@@ -961,12 +966,12 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
} else if (enable_dc == -1) {
requested_dc = max_dc;
} else if (enable_dc > max_dc && enable_dc <= 4) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Adjusting requested max DC state (%d->%d)\n",
enable_dc, max_dc);
requested_dc = max_dc;
} else {
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"Unexpected value for enable_dc (%d)\n", enable_dc);
requested_dc = max_dc;
}
@@ -986,7 +991,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
break;
}
- drm_dbg_kms(&dev_priv->drm, "Allowed DC state mask %02x\n", mask);
+ drm_dbg_kms(display->drm, "Allowed DC state mask %02x\n", mask);
return mask;
}
@@ -1000,16 +1005,16 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
*/
int intel_power_domains_init(struct drm_i915_private *dev_priv)
{
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct intel_display *display = &dev_priv->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
- dev_priv->display.params.disable_power_well =
- sanitize_disable_power_well_option(dev_priv,
- dev_priv->display.params.disable_power_well);
+ display->params.disable_power_well =
+ sanitize_disable_power_well_option(display->params.disable_power_well);
power_domains->allowed_dc_mask =
- get_allowed_dc_mask(dev_priv, dev_priv->display.params.enable_dc);
+ get_allowed_dc_mask(display, display->params.enable_dc);
power_domains->target_dc_state =
- sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
+ sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
mutex_init(&power_domains->lock);
@@ -1027,13 +1032,14 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
*/
void intel_power_domains_cleanup(struct drm_i915_private *dev_priv)
{
- intel_display_power_map_cleanup(&dev_priv->display.power.domains);
+ struct intel_display *display = &dev_priv->display;
+
+ intel_display_power_map_cleanup(&display->power.domains);
}
-static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
+static void intel_power_domains_sync_hw(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *power_well;
mutex_lock(&power_domains->lock);
@@ -1042,19 +1048,19 @@ static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
mutex_unlock(&power_domains->lock);
}
-static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv,
+static void gen9_dbuf_slice_set(struct intel_display *display,
enum dbuf_slice slice, bool enable)
{
i915_reg_t reg = DBUF_CTL_S(slice);
bool state;
- intel_de_rmw(dev_priv, reg, DBUF_POWER_REQUEST,
+ intel_de_rmw(display, reg, DBUF_POWER_REQUEST,
enable ? DBUF_POWER_REQUEST : 0);
- intel_de_posting_read(dev_priv, reg);
+ intel_de_posting_read(display, reg);
udelay(10);
- state = intel_de_read(dev_priv, reg) & DBUF_POWER_STATE;
- drm_WARN(&dev_priv->drm, enable != state,
+ state = intel_de_read(display, reg) & DBUF_POWER_STATE;
+ drm_WARN(display->drm, enable != state,
"DBuf slice %d power %s timeout!\n",
slice, str_enable_disable(enable));
}
@@ -1062,15 +1068,16 @@ static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv,
void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices)
{
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
- u8 slice_mask = DISPLAY_INFO(dev_priv)->dbuf.slice_mask;
+ struct intel_display *display = &dev_priv->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
+ u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask;
enum dbuf_slice slice;
- drm_WARN(&dev_priv->drm, req_slices & ~slice_mask,
+ drm_WARN(display->drm, req_slices & ~slice_mask,
"Invalid set of dbuf slices (0x%x) requested (total dbuf slices 0x%x)\n",
req_slices, slice_mask);
- drm_dbg_kms(&dev_priv->drm, "Updating dbuf slices to 0x%x\n",
+ drm_dbg_kms(display->drm, "Updating dbuf slices to 0x%x\n",
req_slices);
/*
@@ -1082,24 +1089,24 @@ void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
*/
mutex_lock(&power_domains->lock);
- for_each_dbuf_slice(dev_priv, slice)
- gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice));
+ for_each_dbuf_slice(display, slice)
+ gen9_dbuf_slice_set(display, slice, req_slices & BIT(slice));
- dev_priv->display.dbuf.enabled_slices = req_slices;
+ display->dbuf.enabled_slices = req_slices;
mutex_unlock(&power_domains->lock);
}
-static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
+static void gen9_dbuf_enable(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u8 slices_mask;
- dev_priv->display.dbuf.enabled_slices =
- intel_enabled_dbuf_slices_mask(dev_priv);
+ display->dbuf.enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
- slices_mask = BIT(DBUF_S1) | dev_priv->display.dbuf.enabled_slices;
+ slices_mask = BIT(DBUF_S1) | display->dbuf.enabled_slices;
- if (DISPLAY_VER(dev_priv) >= 14)
+ if (DISPLAY_VER(display) >= 14)
intel_pmdemand_program_dbuf(dev_priv, slices_mask);
/*
@@ -1109,33 +1116,35 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
gen9_dbuf_slices_update(dev_priv, slices_mask);
}
-static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
+static void gen9_dbuf_disable(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
gen9_dbuf_slices_update(dev_priv, 0);
- if (DISPLAY_VER(dev_priv) >= 14)
+ if (DISPLAY_VER(display) >= 14)
intel_pmdemand_program_dbuf(dev_priv, 0);
}
-static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
+static void gen12_dbuf_slices_config(struct intel_display *display)
{
enum dbuf_slice slice;
- if (IS_ALDERLAKE_P(dev_priv))
+ if (display->platform.alderlake_p)
return;
- for_each_dbuf_slice(dev_priv, slice)
- intel_de_rmw(dev_priv, DBUF_CTL_S(slice),
+ for_each_dbuf_slice(display, slice)
+ intel_de_rmw(display, DBUF_CTL_S(slice),
DBUF_TRACKER_STATE_SERVICE_MASK,
DBUF_TRACKER_STATE_SERVICE(8));
}
-static void icl_mbus_init(struct drm_i915_private *dev_priv)
+static void icl_mbus_init(struct intel_display *display)
{
- unsigned long abox_regs = DISPLAY_INFO(dev_priv)->abox_mask;
+ unsigned long abox_regs = DISPLAY_INFO(display)->abox_mask;
u32 mask, val, i;
- if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
+ if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
return;
mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK |
@@ -1152,16 +1161,16 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
* expect us to program the abox_ctl0 register as well, even though
* we don't have to program other instance-0 registers like BW_BUDDY.
*/
- if (DISPLAY_VER(dev_priv) == 12)
+ if (DISPLAY_VER(display) == 12)
abox_regs |= BIT(0);
for_each_set_bit(i, &abox_regs, sizeof(abox_regs))
- intel_de_rmw(dev_priv, MBUS_ABOX_CTL(i), mask, val);
+ intel_de_rmw(display, MBUS_ABOX_CTL(i), mask, val);
}
-static void hsw_assert_cdclk(struct drm_i915_private *dev_priv)
+static void hsw_assert_cdclk(struct intel_display *display)
{
- u32 val = intel_de_read(dev_priv, LCPLL_CTL);
+ u32 val = intel_de_read(display, LCPLL_CTL);
/*
* The LCPLL register should be turned on by the BIOS. For now
@@ -1170,18 +1179,18 @@ static void hsw_assert_cdclk(struct drm_i915_private *dev_priv)
*/
if (val & LCPLL_CD_SOURCE_FCLK)
- drm_err(&dev_priv->drm, "CDCLK source is not LCPLL\n");
+ drm_err(display->drm, "CDCLK source is not LCPLL\n");
if (val & LCPLL_PLL_DISABLE)
- drm_err(&dev_priv->drm, "LCPLL is disabled\n");
+ drm_err(display->drm, "LCPLL is disabled\n");
if ((val & LCPLL_REF_MASK) != LCPLL_REF_NON_SSC)
- drm_err(&dev_priv->drm, "LCPLL not using non-SSC reference\n");
+ drm_err(display->drm, "LCPLL not using non-SSC reference\n");
}
-static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
+static void assert_can_disable_lcpll(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_crtc *crtc;
for_each_intel_crtc(display->drm, crtc)
@@ -1206,7 +1215,7 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
INTEL_DISPLAY_STATE_WARN(display,
intel_de_read(display, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
"CPU PWM1 enabled\n");
- if (IS_HASWELL(dev_priv))
+ if (display->platform.haswell)
INTEL_DISPLAY_STATE_WARN(display,
intel_de_read(display, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
"CPU PWM2 enabled\n");
@@ -1230,23 +1239,24 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
"IRQs enabled\n");
}
-static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
+static u32 hsw_read_dcomp(struct intel_display *display)
{
- if (IS_HASWELL(dev_priv))
- return intel_de_read(dev_priv, D_COMP_HSW);
+ if (display->platform.haswell)
+ return intel_de_read(display, D_COMP_HSW);
else
- return intel_de_read(dev_priv, D_COMP_BDW);
+ return intel_de_read(display, D_COMP_BDW);
}
-static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
+static void hsw_write_dcomp(struct intel_display *display, u32 val)
{
- if (IS_HASWELL(dev_priv)) {
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
+ if (display->platform.haswell) {
if (snb_pcode_write(&dev_priv->uncore, GEN6_PCODE_WRITE_D_COMP, val))
- drm_dbg_kms(&dev_priv->drm,
- "Failed to write to D_COMP\n");
+ drm_dbg_kms(display->drm, "Failed to write to D_COMP\n");
} else {
- intel_de_write(dev_priv, D_COMP_BDW, val);
- intel_de_posting_read(dev_priv, D_COMP_BDW);
+ intel_de_write(display, D_COMP_BDW, val);
+ intel_de_posting_read(display, D_COMP_BDW);
}
}
@@ -1258,45 +1268,45 @@ static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
* register. Callers should take care of disabling all the display engine
* functions, doing the mode unset, fixing interrupts, etc.
*/
-static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
+static void hsw_disable_lcpll(struct intel_display *display,
bool switch_to_fclk, bool allow_power_down)
{
u32 val;
- assert_can_disable_lcpll(dev_priv);
+ assert_can_disable_lcpll(display);
- val = intel_de_read(dev_priv, LCPLL_CTL);
+ val = intel_de_read(display, LCPLL_CTL);
if (switch_to_fclk) {
val |= LCPLL_CD_SOURCE_FCLK;
- intel_de_write(dev_priv, LCPLL_CTL, val);
+ intel_de_write(display, LCPLL_CTL, val);
- if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) &
+ if (wait_for_us(intel_de_read(display, LCPLL_CTL) &
LCPLL_CD_SOURCE_FCLK_DONE, 1))
- drm_err(&dev_priv->drm, "Switching to FCLK failed\n");
+ drm_err(display->drm, "Switching to FCLK failed\n");
- val = intel_de_read(dev_priv, LCPLL_CTL);
+ val = intel_de_read(display, LCPLL_CTL);
}
val |= LCPLL_PLL_DISABLE;
- intel_de_write(dev_priv, LCPLL_CTL, val);
- intel_de_posting_read(dev_priv, LCPLL_CTL);
+ intel_de_write(display, LCPLL_CTL, val);
+ intel_de_posting_read(display, LCPLL_CTL);
- if (intel_de_wait_for_clear(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 1))
- drm_err(&dev_priv->drm, "LCPLL still locked\n");
+ if (intel_de_wait_for_clear(display, LCPLL_CTL, LCPLL_PLL_LOCK, 1))
+ drm_err(display->drm, "LCPLL still locked\n");
- val = hsw_read_dcomp(dev_priv);
+ val = hsw_read_dcomp(display);
val |= D_COMP_COMP_DISABLE;
- hsw_write_dcomp(dev_priv, val);
+ hsw_write_dcomp(display, val);
ndelay(100);
- if (wait_for((hsw_read_dcomp(dev_priv) &
+ if (wait_for((hsw_read_dcomp(display) &
D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
- drm_err(&dev_priv->drm, "D_COMP RCOMP still in progress\n");
+ drm_err(display->drm, "D_COMP RCOMP still in progress\n");
if (allow_power_down) {
- intel_de_rmw(dev_priv, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW);
- intel_de_posting_read(dev_priv, LCPLL_CTL);
+ intel_de_rmw(display, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW);
+ intel_de_posting_read(display, LCPLL_CTL);
}
}
@@ -1304,12 +1314,12 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
* Fully restores LCPLL, disallowing power down and switching back to LCPLL
* source.
*/
-static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
+static void hsw_restore_lcpll(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm);
u32 val;
- val = intel_de_read(dev_priv, LCPLL_CTL);
+ val = intel_de_read(display, LCPLL_CTL);
if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
@@ -1323,28 +1333,28 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
if (val & LCPLL_POWER_DOWN_ALLOW) {
val &= ~LCPLL_POWER_DOWN_ALLOW;
- intel_de_write(dev_priv, LCPLL_CTL, val);
- intel_de_posting_read(dev_priv, LCPLL_CTL);
+ intel_de_write(display, LCPLL_CTL, val);
+ intel_de_posting_read(display, LCPLL_CTL);
}
- val = hsw_read_dcomp(dev_priv);
+ val = hsw_read_dcomp(display);
val |= D_COMP_COMP_FORCE;
val &= ~D_COMP_COMP_DISABLE;
- hsw_write_dcomp(dev_priv, val);
+ hsw_write_dcomp(display, val);
- val = intel_de_read(dev_priv, LCPLL_CTL);
+ val = intel_de_read(display, LCPLL_CTL);
val &= ~LCPLL_PLL_DISABLE;
- intel_de_write(dev_priv, LCPLL_CTL, val);
+ intel_de_write(display, LCPLL_CTL, val);
- if (intel_de_wait_for_set(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 5))
- drm_err(&dev_priv->drm, "LCPLL not locked yet\n");
+ if (intel_de_wait_for_set(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5))
+ drm_err(display->drm, "LCPLL not locked yet\n");
if (val & LCPLL_CD_SOURCE_FCLK) {
- intel_de_rmw(dev_priv, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0);
+ intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0);
- if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &
+ if (wait_for_us((intel_de_read(display, LCPLL_CTL) &
LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"Switching back to LCPLL failed\n");
}
@@ -1377,36 +1387,42 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
* For more, read "Display Sequences for Package C8" on the hardware
* documentation.
*/
-static void hsw_enable_pc8(struct drm_i915_private *dev_priv)
+static void hsw_enable_pc8(struct intel_display *display)
{
- drm_dbg_kms(&dev_priv->drm, "Enabling package C8+\n");
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
+ drm_dbg_kms(display->drm, "Enabling package C8+\n");
if (HAS_PCH_LPT_LP(dev_priv))
- intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D,
+ intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
PCH_LP_PARTITION_LEVEL_DISABLE, 0);
lpt_disable_clkout_dp(dev_priv);
- hsw_disable_lcpll(dev_priv, true, true);
+ hsw_disable_lcpll(display, true, true);
}
-static void hsw_disable_pc8(struct drm_i915_private *dev_priv)
+static void hsw_disable_pc8(struct intel_display *display)
{
- drm_dbg_kms(&dev_priv->drm, "Disabling package C8+\n");
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
+ drm_dbg_kms(display->drm, "Disabling package C8+\n");
- hsw_restore_lcpll(dev_priv);
+ hsw_restore_lcpll(display);
intel_init_pch_refclk(dev_priv);
/* Many display registers don't survive PC8+ */
+#ifdef I915 /* FIXME */
intel_clock_gating_init(dev_priv);
+#endif
}
-static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
+static void intel_pch_reset_handshake(struct intel_display *display,
bool enable)
{
i915_reg_t reg;
u32 reset_bits;
- if (IS_IVYBRIDGE(dev_priv)) {
+ if (display->platform.ivybridge) {
reg = GEN7_MSG_CTL;
reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK;
} else {
@@ -1414,25 +1430,25 @@ static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
reset_bits = RESET_PCH_HANDSHAKE_ENABLE;
}
- if (DISPLAY_VER(dev_priv) >= 14)
+ if (DISPLAY_VER(display) >= 14)
reset_bits |= MTL_RESET_PICA_HANDSHAKE_EN;
- intel_de_rmw(dev_priv, reg, reset_bits, enable ? reset_bits : 0);
+ intel_de_rmw(display, reg, reset_bits, enable ? reset_bits : 0);
}
-static void skl_display_core_init(struct drm_i915_private *dev_priv,
+static void skl_display_core_init(struct intel_display *display,
bool resume)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *well;
gen9_set_dc_state(display, DC_STATE_DISABLE);
/* enable PCH reset handshake */
- intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
+ intel_pch_reset_handshake(display, !HAS_PCH_NOP(dev_priv));
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(display))
return;
/* enable PG1 and Misc I/O */
@@ -1448,25 +1464,24 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
intel_cdclk_init_hw(display);
- gen9_dbuf_enable(dev_priv);
+ gen9_dbuf_enable(display);
if (resume)
intel_dmc_load_program(display);
}
-static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
+static void skl_display_core_uninit(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *well;
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(display))
return;
gen9_disable_dc_states(display);
/* TODO: disable DMC program */
- gen9_dbuf_disable(dev_priv);
+ gen9_dbuf_disable(display);
intel_cdclk_uninit_hw(display);
@@ -1489,9 +1504,8 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
usleep_range(10, 30); /* 10 us delay per Bspec */
}
-static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume)
+static void bxt_display_core_init(struct intel_display *display, bool resume)
{
- struct intel_display *display = &dev_priv->display;
struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *well;
@@ -1503,9 +1517,9 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
* Move the handshake programming to initialization sequence.
* Previously was left up to BIOS.
*/
- intel_pch_reset_handshake(dev_priv, false);
+ intel_pch_reset_handshake(display, false);
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(display))
return;
/* Enable PG1 */
@@ -1518,25 +1532,24 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
intel_cdclk_init_hw(display);
- gen9_dbuf_enable(dev_priv);
+ gen9_dbuf_enable(display);
if (resume)
intel_dmc_load_program(display);
}
-static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
+static void bxt_display_core_uninit(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *well;
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(display))
return;
gen9_disable_dc_states(display);
/* TODO: disable DMC program */
- gen9_dbuf_disable(dev_priv);
+ gen9_dbuf_disable(display);
intel_cdclk_uninit_hw(display);
@@ -1587,20 +1600,21 @@ static const struct buddy_page_mask wa_1409767108_buddy_page_masks[] = {
{}
};
-static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
+static void tgl_bw_buddy_init(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
enum intel_dram_type type = dev_priv->dram_info.type;
u8 num_channels = dev_priv->dram_info.num_channels;
const struct buddy_page_mask *table;
- unsigned long abox_mask = DISPLAY_INFO(dev_priv)->abox_mask;
+ unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask;
int config, i;
/* BW_BUDDY registers are not used on dgpu's beyond DG1 */
- if (IS_DGFX(dev_priv) && !IS_DG1(dev_priv))
+ if (display->platform.dgfx && !display->platform.dg1)
return;
- if (IS_ALDERLAKE_S(dev_priv) ||
- (IS_ROCKETLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)))
+ if (display->platform.alderlake_s ||
+ (display->platform.rocketlake && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)))
/* Wa_1409767108 */
table = wa_1409767108_buddy_page_masks;
else
@@ -1612,29 +1626,29 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
break;
if (table[config].page_mask == 0) {
- drm_dbg(&dev_priv->drm,
- "Unknown memory configuration; disabling address buddy logic.\n");
+ drm_dbg_kms(display->drm,
+ "Unknown memory configuration; disabling address buddy logic.\n");
for_each_set_bit(i, &abox_mask, sizeof(abox_mask))
- intel_de_write(dev_priv, BW_BUDDY_CTL(i),
+ intel_de_write(display, BW_BUDDY_CTL(i),
BW_BUDDY_DISABLE);
} else {
for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) {
- intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i),
+ intel_de_write(display, BW_BUDDY_PAGE_MASK(i),
table[config].page_mask);
/* Wa_22010178259:tgl,dg1,rkl,adl-s */
- if (DISPLAY_VER(dev_priv) == 12)
- intel_de_rmw(dev_priv, BW_BUDDY_CTL(i),
+ if (DISPLAY_VER(display) == 12)
+ intel_de_rmw(display, BW_BUDDY_CTL(i),
BW_BUDDY_TLB_REQ_TIMER_MASK,
BW_BUDDY_TLB_REQ_TIMER(0x8));
}
}
}
-static void icl_display_core_init(struct drm_i915_private *dev_priv,
+static void icl_display_core_init(struct intel_display *display,
bool resume)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *well;
@@ -1643,13 +1657,13 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
/* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
- intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
+ intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0,
PCH_DPMGUNIT_CLOCK_GATE_DISABLE);
/* 1. Enable PCH reset handshake. */
- intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
+ intel_pch_reset_handshake(display, !HAS_PCH_NOP(dev_priv));
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(display))
return;
/* 2. Initialize all combo phys */
@@ -1664,63 +1678,63 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
intel_power_well_enable(display, well);
mutex_unlock(&power_domains->lock);
- if (DISPLAY_VER(dev_priv) == 14)
- intel_de_rmw(dev_priv, DC_STATE_EN,
+ if (DISPLAY_VER(display) == 14)
+ intel_de_rmw(display, DC_STATE_EN,
HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0);
/* 4. Enable CDCLK. */
intel_cdclk_init_hw(display);
- if (DISPLAY_VER(dev_priv) >= 12)
- gen12_dbuf_slices_config(dev_priv);
+ if (DISPLAY_VER(display) >= 12)
+ gen12_dbuf_slices_config(display);
/* 5. Enable DBUF. */
- gen9_dbuf_enable(dev_priv);
+ gen9_dbuf_enable(display);
/* 6. Setup MBUS. */
- icl_mbus_init(dev_priv);
+ icl_mbus_init(display);
/* 7. Program arbiter BW_BUDDY registers */
- if (DISPLAY_VER(dev_priv) >= 12)
- tgl_bw_buddy_init(dev_priv);
+ if (DISPLAY_VER(display) >= 12)
+ tgl_bw_buddy_init(display);
/* 8. Ensure PHYs have completed calibration and adaptation */
- if (IS_DG2(dev_priv))
+ if (display->platform.dg2)
intel_snps_phy_wait_for_calibration(dev_priv);
/* 9. XE2_HPD: Program CHICKEN_MISC_2 before any cursor or planes are enabled */
- if (DISPLAY_VERx100(dev_priv) == 1401)
- intel_de_rmw(dev_priv, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1);
+ if (DISPLAY_VERx100(display) == 1401)
+ intel_de_rmw(display, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1);
if (resume)
intel_dmc_load_program(display);
/* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p,dg2 */
- if (IS_DISPLAY_VERx100(dev_priv, 1200, 1300))
- intel_de_rmw(dev_priv, GEN11_CHICKEN_DCPR_2, 0,
+ if (IS_DISPLAY_VERx100(display, 1200, 1300))
+ intel_de_rmw(display, GEN11_CHICKEN_DCPR_2, 0,
DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM |
DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR);
/* Wa_14011503030:xelpd */
- if (DISPLAY_VER(dev_priv) == 13)
- intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
+ if (DISPLAY_VER(display) == 13)
+ intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
/* Wa_15013987218 */
- if (DISPLAY_VER(dev_priv) == 20) {
- intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D,
+ if (DISPLAY_VER(display) == 20) {
+ intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
0, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE);
- intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D,
+ intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 0);
}
}
-static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
+static void icl_display_core_uninit(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *well;
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(display))
return;
gen9_disable_dc_states(display);
@@ -1729,13 +1743,13 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
/* 1. Disable all display engine functions -> aready done */
/* 2. Disable DBUF */
- gen9_dbuf_disable(dev_priv);
+ gen9_dbuf_disable(display);
/* 3. Disable CD clock */
intel_cdclk_uninit_hw(display);
- if (DISPLAY_VER(dev_priv) == 14)
- intel_de_rmw(dev_priv, DC_STATE_EN, 0,
+ if (DISPLAY_VER(display) == 14)
+ intel_de_rmw(display, DC_STATE_EN, 0,
HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH);
/*
@@ -1752,9 +1766,8 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
intel_combo_phy_uninit(dev_priv);
}
-static void chv_phy_control_init(struct drm_i915_private *dev_priv)
+static void chv_phy_control_init(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
struct i915_power_well *cmn_bc =
lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);
struct i915_power_well *cmn_d =
@@ -1767,7 +1780,7 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
* power well state and lane status to reconstruct the
* expected initial value.
*/
- dev_priv->display.power.chv_phy_control =
+ display->power.chv_phy_control =
PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
@@ -1782,38 +1795,38 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
* current lane status.
*/
if (intel_power_well_is_enabled(display, cmn_bc)) {
- u32 status = intel_de_read(dev_priv, DPLL(dev_priv, PIPE_A));
+ u32 status = intel_de_read(display, DPLL(display, PIPE_A));
unsigned int mask;
mask = status & DPLL_PORTB_READY_MASK;
if (mask == 0xf)
mask = 0x0;
else
- dev_priv->display.power.chv_phy_control |=
+ display->power.chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
- dev_priv->display.power.chv_phy_control |=
+ display->power.chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
mask = (status & DPLL_PORTC_READY_MASK) >> 4;
if (mask == 0xf)
mask = 0x0;
else
- dev_priv->display.power.chv_phy_control |=
+ display->power.chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
- dev_priv->display.power.chv_phy_control |=
+ display->power.chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
- dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
+ display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
- dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = false;
+ display->power.chv_phy_assert[DPIO_PHY0] = false;
} else {
- dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = true;
+ display->power.chv_phy_assert[DPIO_PHY0] = true;
}
if (intel_power_well_is_enabled(display, cmn_d)) {
- u32 status = intel_de_read(dev_priv, DPIO_PHY_STATUS);
+ u32 status = intel_de_read(display, DPIO_PHY_STATUS);
unsigned int mask;
mask = status & DPLL_PORTD_READY_MASK;
@@ -1821,28 +1834,27 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
if (mask == 0xf)
mask = 0x0;
else
- dev_priv->display.power.chv_phy_control |=
+ display->power.chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
- dev_priv->display.power.chv_phy_control |=
+ display->power.chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
- dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
+ display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
- dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = false;
+ display->power.chv_phy_assert[DPIO_PHY1] = false;
} else {
- dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = true;
+ display->power.chv_phy_assert[DPIO_PHY1] = true;
}
- drm_dbg_kms(&dev_priv->drm, "Initial PHY_CONTROL=0x%08x\n",
- dev_priv->display.power.chv_phy_control);
+ drm_dbg_kms(display->drm, "Initial PHY_CONTROL=0x%08x\n",
+ display->power.chv_phy_control);
/* Defer application of initial phy_control to enabling the powerwell */
}
-static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
+static void vlv_cmnlane_wa(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
struct i915_power_well *cmn =
lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);
struct i915_power_well *disp2d =
@@ -1851,10 +1863,10 @@ static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
/* If the display might be already active skip this */
if (intel_power_well_is_enabled(display, cmn) &&
intel_power_well_is_enabled(display, disp2d) &&
- intel_de_read(dev_priv, DPIO_CTL) & DPIO_CMNRST)
+ intel_de_read(display, DPIO_CTL) & DPIO_CMNRST)
return;
- drm_dbg_kms(&dev_priv->drm, "toggling display PHY side reset\n");
+ drm_dbg_kms(display->drm, "toggling display PHY side reset\n");
/* cmnlane needs DPLL registers */
intel_power_well_enable(display, disp2d);
@@ -1869,8 +1881,9 @@ static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
intel_power_well_disable(display, cmn);
}
-static bool vlv_punit_is_power_gated(struct drm_i915_private *dev_priv, u32 reg0)
+static bool vlv_punit_is_power_gated(struct intel_display *display, u32 reg0)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
bool ret;
vlv_punit_get(dev_priv);
@@ -1880,14 +1893,14 @@ static bool vlv_punit_is_power_gated(struct drm_i915_private *dev_priv, u32 reg0
return ret;
}
-static void assert_ved_power_gated(struct drm_i915_private *dev_priv)
+static void assert_ved_power_gated(struct intel_display *display)
{
- drm_WARN(&dev_priv->drm,
- !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_VEDSSPM0),
+ drm_WARN(display->drm,
+ !vlv_punit_is_power_gated(display, PUNIT_REG_VEDSSPM0),
"VED not power gated\n");
}
-static void assert_isp_power_gated(struct drm_i915_private *dev_priv)
+static void assert_isp_power_gated(struct intel_display *display)
{
static const struct pci_device_id isp_ids[] = {
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0f38)},
@@ -1895,12 +1908,12 @@ static void assert_isp_power_gated(struct drm_i915_private *dev_priv)
{}
};
- drm_WARN(&dev_priv->drm, !pci_dev_present(isp_ids) &&
- !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_ISPSSPM0),
+ drm_WARN(display->drm, !pci_dev_present(isp_ids) &&
+ !vlv_punit_is_power_gated(display, PUNIT_REG_ISPSSPM0),
"ISP not power gated\n");
}
-static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
+static void intel_power_domains_verify_state(struct intel_display *display);
/**
* intel_power_domains_init_hw - initialize hardware power domain state
@@ -1920,32 +1933,33 @@ static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
*/
void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
{
- struct i915_power_domains *power_domains = &i915->display.power.domains;
+ struct intel_display *display = &i915->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
power_domains->initializing = true;
- if (DISPLAY_VER(i915) >= 11) {
- icl_display_core_init(i915, resume);
- } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
- bxt_display_core_init(i915, resume);
- } else if (DISPLAY_VER(i915) == 9) {
- skl_display_core_init(i915, resume);
- } else if (IS_CHERRYVIEW(i915)) {
+ if (DISPLAY_VER(display) >= 11) {
+ icl_display_core_init(display, resume);
+ } else if (display->platform.geminilake || display->platform.broxton) {
+ bxt_display_core_init(display, resume);
+ } else if (DISPLAY_VER(display) == 9) {
+ skl_display_core_init(display, resume);
+ } else if (display->platform.cherryview) {
mutex_lock(&power_domains->lock);
- chv_phy_control_init(i915);
+ chv_phy_control_init(display);
mutex_unlock(&power_domains->lock);
- assert_isp_power_gated(i915);
- } else if (IS_VALLEYVIEW(i915)) {
+ assert_isp_power_gated(display);
+ } else if (display->platform.valleyview) {
mutex_lock(&power_domains->lock);
- vlv_cmnlane_wa(i915);
+ vlv_cmnlane_wa(display);
mutex_unlock(&power_domains->lock);
- assert_ved_power_gated(i915);
- assert_isp_power_gated(i915);
- } else if (IS_BROADWELL(i915) || IS_HASWELL(i915)) {
- hsw_assert_cdclk(i915);
- intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
- } else if (IS_IVYBRIDGE(i915)) {
- intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
+ assert_ved_power_gated(display);
+ assert_isp_power_gated(display);
+ } else if (display->platform.broadwell || display->platform.haswell) {
+ hsw_assert_cdclk(display);
+ intel_pch_reset_handshake(display, !HAS_PCH_NOP(i915));
+ } else if (display->platform.ivybridge) {
+ intel_pch_reset_handshake(display, !HAS_PCH_NOP(i915));
}
/*
@@ -1954,17 +1968,17 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
* resources powered until display HW readout is complete. We drop
* this reference in intel_power_domains_enable().
*/
- drm_WARN_ON(&i915->drm, power_domains->init_wakeref);
+ drm_WARN_ON(display->drm, power_domains->init_wakeref);
power_domains->init_wakeref =
intel_display_power_get(i915, POWER_DOMAIN_INIT);
/* Disable power support if the user asked so. */
- if (!i915->display.params.disable_power_well) {
- drm_WARN_ON(&i915->drm, power_domains->disable_wakeref);
- i915->display.power.domains.disable_wakeref = intel_display_power_get(i915,
- POWER_DOMAIN_INIT);
+ if (!display->params.disable_power_well) {
+ drm_WARN_ON(display->drm, power_domains->disable_wakeref);
+ display->power.domains.disable_wakeref = intel_display_power_get(i915,
+ POWER_DOMAIN_INIT);
}
- intel_power_domains_sync_hw(i915);
+ intel_power_domains_sync_hw(display);
power_domains->initializing = false;
}
@@ -1982,17 +1996,18 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
*/
void intel_power_domains_driver_remove(struct drm_i915_private *i915)
{
+ struct intel_display *display = &i915->display;
intel_wakeref_t wakeref __maybe_unused =
- fetch_and_zero(&i915->display.power.domains.init_wakeref);
+ fetch_and_zero(&display->power.domains.init_wakeref);
/* Remove the refcount we took to keep power well support disabled. */
- if (!i915->display.params.disable_power_well)
+ if (!display->params.disable_power_well)
intel_display_power_put(i915, POWER_DOMAIN_INIT,
- fetch_and_zero(&i915->display.power.domains.disable_wakeref));
+ fetch_and_zero(&display->power.domains.disable_wakeref));
- intel_display_power_flush_work_sync(i915);
+ intel_display_power_flush_work_sync(display);
- intel_power_domains_verify_state(i915);
+ intel_power_domains_verify_state(display);
/* Keep the power well enabled, but cancel its rpm wakeref. */
intel_runtime_pm_put(&i915->runtime_pm, wakeref);
@@ -2011,7 +2026,7 @@ void intel_power_domains_driver_remove(struct drm_i915_private *i915)
void intel_power_domains_sanitize_state(struct drm_i915_private *i915)
{
struct intel_display *display = &i915->display;
- struct i915_power_domains *power_domains = &i915->display.power.domains;
+ struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *power_well;
mutex_lock(&power_domains->lock);
@@ -2021,7 +2036,7 @@ void intel_power_domains_sanitize_state(struct drm_i915_private *i915)
!intel_power_well_is_enabled(display, power_well))
continue;
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"BIOS left unused %s power well enabled, disabling it\n",
intel_power_well_name(power_well));
intel_power_well_disable(display, power_well);
@@ -2044,11 +2059,12 @@ void intel_power_domains_sanitize_state(struct drm_i915_private *i915)
*/
void intel_power_domains_enable(struct drm_i915_private *i915)
{
+ struct intel_display *display = &i915->display;
intel_wakeref_t wakeref __maybe_unused =
- fetch_and_zero(&i915->display.power.domains.init_wakeref);
+ fetch_and_zero(&display->power.domains.init_wakeref);
intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
- intel_power_domains_verify_state(i915);
+ intel_power_domains_verify_state(display);
}
/**
@@ -2060,13 +2076,14 @@ void intel_power_domains_enable(struct drm_i915_private *i915)
*/
void intel_power_domains_disable(struct drm_i915_private *i915)
{
- struct i915_power_domains *power_domains = &i915->display.power.domains;
+ struct intel_display *display = &i915->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
- drm_WARN_ON(&i915->drm, power_domains->init_wakeref);
+ drm_WARN_ON(display->drm, power_domains->init_wakeref);
power_domains->init_wakeref =
intel_display_power_get(i915, POWER_DOMAIN_INIT);
- intel_power_domains_verify_state(i915);
+ intel_power_domains_verify_state(display);
}
/**
@@ -2099,7 +2116,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle)
if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) && s2idle &&
intel_dmc_has_payload(display)) {
intel_display_power_flush_work(i915);
- intel_power_domains_verify_state(i915);
+ intel_power_domains_verify_state(display);
return;
}
@@ -2107,19 +2124,19 @@ void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle)
* Even if power well support was disabled we still want to disable
* power wells if power domains must be deinitialized for suspend.
*/
- if (!i915->display.params.disable_power_well)
+ if (!display->params.disable_power_well)
intel_display_power_put(i915, POWER_DOMAIN_INIT,
- fetch_and_zero(&i915->display.power.domains.disable_wakeref));
+ fetch_and_zero(&display->power.domains.disable_wakeref));
intel_display_power_flush_work(i915);
- intel_power_domains_verify_state(i915);
+ intel_power_domains_verify_state(display);
- if (DISPLAY_VER(i915) >= 11)
- icl_display_core_uninit(i915);
- else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
- bxt_display_core_uninit(i915);
- else if (DISPLAY_VER(i915) == 9)
- skl_display_core_uninit(i915);
+ if (DISPLAY_VER(display) >= 11)
+ icl_display_core_uninit(display);
+ else if (display->platform.geminilake || display->platform.broxton)
+ bxt_display_core_uninit(display);
+ else if (DISPLAY_VER(display) == 9)
+ skl_display_core_uninit(display);
power_domains->display_core_suspended = true;
}
@@ -2136,44 +2153,44 @@ void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle)
*/
void intel_power_domains_resume(struct drm_i915_private *i915)
{
- struct i915_power_domains *power_domains = &i915->display.power.domains;
+ struct intel_display *display = &i915->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
if (power_domains->display_core_suspended) {
intel_power_domains_init_hw(i915, true);
power_domains->display_core_suspended = false;
} else {
- drm_WARN_ON(&i915->drm, power_domains->init_wakeref);
+ drm_WARN_ON(display->drm, power_domains->init_wakeref);
power_domains->init_wakeref =
intel_display_power_get(i915, POWER_DOMAIN_INIT);
}
- intel_power_domains_verify_state(i915);
+ intel_power_domains_verify_state(display);
}
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
-static void intel_power_domains_dump_info(struct drm_i915_private *i915)
+static void intel_power_domains_dump_info(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
- struct i915_power_domains *power_domains = &i915->display.power.domains;
+ struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *power_well;
for_each_power_well(display, power_well) {
enum intel_display_power_domain domain;
- drm_dbg(&i915->drm, "%-25s %d\n",
- intel_power_well_name(power_well), intel_power_well_refcount(power_well));
+ drm_dbg_kms(display->drm, "%-25s %d\n",
+ intel_power_well_name(power_well), intel_power_well_refcount(power_well));
for_each_power_domain(domain, intel_power_well_domains(power_well))
- drm_dbg(&i915->drm, " %-23s %d\n",
- intel_display_power_domain_str(domain),
- power_domains->domain_use_count[domain]);
+ drm_dbg_kms(display->drm, " %-23s %d\n",
+ intel_display_power_domain_str(domain),
+ power_domains->domain_use_count[domain]);
}
}
/**
* intel_power_domains_verify_state - verify the HW/SW state for all power wells
- * @i915: i915 device instance
+ * @display: display device instance
*
* Verify if the reference count of each power well matches its HW enabled
* state and the total refcount of the domains it belongs to. This must be
@@ -2181,10 +2198,9 @@ static void intel_power_domains_dump_info(struct drm_i915_private *i915)
* acquiring reference counts for any power wells in use and disabling the
* ones left on by BIOS but not required by any active output.
*/
-static void intel_power_domains_verify_state(struct drm_i915_private *i915)
+static void intel_power_domains_verify_state(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
- struct i915_power_domains *power_domains = &i915->display.power.domains;
+ struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *power_well;
bool dump_domain_info;
@@ -2202,7 +2218,7 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
if ((intel_power_well_refcount(power_well) ||
intel_power_well_is_always_on(power_well)) !=
enabled)
- drm_err(&i915->drm,
+ drm_err(display->drm,
"power well %s state mismatch (refcount %d/enabled %d)",
intel_power_well_name(power_well),
intel_power_well_refcount(power_well), enabled);
@@ -2212,7 +2228,7 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
domains_count += power_domains->domain_use_count[domain];
if (intel_power_well_refcount(power_well) != domains_count) {
- drm_err(&i915->drm,
+ drm_err(display->drm,
"power well %s refcount/domain refcount mismatch "
"(refcount %d/domains refcount %d)\n",
intel_power_well_name(power_well),
@@ -2226,7 +2242,7 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
static bool dumped;
if (!dumped) {
- intel_power_domains_dump_info(i915);
+ intel_power_domains_dump_info(display);
dumped = true;
}
}
@@ -2236,7 +2252,7 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
#else
-static void intel_power_domains_verify_state(struct drm_i915_private *i915)
+static void intel_power_domains_verify_state(struct intel_display *display)
{
}
@@ -2248,11 +2264,11 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915, bool s2idle
intel_power_domains_suspend(i915, s2idle);
- if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
- IS_BROXTON(i915)) {
+ if (DISPLAY_VER(display) >= 11 || display->platform.geminilake ||
+ display->platform.broxton) {
bxt_enable_dc9(display);
- } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
- hsw_enable_pc8(i915);
+ } else if (display->platform.haswell || display->platform.broadwell) {
+ hsw_enable_pc8(display);
}
/* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */
@@ -2264,12 +2280,12 @@ void intel_display_power_resume_early(struct drm_i915_private *i915)
{
struct intel_display *display = &i915->display;
- if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
- IS_BROXTON(i915)) {
+ if (DISPLAY_VER(display) >= 11 || display->platform.geminilake ||
+ display->platform.broxton) {
gen9_sanitize_dc_state(display);
bxt_disable_dc9(display);
- } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
- hsw_disable_pc8(i915);
+ } else if (display->platform.haswell || display->platform.broadwell) {
+ hsw_disable_pc8(display);
}
/* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */
@@ -2283,14 +2299,14 @@ void intel_display_power_suspend(struct drm_i915_private *i915)
{
struct intel_display *display = &i915->display;
- if (DISPLAY_VER(i915) >= 11) {
- icl_display_core_uninit(i915);
+ if (DISPLAY_VER(display) >= 11) {
+ icl_display_core_uninit(display);
bxt_enable_dc9(display);
- } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
- bxt_display_core_uninit(i915);
+ } else if (display->platform.geminilake || display->platform.broxton) {
+ bxt_display_core_uninit(display);
bxt_enable_dc9(display);
- } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
- hsw_enable_pc8(i915);
+ } else if (display->platform.haswell || display->platform.broadwell) {
+ hsw_enable_pc8(display);
}
}
@@ -2299,29 +2315,30 @@ void intel_display_power_resume(struct drm_i915_private *i915)
struct intel_display *display = &i915->display;
struct i915_power_domains *power_domains = &display->power.domains;
- if (DISPLAY_VER(i915) >= 11) {
+ if (DISPLAY_VER(display) >= 11) {
bxt_disable_dc9(display);
- icl_display_core_init(i915, true);
+ icl_display_core_init(display, true);
if (intel_dmc_has_payload(display)) {
if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
skl_enable_dc6(display);
else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
gen9_enable_dc5(display);
}
- } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
+ } else if (display->platform.geminilake || display->platform.broxton) {
bxt_disable_dc9(display);
- bxt_display_core_init(i915, true);
+ bxt_display_core_init(display, true);
if (intel_dmc_has_payload(display) &&
(power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
gen9_enable_dc5(display);
- } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
- hsw_disable_pc8(i915);
+ } else if (display->platform.haswell || display->platform.broadwell) {
+ hsw_disable_pc8(display);
}
}
void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m)
{
- struct i915_power_domains *power_domains = &i915->display.power.domains;
+ struct intel_display *display = &i915->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
int i;
mutex_lock(&power_domains->lock);
@@ -2466,17 +2483,17 @@ d13_port_domains[] = {
};
static void
-intel_port_domains_for_platform(struct drm_i915_private *i915,
+intel_port_domains_for_platform(struct intel_display *display,
const struct intel_ddi_port_domains **domains,
int *domains_size)
{
- if (DISPLAY_VER(i915) >= 13) {
+ if (DISPLAY_VER(display) >= 13) {
*domains = d13_port_domains;
*domains_size = ARRAY_SIZE(d13_port_domains);
- } else if (DISPLAY_VER(i915) >= 12) {
+ } else if (DISPLAY_VER(display) >= 12) {
*domains = d12_port_domains;
*domains_size = ARRAY_SIZE(d12_port_domains);
- } else if (DISPLAY_VER(i915) >= 11) {
+ } else if (DISPLAY_VER(display) >= 11) {
*domains = d11_port_domains;
*domains_size = ARRAY_SIZE(d11_port_domains);
} else {
@@ -2486,13 +2503,13 @@ intel_port_domains_for_platform(struct drm_i915_private *i915,
}
static const struct intel_ddi_port_domains *
-intel_port_domains_for_port(struct drm_i915_private *i915, enum port port)
+intel_port_domains_for_port(struct intel_display *display, enum port port)
{
const struct intel_ddi_port_domains *domains;
int domains_size;
int i;
- intel_port_domains_for_platform(i915, &domains, &domains_size);
+ intel_port_domains_for_platform(display, &domains, &domains_size);
for (i = 0; i < domains_size; i++)
if (port >= domains[i].port_start && port <= domains[i].port_end)
return &domains[i];
@@ -2503,9 +2520,10 @@ intel_port_domains_for_port(struct drm_i915_private *i915, enum port port)
enum intel_display_power_domain
intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port)
{
- const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port);
+ struct intel_display *display = &i915->display;
+ const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port);
- if (drm_WARN_ON(&i915->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID))
+ if (drm_WARN_ON(display->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID))
return POWER_DOMAIN_PORT_DDI_IO_A;
return domains->ddi_io + (int)(port - domains->port_start);
@@ -2514,22 +2532,23 @@ intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port)
enum intel_display_power_domain
intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port)
{
- const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port);
+ struct intel_display *display = &i915->display;
+ const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port);
- if (drm_WARN_ON(&i915->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID))
+ if (drm_WARN_ON(display->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID))
return POWER_DOMAIN_PORT_DDI_LANES_A;
return domains->ddi_lanes + (int)(port - domains->port_start);
}
static const struct intel_ddi_port_domains *
-intel_port_domains_for_aux_ch(struct drm_i915_private *i915, enum aux_ch aux_ch)
+intel_port_domains_for_aux_ch(struct intel_display *display, enum aux_ch aux_ch)
{
const struct intel_ddi_port_domains *domains;
int domains_size;
int i;
- intel_port_domains_for_platform(i915, &domains, &domains_size);
+ intel_port_domains_for_platform(display, &domains, &domains_size);
for (i = 0; i < domains_size; i++)
if (aux_ch >= domains[i].aux_ch_start && aux_ch <= domains[i].aux_ch_end)
return &domains[i];
@@ -2540,9 +2559,10 @@ intel_port_domains_for_aux_ch(struct drm_i915_private *i915, enum aux_ch aux_ch)
enum intel_display_power_domain
intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
{
- const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
+ struct intel_display *display = &i915->display;
+ const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch);
- if (drm_WARN_ON(&i915->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID))
+ if (drm_WARN_ON(display->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID))
return POWER_DOMAIN_AUX_IO_A;
return domains->aux_io + (int)(aux_ch - domains->aux_ch_start);
@@ -2551,9 +2571,10 @@ intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux
enum intel_display_power_domain
intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
{
- const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
+ struct intel_display *display = &i915->display;
+ const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch);
- if (drm_WARN_ON(&i915->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID))
+ if (drm_WARN_ON(display->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID))
return POWER_DOMAIN_AUX_A;
return domains->aux_legacy_usbc + (int)(aux_ch - domains->aux_ch_start);
@@ -2562,9 +2583,10 @@ intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch
enum intel_display_power_domain
intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
{
- const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
+ struct intel_display *display = &i915->display;
+ const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch);
- if (drm_WARN_ON(&i915->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID))
+ if (drm_WARN_ON(display->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID))
return POWER_DOMAIN_AUX_TBT1;
return domains->aux_tbt + (int)(aux_ch - domains->aux_ch_start);
--
2.39.5
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 5/6] drm/i915/display: convert high level power interfaces to struct intel_display
2024-11-28 15:38 [PATCH v2 0/6] drm/i915/display: power conversion to struct intel_display Jani Nikula
` (3 preceding siblings ...)
2024-11-28 15:38 ` [PATCH v2 4/6] drm/i915/display: convert power domain code internally " Jani Nikula
@ 2024-11-28 15:38 ` Jani Nikula
2024-11-28 15:38 ` [PATCH v2 6/6] drm/i915/display: convert power map " Jani Nikula
` (6 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Jani Nikula @ 2024-11-28 15:38 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: imre.deak, jani.nikula
Going forward, struct intel_display is the main device data structure
for display. Convert the high level interfaces (init, cleanup, suspend,
resume, etc.) of intel_display_power.c over to it. The actual power
get/put etc. are left for follow-up.
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../drm/i915/display/intel_display_driver.c | 8 +-
.../gpu/drm/i915/display/intel_display_irq.c | 3 +-
.../drm/i915/display/intel_display_power.c | 78 +++++++++----------
.../drm/i915/display/intel_display_power.h | 31 ++++----
.../drm/i915/display/intel_modeset_setup.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 6 +-
drivers/gpu/drm/i915/i915_driver.c | 32 +++++---
drivers/gpu/drm/xe/display/xe_display.c | 28 ++++---
8 files changed, 98 insertions(+), 90 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 2a6301b8674a..2ef5aeb04bd5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -226,13 +226,13 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
goto cleanup_bios;
/* FIXME: completely on the wrong abstraction layer */
- ret = intel_power_domains_init(i915);
+ ret = intel_power_domains_init(display);
if (ret < 0)
goto cleanup_vga;
intel_pmdemand_init_early(i915);
- intel_power_domains_init_hw(i915, false);
+ intel_power_domains_init_hw(display, false);
if (!HAS_DISPLAY(i915))
return 0;
@@ -273,7 +273,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
cleanup_vga_client_pw_domain_dmc:
intel_dmc_fini(display);
- intel_power_domains_driver_remove(i915);
+ intel_power_domains_driver_remove(display);
cleanup_vga:
intel_vga_unregister(display);
cleanup_bios:
@@ -624,7 +624,7 @@ void intel_display_driver_remove_nogem(struct drm_i915_private *i915)
intel_dmc_fini(display);
- intel_power_domains_driver_remove(i915);
+ intel_power_domains_driver_remove(display);
intel_vga_unregister(display);
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index cb79c2796e3a..069043f9d894 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1423,7 +1423,6 @@ static void intel_display_vblank_dc_work(struct work_struct *work)
{
struct intel_display *display =
container_of(work, typeof(*display), irq.vblank_dc_work);
- struct drm_i915_private *i915 = to_i915(display->drm);
int vblank_wa_num_pipes = READ_ONCE(display->irq.vblank_wa_num_pipes);
/*
@@ -1432,7 +1431,7 @@ static void intel_display_vblank_dc_work(struct work_struct *work)
* PSR code. If DC3CO is taken into use we need take that into account
* here as well.
*/
- intel_display_power_set_target_dc_state(i915, vblank_wa_num_pipes ? DC_STATE_DISABLE :
+ intel_display_power_set_target_dc_state(display, vblank_wa_num_pipes ? DC_STATE_DISABLE :
DC_STATE_EN_UPTO_DC6);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 4043d6971c3e..34465d56def0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -281,17 +281,16 @@ sanitize_target_dc_state(struct intel_display *display,
/**
* intel_display_power_set_target_dc_state - Set target dc state.
- * @dev_priv: i915 device
+ * @display: display device
* @state: state which needs to be set as target_dc_state.
*
* This function set the "DC off" power well target_dc_state,
* based upon this target_dc_stste, "DC off" power well will
* enable desired DC state.
*/
-void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
+void intel_display_power_set_target_dc_state(struct intel_display *display,
u32 state)
{
- struct intel_display *display = &dev_priv->display;
struct i915_power_well *power_well;
bool dc_off_enabled;
struct i915_power_domains *power_domains = &display->power.domains;
@@ -998,14 +997,13 @@ static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc)
/**
* intel_power_domains_init - initializes the power domain structures
- * @dev_priv: i915 device instance
+ * @display: display device instance
*
* Initializes the power domain structures for @dev_priv depending upon the
* supported platform.
*/
-int intel_power_domains_init(struct drm_i915_private *dev_priv)
+int intel_power_domains_init(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
struct i915_power_domains *power_domains = &display->power.domains;
display->params.disable_power_well =
@@ -1026,14 +1024,12 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
/**
* intel_power_domains_cleanup - clean up power domains resources
- * @dev_priv: i915 device instance
+ * @display: display device instance
*
* Release any resources acquired by intel_power_domains_init()
*/
-void intel_power_domains_cleanup(struct drm_i915_private *dev_priv)
+void intel_power_domains_cleanup(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
-
intel_display_power_map_cleanup(&display->power.domains);
}
@@ -1917,7 +1913,7 @@ static void intel_power_domains_verify_state(struct intel_display *display);
/**
* intel_power_domains_init_hw - initialize hardware power domain state
- * @i915: i915 device instance
+ * @display: display device instance
* @resume: Called from resume code paths or not
*
* This function initializes the hardware power domain state and enables all
@@ -1931,9 +1927,9 @@ static void intel_power_domains_verify_state(struct intel_display *display);
* intel_power_domains_enable()) and must be paired with
* intel_power_domains_driver_remove().
*/
-void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
+void intel_power_domains_init_hw(struct intel_display *display, bool resume)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
struct i915_power_domains *power_domains = &display->power.domains;
power_domains->initializing = true;
@@ -1985,7 +1981,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
/**
* intel_power_domains_driver_remove - deinitialize hw power domain state
- * @i915: i915 device instance
+ * @display: display device instance
*
* De-initializes the display power domain HW state. It also ensures that the
* device stays powered up so that the driver can be reloaded.
@@ -1994,9 +1990,9 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
* intel_power_domains_disable()) and must be paired with
* intel_power_domains_init_hw().
*/
-void intel_power_domains_driver_remove(struct drm_i915_private *i915)
+void intel_power_domains_driver_remove(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
intel_wakeref_t wakeref __maybe_unused =
fetch_and_zero(&display->power.domains.init_wakeref);
@@ -2015,7 +2011,7 @@ void intel_power_domains_driver_remove(struct drm_i915_private *i915)
/**
* intel_power_domains_sanitize_state - sanitize power domains state
- * @i915: i915 device instance
+ * @display: display device instance
*
* Sanitize the power domains state during driver loading and system resume.
* The function will disable all display power wells that BIOS has enabled
@@ -2023,9 +2019,8 @@ void intel_power_domains_driver_remove(struct drm_i915_private *i915)
* on it by the time this function is called, after the state of all the
* pipe, encoder, etc. HW resources have been sanitized).
*/
-void intel_power_domains_sanitize_state(struct drm_i915_private *i915)
+void intel_power_domains_sanitize_state(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *power_well;
@@ -2047,7 +2042,7 @@ void intel_power_domains_sanitize_state(struct drm_i915_private *i915)
/**
* intel_power_domains_enable - enable toggling of display power wells
- * @i915: i915 device instance
+ * @display: display device instance
*
* Enable the ondemand enabling/disabling of the display power wells. Note that
* power wells not belonging to POWER_DOMAIN_INIT are allowed to be toggled
@@ -2057,9 +2052,9 @@ void intel_power_domains_sanitize_state(struct drm_i915_private *i915)
* of display HW readout (which will acquire the power references reflecting
* the current HW state).
*/
-void intel_power_domains_enable(struct drm_i915_private *i915)
+void intel_power_domains_enable(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
intel_wakeref_t wakeref __maybe_unused =
fetch_and_zero(&display->power.domains.init_wakeref);
@@ -2069,14 +2064,14 @@ void intel_power_domains_enable(struct drm_i915_private *i915)
/**
* intel_power_domains_disable - disable toggling of display power wells
- * @i915: i915 device instance
+ * @display: display device instance
*
* Disable the ondemand enabling/disabling of the display power wells. See
* intel_power_domains_enable() for which power wells this call controls.
*/
-void intel_power_domains_disable(struct drm_i915_private *i915)
+void intel_power_domains_disable(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
struct i915_power_domains *power_domains = &display->power.domains;
drm_WARN_ON(display->drm, power_domains->init_wakeref);
@@ -2088,7 +2083,7 @@ void intel_power_domains_disable(struct drm_i915_private *i915)
/**
* intel_power_domains_suspend - suspend power domain state
- * @i915: i915 device instance
+ * @display: display device instance
* @s2idle: specifies whether we go to idle, or deeper sleep
*
* This function prepares the hardware power domain state before entering
@@ -2097,9 +2092,9 @@ void intel_power_domains_disable(struct drm_i915_private *i915)
* It must be called with power domains already disabled (after a call to
* intel_power_domains_disable()) and paired with intel_power_domains_resume().
*/
-void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle)
+void intel_power_domains_suspend(struct intel_display *display, bool s2idle)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
struct i915_power_domains *power_domains = &display->power.domains;
intel_wakeref_t wakeref __maybe_unused =
fetch_and_zero(&power_domains->init_wakeref);
@@ -2143,7 +2138,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle)
/**
* intel_power_domains_resume - resume power domain state
- * @i915: i915 device instance
+ * @display: display device instance
*
* This function resume the hardware power domain state during system resume.
*
@@ -2151,13 +2146,13 @@ void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle)
* intel_power_domains_enable()) and must be paired with
* intel_power_domains_suspend().
*/
-void intel_power_domains_resume(struct drm_i915_private *i915)
+void intel_power_domains_resume(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
struct i915_power_domains *power_domains = &display->power.domains;
if (power_domains->display_core_suspended) {
- intel_power_domains_init_hw(i915, true);
+ intel_power_domains_init_hw(display, true);
power_domains->display_core_suspended = false;
} else {
drm_WARN_ON(display->drm, power_domains->init_wakeref);
@@ -2258,11 +2253,11 @@ static void intel_power_domains_verify_state(struct intel_display *display)
#endif
-void intel_display_power_suspend_late(struct drm_i915_private *i915, bool s2idle)
+void intel_display_power_suspend_late(struct intel_display *display, bool s2idle)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
- intel_power_domains_suspend(i915, s2idle);
+ intel_power_domains_suspend(display, s2idle);
if (DISPLAY_VER(display) >= 11 || display->platform.geminilake ||
display->platform.broxton) {
@@ -2276,9 +2271,9 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915, bool s2idle
intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
}
-void intel_display_power_resume_early(struct drm_i915_private *i915)
+void intel_display_power_resume_early(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
if (DISPLAY_VER(display) >= 11 || display->platform.geminilake ||
display->platform.broxton) {
@@ -2292,13 +2287,11 @@ void intel_display_power_resume_early(struct drm_i915_private *i915)
if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)
intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
- intel_power_domains_resume(i915);
+ intel_power_domains_resume(display);
}
-void intel_display_power_suspend(struct drm_i915_private *i915)
+void intel_display_power_suspend(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
-
if (DISPLAY_VER(display) >= 11) {
icl_display_core_uninit(display);
bxt_enable_dc9(display);
@@ -2310,9 +2303,8 @@ void intel_display_power_suspend(struct drm_i915_private *i915)
}
}
-void intel_display_power_resume(struct drm_i915_private *i915)
+void intel_display_power_resume(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
struct i915_power_domains *power_domains = &display->power.domains;
if (DISPLAY_VER(display) >= 11) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 688f3b60b5c5..7b294eec4431 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -15,6 +15,7 @@ enum aux_ch;
enum port;
struct drm_i915_private;
struct i915_power_well;
+struct intel_display;
struct intel_encoder;
struct seq_file;
@@ -166,21 +167,21 @@ struct intel_display_power_domain_set {
for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++) \
for_each_if(test_bit((__domain), (__mask)->bits))
-int intel_power_domains_init(struct drm_i915_private *dev_priv);
-void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
-void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
-void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);
-void intel_power_domains_enable(struct drm_i915_private *dev_priv);
-void intel_power_domains_disable(struct drm_i915_private *dev_priv);
-void intel_power_domains_suspend(struct drm_i915_private *dev_priv, bool s2idle);
-void intel_power_domains_resume(struct drm_i915_private *dev_priv);
-void intel_power_domains_sanitize_state(struct drm_i915_private *dev_priv);
-
-void intel_display_power_suspend_late(struct drm_i915_private *i915, bool s2idle);
-void intel_display_power_resume_early(struct drm_i915_private *i915);
-void intel_display_power_suspend(struct drm_i915_private *i915);
-void intel_display_power_resume(struct drm_i915_private *i915);
-void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
+int intel_power_domains_init(struct intel_display *display);
+void intel_power_domains_cleanup(struct intel_display *display);
+void intel_power_domains_init_hw(struct intel_display *display, bool resume);
+void intel_power_domains_driver_remove(struct intel_display *display);
+void intel_power_domains_enable(struct intel_display *display);
+void intel_power_domains_disable(struct intel_display *display);
+void intel_power_domains_suspend(struct intel_display *display, bool s2idle);
+void intel_power_domains_resume(struct intel_display *display);
+void intel_power_domains_sanitize_state(struct intel_display *display);
+
+void intel_display_power_suspend_late(struct intel_display *display, bool s2idle);
+void intel_display_power_resume_early(struct intel_display *display);
+void intel_display_power_suspend(struct intel_display *display);
+void intel_display_power_resume(struct intel_display *display);
+void intel_display_power_set_target_dc_state(struct intel_display *display,
u32 state);
bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 2c8668b1ebae..9db30db428f7 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -1024,5 +1024,5 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
- intel_power_domains_sanitize_state(i915);
+ intel_power_domains_sanitize_state(display);
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 15b70a1127d4..64c00a8a6850 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1130,18 +1130,16 @@ static void psr2_program_idle_frames(struct intel_dp *intel_dp,
static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp)
{
struct intel_display *display = to_intel_display(intel_dp);
- struct drm_i915_private *dev_priv = to_i915(display->drm);
psr2_program_idle_frames(intel_dp, 0);
- intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO);
+ intel_display_power_set_target_dc_state(display, DC_STATE_EN_DC3CO);
}
static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp)
{
struct intel_display *display = to_intel_display(intel_dp);
- struct drm_i915_private *dev_priv = to_i915(display->drm);
- intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
+ intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp));
}
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index ff99d45bdfda..c1edf5e1f61e 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -286,8 +286,10 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
*/
static void i915_driver_late_release(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
+
intel_irq_fini(dev_priv);
- intel_power_domains_cleanup(dev_priv);
+ intel_power_domains_cleanup(display);
i915_gem_cleanup_early(dev_priv);
intel_gt_driver_late_release_all(dev_priv);
intel_region_ttm_device_fini(dev_priv);
@@ -605,6 +607,7 @@ static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
*/
static void i915_driver_register(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
struct intel_gt *gt;
unsigned int i;
@@ -635,7 +638,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
intel_display_driver_register(dev_priv);
- intel_power_domains_enable(dev_priv);
+ intel_power_domains_enable(display);
intel_runtime_pm_enable(&dev_priv->runtime_pm);
intel_register_dsm_handler();
@@ -650,6 +653,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
*/
static void i915_driver_unregister(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
struct intel_gt *gt;
unsigned int i;
@@ -658,7 +662,7 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv)
intel_unregister_dsm_handler();
intel_runtime_pm_disable(&dev_priv->runtime_pm);
- intel_power_domains_disable(dev_priv);
+ intel_power_domains_disable(display);
intel_display_driver_unregister(dev_priv);
@@ -943,9 +947,11 @@ static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
void i915_driver_shutdown(struct drm_i915_private *i915)
{
+ struct intel_display *display = &i915->display;
+
disable_rpm_wakeref_asserts(&i915->runtime_pm);
intel_runtime_pm_disable(&i915->runtime_pm);
- intel_power_domains_disable(i915);
+ intel_power_domains_disable(display);
intel_fbdev_set_suspend(&i915->drm, FBINFO_STATE_SUSPENDED, true);
if (HAS_DISPLAY(i915)) {
@@ -981,7 +987,7 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
* - unify the driver remove and system/runtime suspend sequences with
* the above unified shutdown/poweroff sequence.
*/
- intel_power_domains_driver_remove(i915);
+ intel_power_domains_driver_remove(display);
enable_rpm_wakeref_asserts(&i915->runtime_pm);
intel_runtime_pm_driver_last_release(&i915->runtime_pm);
@@ -1029,7 +1035,7 @@ static int i915_drm_suspend(struct drm_device *dev)
/* We do a lot of poking in a lot of registers, make sure they work
* properly. */
- intel_power_domains_disable(dev_priv);
+ intel_power_domains_disable(display);
intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
if (HAS_DISPLAY(dev_priv)) {
drm_kms_helper_poll_disable(dev);
@@ -1071,6 +1077,7 @@ static int i915_drm_suspend(struct drm_device *dev)
static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_display *display = &dev_priv->display;
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
struct intel_gt *gt;
@@ -1086,12 +1093,12 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
for_each_gt(gt, dev_priv, i)
intel_uncore_suspend(gt->uncore);
- intel_display_power_suspend_late(dev_priv, s2idle);
+ intel_display_power_suspend_late(display, s2idle);
ret = vlv_suspend_complete(dev_priv);
if (ret) {
drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
- intel_display_power_resume_early(dev_priv);
+ intel_display_power_resume_early(display);
goto out;
}
@@ -1217,7 +1224,7 @@ static int i915_drm_resume(struct drm_device *dev)
intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
- intel_power_domains_enable(dev_priv);
+ intel_power_domains_enable(display);
intel_gvt_resume(dev_priv);
@@ -1229,6 +1236,7 @@ static int i915_drm_resume(struct drm_device *dev)
static int i915_drm_resume_early(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_display *display = &dev_priv->display;
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
struct intel_gt *gt;
int ret, i;
@@ -1288,7 +1296,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
for_each_gt(gt, dev_priv, i)
intel_gt_resume_early(gt);
- intel_display_power_resume_early(dev_priv);
+ intel_display_power_resume_early(display);
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
@@ -1490,7 +1498,7 @@ static int intel_runtime_suspend(struct device *kdev)
for_each_gt(gt, dev_priv, i)
intel_uncore_suspend(gt->uncore);
- intel_display_power_suspend(dev_priv);
+ intel_display_power_suspend(display);
ret = vlv_suspend_complete(dev_priv);
if (ret) {
@@ -1584,7 +1592,7 @@ static int intel_runtime_resume(struct device *kdev)
drm_dbg(&dev_priv->drm,
"Unclaimed access during suspend, bios?\n");
- intel_display_power_resume(dev_priv);
+ intel_display_power_resume(display);
ret = vlv_resume_prepare(dev_priv, true);
diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index 69c828f38cb6..31c05f54b699 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -103,11 +103,12 @@ int xe_display_create(struct xe_device *xe)
static void xe_display_fini_nommio(struct drm_device *dev, void *dummy)
{
struct xe_device *xe = to_xe_device(dev);
+ struct intel_display *display = &xe->display;
if (!xe->info.probe_display)
return;
- intel_power_domains_cleanup(xe);
+ intel_power_domains_cleanup(display);
}
int xe_display_init_nommio(struct xe_device *xe)
@@ -215,21 +216,25 @@ void xe_display_fini(struct xe_device *xe)
void xe_display_register(struct xe_device *xe)
{
+ struct intel_display *display = &xe->display;
+
if (!xe->info.probe_display)
return;
intel_display_driver_register(xe);
- intel_power_domains_enable(xe);
+ intel_power_domains_enable(display);
intel_register_dsm_handler();
}
void xe_display_unregister(struct xe_device *xe)
{
+ struct intel_display *display = &xe->display;
+
if (!xe->info.probe_display)
return;
intel_unregister_dsm_handler();
- intel_power_domains_disable(xe);
+ intel_power_domains_disable(display);
intel_display_driver_unregister(xe);
}
@@ -322,7 +327,7 @@ static void __xe_display_pm_suspend(struct xe_device *xe, bool runtime)
* We do a lot of poking in a lot of registers, make sure they work
* properly.
*/
- intel_power_domains_disable(xe);
+ intel_power_domains_disable(display);
if (!runtime)
intel_fbdev_set_suspend(&xe->drm, FBINFO_STATE_SUSPENDED, true);
@@ -361,7 +366,7 @@ void xe_display_pm_shutdown(struct xe_device *xe)
if (!xe->info.probe_display)
return;
- intel_power_domains_disable(xe);
+ intel_power_domains_disable(display);
intel_fbdev_set_suspend(&xe->drm, FBINFO_STATE_SUSPENDED, true);
if (has_display(xe)) {
drm_kms_helper_poll_disable(&xe->drm);
@@ -399,16 +404,19 @@ void xe_display_pm_runtime_suspend(struct xe_device *xe)
void xe_display_pm_suspend_late(struct xe_device *xe)
{
+ struct intel_display *display = &xe->display;
bool s2idle = suspend_to_idle();
if (!xe->info.probe_display)
return;
- intel_display_power_suspend_late(xe, s2idle);
+ intel_display_power_suspend_late(display, s2idle);
}
void xe_display_pm_shutdown_late(struct xe_device *xe)
{
+ struct intel_display *display = &xe->display;
+
if (!xe->info.probe_display)
return;
@@ -417,15 +425,17 @@ void xe_display_pm_shutdown_late(struct xe_device *xe)
* for now leaving all display power wells in the INIT power domain
* enabled.
*/
- intel_power_domains_driver_remove(xe);
+ intel_power_domains_driver_remove(display);
}
void xe_display_pm_resume_early(struct xe_device *xe)
{
+ struct intel_display *display = &xe->display;
+
if (!xe->info.probe_display)
return;
- intel_display_power_resume_early(xe);
+ intel_display_power_resume_early(display);
}
static void __xe_display_pm_resume(struct xe_device *xe, bool runtime)
@@ -461,7 +471,7 @@ static void __xe_display_pm_resume(struct xe_device *xe, bool runtime)
if (!runtime)
intel_fbdev_set_suspend(&xe->drm, FBINFO_STATE_RUNNING, false);
- intel_power_domains_enable(xe);
+ intel_power_domains_enable(display);
}
void xe_display_pm_resume(struct xe_device *xe)
--
2.39.5
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 6/6] drm/i915/display: convert power map to struct intel_display
2024-11-28 15:38 [PATCH v2 0/6] drm/i915/display: power conversion to struct intel_display Jani Nikula
` (4 preceding siblings ...)
2024-11-28 15:38 ` [PATCH v2 5/6] drm/i915/display: convert high level power interfaces " Jani Nikula
@ 2024-11-28 15:38 ` Jani Nikula
2024-11-28 18:13 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: power conversion to struct intel_display (rev2) Patchwork
` (5 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Jani Nikula @ 2024-11-28 15:38 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: imre.deak, jani.nikula
Going forward, struct intel_display is the main device data structure
for display. Convert the power map code to it.
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../i915/display/intel_display_power_map.c | 56 +++++++++----------
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 5575aa0d6689..fb2df5c382d8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1752,9 +1752,9 @@ __set_power_wells(struct i915_power_domains *power_domains,
const struct i915_power_well_desc_list *power_well_descs,
int power_well_descs_sz)
{
- struct drm_i915_private *i915 = container_of(power_domains,
- struct drm_i915_private,
- display.power.domains);
+ struct intel_display *display = container_of(power_domains,
+ struct intel_display,
+ power.domains);
u64 power_well_ids = 0;
const struct i915_power_well_desc_list *desc_list;
const struct i915_power_well_desc *desc;
@@ -1778,7 +1778,7 @@ __set_power_wells(struct i915_power_domains *power_domains,
enum i915_power_well_id id = inst->id;
pw->desc = desc;
- drm_WARN_ON(&i915->drm,
+ drm_WARN_ON(display->drm,
overflows_type(inst - desc->instances->list, pw->instance_idx));
pw->instance_idx = inst - desc->instances->list;
@@ -1789,8 +1789,8 @@ __set_power_wells(struct i915_power_domains *power_domains,
if (id == DISP_PW_ID_NONE)
continue;
- drm_WARN_ON(&i915->drm, id >= sizeof(power_well_ids) * 8);
- drm_WARN_ON(&i915->drm, power_well_ids & BIT_ULL(id));
+ drm_WARN_ON(display->drm, id >= sizeof(power_well_ids) * 8);
+ drm_WARN_ON(display->drm, power_well_ids & BIT_ULL(id));
power_well_ids |= BIT_ULL(id);
}
@@ -1811,53 +1811,53 @@ __set_power_wells(struct i915_power_domains *power_domains,
*/
int intel_display_power_map_init(struct i915_power_domains *power_domains)
{
- struct drm_i915_private *i915 = container_of(power_domains,
- struct drm_i915_private,
- display.power.domains);
+ struct intel_display *display = container_of(power_domains,
+ struct intel_display,
+ power.domains);
/*
* The enabling order will be from lower to higher indexed wells,
* the disabling order is reversed.
*/
- if (!HAS_DISPLAY(i915)) {
+ if (!HAS_DISPLAY(display)) {
power_domains->power_well_count = 0;
return 0;
}
- if (DISPLAY_VER(i915) >= 30)
+ if (DISPLAY_VER(display) >= 30)
return set_power_wells(power_domains, xe3lpd_power_wells);
- else if (DISPLAY_VER(i915) >= 20)
+ else if (DISPLAY_VER(display) >= 20)
return set_power_wells(power_domains, xe2lpd_power_wells);
- else if (DISPLAY_VER(i915) >= 14)
+ else if (DISPLAY_VER(display) >= 14)
return set_power_wells(power_domains, xelpdp_power_wells);
- else if (IS_DG2(i915))
+ else if (display->platform.dg2)
return set_power_wells(power_domains, xehpd_power_wells);
- else if (DISPLAY_VER(i915) >= 13)
+ else if (DISPLAY_VER(display) >= 13)
return set_power_wells(power_domains, xelpd_power_wells);
- else if (IS_DG1(i915))
+ else if (display->platform.dg1)
return set_power_wells(power_domains, dg1_power_wells);
- else if (IS_ALDERLAKE_S(i915))
+ else if (display->platform.alderlake_s)
return set_power_wells(power_domains, adls_power_wells);
- else if (IS_ROCKETLAKE(i915))
+ else if (display->platform.rocketlake)
return set_power_wells(power_domains, rkl_power_wells);
- else if (DISPLAY_VER(i915) == 12)
+ else if (DISPLAY_VER(display) == 12)
return set_power_wells(power_domains, tgl_power_wells);
- else if (DISPLAY_VER(i915) == 11)
+ else if (DISPLAY_VER(display) == 11)
return set_power_wells(power_domains, icl_power_wells);
- else if (IS_GEMINILAKE(i915))
+ else if (display->platform.geminilake)
return set_power_wells(power_domains, glk_power_wells);
- else if (IS_BROXTON(i915))
+ else if (display->platform.broxton)
return set_power_wells(power_domains, bxt_power_wells);
- else if (DISPLAY_VER(i915) == 9)
+ else if (DISPLAY_VER(display) == 9)
return set_power_wells(power_domains, skl_power_wells);
- else if (IS_CHERRYVIEW(i915))
+ else if (display->platform.cherryview)
return set_power_wells(power_domains, chv_power_wells);
- else if (IS_BROADWELL(i915))
+ else if (display->platform.broadwell)
return set_power_wells(power_domains, bdw_power_wells);
- else if (IS_HASWELL(i915))
+ else if (display->platform.haswell)
return set_power_wells(power_domains, hsw_power_wells);
- else if (IS_VALLEYVIEW(i915))
+ else if (display->platform.valleyview)
return set_power_wells(power_domains, vlv_power_wells);
- else if (IS_I830(i915))
+ else if (display->platform.i830)
return set_power_wells(power_domains, i830_power_wells);
else
return set_power_wells(power_domains, i9xx_power_wells);
--
2.39.5
^ permalink raw reply related [flat|nested] 17+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: power conversion to struct intel_display (rev2)
2024-11-28 15:38 [PATCH v2 0/6] drm/i915/display: power conversion to struct intel_display Jani Nikula
` (5 preceding siblings ...)
2024-11-28 15:38 ` [PATCH v2 6/6] drm/i915/display: convert power map " Jani Nikula
@ 2024-11-28 18:13 ` Patchwork
2024-11-28 18:13 ` ✗ Fi.CI.SPARSE: " Patchwork
` (4 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2024-11-28 18:13 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/display: power conversion to struct intel_display (rev2)
URL : https://patchwork.freedesktop.org/series/141846/
State : warning
== Summary ==
Error: dim checkpatch failed
cd780c372c31 drm/i915/display: convert for_each_power_well() to struct intel_display
-:118: CHECK:MACRO_ARG_REUSE: Macro argument reuse '___display' - possible side-effects?
#118: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.h:18:
+#define for_each_power_well(___display, __power_well) \
+ for ((__power_well) = (___display)->power.domains.power_wells; \
+ (__power_well) - (___display)->power.domains.power_wells < \
+ (___display)->power.domains.power_well_count; \
(__power_well)++)
-:118: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well' - possible side-effects?
#118: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.h:18:
+#define for_each_power_well(___display, __power_well) \
+ for ((__power_well) = (___display)->power.domains.power_wells; \
+ (__power_well) - (___display)->power.domains.power_wells < \
+ (___display)->power.domains.power_well_count; \
(__power_well)++)
-:128: CHECK:MACRO_ARG_REUSE: Macro argument reuse '___display' - possible side-effects?
#128: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.h:24:
+#define for_each_power_well_reverse(___display, __power_well) \
+ for ((__power_well) = (___display)->power.domains.power_wells + \
+ (___display)->power.domains.power_well_count - 1; \
+ (__power_well) - (___display)->power.domains.power_wells >= 0; \
(__power_well)--)
-:128: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well' - possible side-effects?
#128: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.h:24:
+#define for_each_power_well_reverse(___display, __power_well) \
+ for ((__power_well) = (___display)->power.domains.power_wells + \
+ (___display)->power.domains.power_well_count - 1; \
+ (__power_well) - (___display)->power.domains.power_wells >= 0; \
(__power_well)--)
total: 0 errors, 0 warnings, 4 checks, 102 lines checked
45b65941930b drm/i915/display: convert for_each_power_domain_well() to struct intel_display
-:24: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#24: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:31:
+#define for_each_power_domain_well(__display, __power_well, __domain) \
+ for_each_power_well((__display), __power_well) \
for_each_if(test_bit((__domain), (__power_well)->domains.bits))
-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:31:
+#define for_each_power_domain_well(__display, __power_well, __domain) \
+ for_each_power_well((__display), __power_well) \
for_each_if(test_bit((__domain), (__power_well)->domains.bits))
-:30: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#30: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:35:
+#define for_each_power_domain_well_reverse(__display, __power_well, __domain) \
+ for_each_power_well_reverse((__display), __power_well) \
for_each_if(test_bit((__domain), (__power_well)->domains.bits))
-:30: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well' - possible side-effects?
#30: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:35:
+#define for_each_power_domain_well_reverse(__display, __power_well, __domain) \
+ for_each_power_well_reverse((__display), __power_well) \
for_each_if(test_bit((__domain), (__power_well)->domains.bits))
total: 2 errors, 0 warnings, 2 checks, 61 lines checked
d78a69328472 drm/i915/display: convert power wells to struct intel_display
520ef50d09b0 drm/i915/display: convert power domain code internally to struct intel_display
-:141: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#141: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:382:
+ drm_dbg_kms(display->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM));
-:1662: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#1662: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:2182:
+ intel_power_well_name(power_well), intel_power_well_refcount(power_well));
-:1907: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#1907: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:2563:
+ const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch);
-:1920: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#1920: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:2575:
+ const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch);
-:1933: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#1933: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:2587:
+ const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch);
total: 0 errors, 5 warnings, 0 checks, 1832 lines checked
ee3522a32636 drm/i915/display: convert high level power interfaces to struct intel_display
e90f1ec218e5 drm/i915/display: convert power map to struct intel_display
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915/display: power conversion to struct intel_display (rev2)
2024-11-28 15:38 [PATCH v2 0/6] drm/i915/display: power conversion to struct intel_display Jani Nikula
` (6 preceding siblings ...)
2024-11-28 18:13 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: power conversion to struct intel_display (rev2) Patchwork
@ 2024-11-28 18:13 ` Patchwork
2024-11-28 18:22 ` ✗ i915.CI.BAT: failure " Patchwork
` (3 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2024-11-28 18:13 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/display: power conversion to struct intel_display (rev2)
URL : https://patchwork.freedesktop.org/series/141846/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✗ i915.CI.BAT: failure for drm/i915/display: power conversion to struct intel_display (rev2)
2024-11-28 15:38 [PATCH v2 0/6] drm/i915/display: power conversion to struct intel_display Jani Nikula
` (7 preceding siblings ...)
2024-11-28 18:13 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2024-11-28 18:22 ` Patchwork
2024-11-29 8:19 ` Jani Nikula
2024-11-29 14:00 ` ✓ i915.CI.BAT: success " Patchwork
` (2 subsequent siblings)
11 siblings, 1 reply; 17+ messages in thread
From: Patchwork @ 2024-11-28 18:22 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/display: power conversion to struct intel_display (rev2)
URL : https://patchwork.freedesktop.org/series/141846/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15759 -> Patchwork_141846v2
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_141846v2 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_141846v2, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/index.html
Participating hosts (45 -> 44)
------------------------------
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_141846v2:
### IGT changes ###
#### Possible regressions ####
* igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-dp-1:
- fi-cfl-8109u: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/fi-cfl-8109u/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-dp-1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/fi-cfl-8109u/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-dp-1.html
Known issues
------------
Here are the changes found in Patchwork_141846v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@workarounds:
- bat-arlh-3: [PASS][3] -> [ABORT][4] ([i915#12061]) +1 other test abort
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/bat-arlh-3/igt@i915_selftest@live@workarounds.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/bat-arlh-3/igt@i915_selftest@live@workarounds.html
- bat-mtlp-6: [PASS][5] -> [ABORT][6] ([i915#12061]) +1 other test abort
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
* igt@kms_flip@basic-flip-vs-modeset@b-dp1:
- bat-apl-1: [PASS][7] -> [DMESG-WARN][8] ([i915#12918]) +1 other test dmesg-warn
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/bat-apl-1/igt@kms_flip@basic-flip-vs-modeset@b-dp1.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/bat-apl-1/igt@kms_flip@basic-flip-vs-modeset@b-dp1.html
* igt@kms_pipe_crc_basic@hang-read-crc:
- fi-cfl-8109u: [PASS][9] -> [DMESG-WARN][10] ([i915#12914]) +1 other test dmesg-warn
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/fi-cfl-8109u/igt@kms_pipe_crc_basic@hang-read-crc.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/fi-cfl-8109u/igt@kms_pipe_crc_basic@hang-read-crc.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_pm:
- bat-twl-2: [ABORT][11] ([i915#12919]) -> [PASS][12] +1 other test pass
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/bat-twl-2/igt@i915_selftest@live@gt_pm.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/bat-twl-2/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@workarounds:
- {bat-arls-6}: [ABORT][13] ([i915#12061]) -> [PASS][14] +1 other test pass
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/bat-arls-6/igt@i915_selftest@live@workarounds.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/bat-arls-6/igt@i915_selftest@live@workarounds.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12914]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12914
[i915#12918]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12918
[i915#12919]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12919
Build changes
-------------
* Linux: CI_DRM_15759 -> Patchwork_141846v2
CI-20190529: 20190529
CI_DRM_15759: 5379d0a88558b73308ad82f163e80b863626e90b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8129: 363499a879fee5b9b7eda8acf7c772bce3423493 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_141846v2: 5379d0a88558b73308ad82f163e80b863626e90b @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/index.html
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: ✗ i915.CI.BAT: failure for drm/i915/display: power conversion to struct intel_display (rev2)
2024-11-28 18:22 ` ✗ i915.CI.BAT: failure " Patchwork
@ 2024-11-29 8:19 ` Jani Nikula
2024-11-29 16:08 ` Illipilli, TejasreeX
0 siblings, 1 reply; 17+ messages in thread
From: Jani Nikula @ 2024-11-29 8:19 UTC (permalink / raw)
To: I915-ci-infra; +Cc: intel-gfx
On Thu, 28 Nov 2024, Patchwork <patchwork@emeril.freedesktop.org> wrote:
> == Series Details ==
>
> Series: drm/i915/display: power conversion to struct intel_display (rev2)
> URL : https://patchwork.freedesktop.org/series/141846/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_15759 -> Patchwork_141846v2
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_141846v2 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_141846v2, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/index.html
>
> Participating hosts (45 -> 44)
> ------------------------------
>
> Missing (1): fi-snb-2520m
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_141846v2:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-dp-1:
> - fi-cfl-8109u: [PASS][1] -> [DMESG-WARN][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/fi-cfl-8109u/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-dp-1.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/fi-cfl-8109u/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-dp-1.html
Unrelated, please re-report.
BR,
Jani.
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_141846v2 that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@i915_selftest@live@workarounds:
> - bat-arlh-3: [PASS][3] -> [ABORT][4] ([i915#12061]) +1 other test abort
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/bat-arlh-3/igt@i915_selftest@live@workarounds.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/bat-arlh-3/igt@i915_selftest@live@workarounds.html
> - bat-mtlp-6: [PASS][5] -> [ABORT][6] ([i915#12061]) +1 other test abort
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
>
> * igt@kms_flip@basic-flip-vs-modeset@b-dp1:
> - bat-apl-1: [PASS][7] -> [DMESG-WARN][8] ([i915#12918]) +1 other test dmesg-warn
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/bat-apl-1/igt@kms_flip@basic-flip-vs-modeset@b-dp1.html
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/bat-apl-1/igt@kms_flip@basic-flip-vs-modeset@b-dp1.html
>
> * igt@kms_pipe_crc_basic@hang-read-crc:
> - fi-cfl-8109u: [PASS][9] -> [DMESG-WARN][10] ([i915#12914]) +1 other test dmesg-warn
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/fi-cfl-8109u/igt@kms_pipe_crc_basic@hang-read-crc.html
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/fi-cfl-8109u/igt@kms_pipe_crc_basic@hang-read-crc.html
>
>
> #### Possible fixes ####
>
> * igt@i915_selftest@live@gt_pm:
> - bat-twl-2: [ABORT][11] ([i915#12919]) -> [PASS][12] +1 other test pass
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/bat-twl-2/igt@i915_selftest@live@gt_pm.html
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/bat-twl-2/igt@i915_selftest@live@gt_pm.html
>
> * igt@i915_selftest@live@workarounds:
> - {bat-arls-6}: [ABORT][13] ([i915#12061]) -> [PASS][14] +1 other test pass
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/bat-arls-6/igt@i915_selftest@live@workarounds.html
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/bat-arls-6/igt@i915_selftest@live@workarounds.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
> [i915#12914]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12914
> [i915#12918]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12918
> [i915#12919]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12919
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_15759 -> Patchwork_141846v2
>
> CI-20190529: 20190529
> CI_DRM_15759: 5379d0a88558b73308ad82f163e80b863626e90b @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_8129: 363499a879fee5b9b7eda8acf7c772bce3423493 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_141846v2: 5379d0a88558b73308ad82f163e80b863626e90b @ git://anongit.freedesktop.org/gfx-ci/linux
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/index.html
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✓ i915.CI.BAT: success for drm/i915/display: power conversion to struct intel_display (rev2)
2024-11-28 15:38 [PATCH v2 0/6] drm/i915/display: power conversion to struct intel_display Jani Nikula
` (8 preceding siblings ...)
2024-11-28 18:22 ` ✗ i915.CI.BAT: failure " Patchwork
@ 2024-11-29 14:00 ` Patchwork
2024-11-29 14:18 ` [PATCH v2 0/6] drm/i915/display: power conversion to struct intel_display Imre Deak
2024-11-29 19:12 ` ✗ i915.CI.Full: failure for drm/i915/display: power conversion to struct intel_display (rev2) Patchwork
11 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2024-11-29 14:00 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/display: power conversion to struct intel_display (rev2)
URL : https://patchwork.freedesktop.org/series/141846/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15759 -> Patchwork_141846v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/index.html
Participating hosts (45 -> 44)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_141846v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@workarounds:
- bat-arlh-3: [PASS][1] -> [ABORT][2] ([i915#12061]) +1 other test abort
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/bat-arlh-3/igt@i915_selftest@live@workarounds.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/bat-arlh-3/igt@i915_selftest@live@workarounds.html
- bat-mtlp-6: [PASS][3] -> [ABORT][4] ([i915#12061]) +1 other test abort
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
* igt@kms_flip@basic-flip-vs-modeset@b-dp1:
- bat-apl-1: [PASS][5] -> [DMESG-WARN][6] ([i915#12918]) +1 other test dmesg-warn
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/bat-apl-1/igt@kms_flip@basic-flip-vs-modeset@b-dp1.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/bat-apl-1/igt@kms_flip@basic-flip-vs-modeset@b-dp1.html
* igt@kms_pipe_crc_basic@hang-read-crc:
- fi-cfl-8109u: [PASS][7] -> [DMESG-WARN][8] ([i915#12914]) +2 other tests dmesg-warn
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/fi-cfl-8109u/igt@kms_pipe_crc_basic@hang-read-crc.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/fi-cfl-8109u/igt@kms_pipe_crc_basic@hang-read-crc.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_pm:
- bat-twl-2: [ABORT][9] ([i915#12919]) -> [PASS][10] +1 other test pass
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/bat-twl-2/igt@i915_selftest@live@gt_pm.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/bat-twl-2/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@workarounds:
- {bat-arls-6}: [ABORT][11] ([i915#12061]) -> [PASS][12] +1 other test pass
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/bat-arls-6/igt@i915_selftest@live@workarounds.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/bat-arls-6/igt@i915_selftest@live@workarounds.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12914]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12914
[i915#12918]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12918
[i915#12919]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12919
Build changes
-------------
* Linux: CI_DRM_15759 -> Patchwork_141846v2
CI-20190529: 20190529
CI_DRM_15759: 5379d0a88558b73308ad82f163e80b863626e90b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8129: 363499a879fee5b9b7eda8acf7c772bce3423493 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_141846v2: 5379d0a88558b73308ad82f163e80b863626e90b @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/index.html
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 4/6] drm/i915/display: convert power domain code internally to struct intel_display
2024-11-28 15:38 ` [PATCH v2 4/6] drm/i915/display: convert power domain code internally " Jani Nikula
@ 2024-11-29 14:17 ` Imre Deak
2024-11-29 14:46 ` Jani Nikula
0 siblings, 1 reply; 17+ messages in thread
From: Imre Deak @ 2024-11-29 14:17 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Thu, Nov 28, 2024 at 05:38:22PM +0200, Jani Nikula wrote:
> Going forward, struct intel_display is the main device data structure
> for display. Convert intel_display_power.c internally first, leaving
> external interfaces for follow-up.
>
> v2: Rebase, checkpatch fixes
>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 806 +++++++++---------
> 1 file changed, 414 insertions(+), 392 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index ade7192c0461..4043d6971c3e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>
> [...]
>
> -static void hsw_disable_pc8(struct drm_i915_private *dev_priv)
> +static void hsw_disable_pc8(struct intel_display *display)
> {
> - drm_dbg_kms(&dev_priv->drm, "Disabling package C8+\n");
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> +
> + drm_dbg_kms(display->drm, "Disabling package C8+\n");
>
> - hsw_restore_lcpll(dev_priv);
> + hsw_restore_lcpll(display);
> intel_init_pch_refclk(dev_priv);
>
> /* Many display registers don't survive PC8+ */
> +#ifdef I915 /* FIXME */
> intel_clock_gating_init(dev_priv);
> +#endif
So before the call of hsw_disable_pc8() was optimized out, but now it's
not. For now ok, but imo this could've been in a separate patch.
> }
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 0/6] drm/i915/display: power conversion to struct intel_display
2024-11-28 15:38 [PATCH v2 0/6] drm/i915/display: power conversion to struct intel_display Jani Nikula
` (9 preceding siblings ...)
2024-11-29 14:00 ` ✓ i915.CI.BAT: success " Patchwork
@ 2024-11-29 14:18 ` Imre Deak
2024-11-29 19:12 ` ✗ i915.CI.Full: failure for drm/i915/display: power conversion to struct intel_display (rev2) Patchwork
11 siblings, 0 replies; 17+ messages in thread
From: Imre Deak @ 2024-11-29 14:18 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Thu, Nov 28, 2024 at 05:38:18PM +0200, Jani Nikula wrote:
> This is v2 of [1] with patch 1 dropped, and some minor checkpatch issues
> fixed.
>
> [1] https://lore.kernel.org/r/cover.1732727056.git.jani.nikula@intel.com
The patchset looks ok:
Reviewed-by: Imre Deak <imre.deak@intel.com>
>
> Jani Nikula (6):
> drm/i915/display: convert for_each_power_well() to struct
> intel_display
> drm/i915/display: convert for_each_power_domain_well() to struct
> intel_display
> drm/i915/display: convert power wells to struct intel_display
> drm/i915/display: convert power domain code internally to struct
> intel_display
> drm/i915/display: convert high level power interfaces to struct
> intel_display
> drm/i915/display: convert power map to struct intel_display
>
> .../drm/i915/display/intel_display_debugfs.c | 3 +-
> .../drm/i915/display/intel_display_driver.c | 8 +-
> .../gpu/drm/i915/display/intel_display_irq.c | 3 +-
> .../drm/i915/display/intel_display_power.c | 948 +++++++++---------
> .../drm/i915/display/intel_display_power.h | 31 +-
> .../i915/display/intel_display_power_map.c | 56 +-
> .../i915/display/intel_display_power_well.c | 548 +++++-----
> .../i915/display/intel_display_power_well.h | 35 +-
> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 7 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> .../drm/i915/display/intel_modeset_setup.c | 2 +-
> drivers/gpu/drm/i915/display/intel_pps.c | 4 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 6 +-
> drivers/gpu/drm/i915/i915_driver.c | 32 +-
> drivers/gpu/drm/xe/display/xe_display.c | 28 +-
> 15 files changed, 870 insertions(+), 843 deletions(-)
>
> --
> 2.39.5
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 4/6] drm/i915/display: convert power domain code internally to struct intel_display
2024-11-29 14:17 ` Imre Deak
@ 2024-11-29 14:46 ` Jani Nikula
0 siblings, 0 replies; 17+ messages in thread
From: Jani Nikula @ 2024-11-29 14:46 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx, intel-xe
On Fri, 29 Nov 2024, Imre Deak <imre.deak@intel.com> wrote:
> On Thu, Nov 28, 2024 at 05:38:22PM +0200, Jani Nikula wrote:
>> Going forward, struct intel_display is the main device data structure
>> for display. Convert intel_display_power.c internally first, leaving
>> external interfaces for follow-up.
>>
>> v2: Rebase, checkpatch fixes
>>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> .../drm/i915/display/intel_display_power.c | 806 +++++++++---------
>> 1 file changed, 414 insertions(+), 392 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index ade7192c0461..4043d6971c3e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>>
>> [...]
>>
>> -static void hsw_disable_pc8(struct drm_i915_private *dev_priv)
>> +static void hsw_disable_pc8(struct intel_display *display)
>> {
>> - drm_dbg_kms(&dev_priv->drm, "Disabling package C8+\n");
>> + struct drm_i915_private *dev_priv = to_i915(display->drm);
>> +
>> + drm_dbg_kms(display->drm, "Disabling package C8+\n");
>>
>> - hsw_restore_lcpll(dev_priv);
>> + hsw_restore_lcpll(display);
>> intel_init_pch_refclk(dev_priv);
>>
>> /* Many display registers don't survive PC8+ */
>> +#ifdef I915 /* FIXME */
>> intel_clock_gating_init(dev_priv);
>> +#endif
>
> So before the call of hsw_disable_pc8() was optimized out, but now it's
> not. For now ok, but imo this could've been in a separate patch.
Yeah, stuck it in to fix the build, but forgot about it.
>
>> }
>>
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: ✗ i915.CI.BAT: failure for drm/i915/display: power conversion to struct intel_display (rev2)
2024-11-29 8:19 ` Jani Nikula
@ 2024-11-29 16:08 ` Illipilli, TejasreeX
0 siblings, 0 replies; 17+ messages in thread
From: Illipilli, TejasreeX @ 2024-11-29 16:08 UTC (permalink / raw)
To: i915-ci-infra@lists.freedesktop.org; +Cc: intel-gfx@lists.freedesktop.org
Hi,
https://patchwork.freedesktop.org/series/141846/ - Re-reported.
Thanks,
Tejasree
-----Original Message-----
From: I915-ci-infra <i915-ci-infra-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
Sent: Friday, November 29, 2024 1:50 PM
To: I915-ci-infra@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: ✗ i915.CI.BAT: failure for drm/i915/display: power conversion to struct intel_display (rev2)
On Thu, 28 Nov 2024, Patchwork <patchwork@emeril.freedesktop.org> wrote:
> == Series Details ==
>
> Series: drm/i915/display: power conversion to struct intel_display (rev2)
> URL : https://patchwork.freedesktop.org/series/141846/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_15759 -> Patchwork_141846v2
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_141846v2 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_141846v2, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/index.html
>
> Participating hosts (45 -> 44)
> ------------------------------
>
> Missing (1): fi-snb-2520m
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_141846v2:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-dp-1:
> - fi-cfl-8109u: [PASS][1] -> [DMESG-WARN][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/fi-cfl-8109u/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-dp-1.html
> [2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/fi-cfl-810
> 9u/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-dp-1.html
Unrelated, please re-report.
BR,
Jani.
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_141846v2 that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@i915_selftest@live@workarounds:
> - bat-arlh-3: [PASS][3] -> [ABORT][4] ([i915#12061]) +1 other test abort
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/bat-arlh-3/igt@i915_selftest@live@workarounds.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/bat-arlh-3/igt@i915_selftest@live@workarounds.html
> - bat-mtlp-6: [PASS][5] -> [ABORT][6] ([i915#12061]) +1 other test abort
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
> [6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/bat-mtlp-6
> /igt@i915_selftest@live@workarounds.html
>
> * igt@kms_flip@basic-flip-vs-modeset@b-dp1:
> - bat-apl-1: [PASS][7] -> [DMESG-WARN][8] ([i915#12918]) +1 other test dmesg-warn
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/bat-apl-1/igt@kms_flip@basic-flip-vs-modeset@b-dp1.html
> [8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/bat-apl-1/
> igt@kms_flip@basic-flip-vs-modeset@b-dp1.html
>
> * igt@kms_pipe_crc_basic@hang-read-crc:
> - fi-cfl-8109u: [PASS][9] -> [DMESG-WARN][10] ([i915#12914]) +1 other test dmesg-warn
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/fi-cfl-8109u/igt@kms_pipe_crc_basic@hang-read-crc.html
> [10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/fi-cfl-810
> 9u/igt@kms_pipe_crc_basic@hang-read-crc.html
>
>
> #### Possible fixes ####
>
> * igt@i915_selftest@live@gt_pm:
> - bat-twl-2: [ABORT][11] ([i915#12919]) -> [PASS][12] +1 other test pass
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/bat-twl-2/igt@i915_selftest@live@gt_pm.html
> [12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/bat-twl-2/
> igt@i915_selftest@live@gt_pm.html
>
> * igt@i915_selftest@live@workarounds:
> - {bat-arls-6}: [ABORT][13] ([i915#12061]) -> [PASS][14] +1 other test pass
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/bat-arls-6/igt@i915_selftest@live@workarounds.html
> [14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/bat-arls-6
> /igt@i915_selftest@live@workarounds.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
> [i915#12914]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12914
> [i915#12918]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12918
> [i915#12919]:
> https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12919
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_15759 -> Patchwork_141846v2
>
> CI-20190529: 20190529
> CI_DRM_15759: 5379d0a88558b73308ad82f163e80b863626e90b @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_8129: 363499a879fee5b9b7eda8acf7c772bce3423493 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_141846v2: 5379d0a88558b73308ad82f163e80b863626e90b @
> git://anongit.freedesktop.org/gfx-ci/linux
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/index.html
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✗ i915.CI.Full: failure for drm/i915/display: power conversion to struct intel_display (rev2)
2024-11-28 15:38 [PATCH v2 0/6] drm/i915/display: power conversion to struct intel_display Jani Nikula
` (10 preceding siblings ...)
2024-11-29 14:18 ` [PATCH v2 0/6] drm/i915/display: power conversion to struct intel_display Imre Deak
@ 2024-11-29 19:12 ` Patchwork
11 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2024-11-29 19:12 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 88153 bytes --]
== Series Details ==
Series: drm/i915/display: power conversion to struct intel_display (rev2)
URL : https://patchwork.freedesktop.org/series/141846/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15759_full -> Patchwork_141846v2_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_141846v2_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_141846v2_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_141846v2_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_ctx_isolation@preservation-s3:
- shard-dg2: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-dg2-3/igt@gem_ctx_isolation@preservation-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-6/igt@gem_ctx_isolation@preservation-s3.html
* igt@gem_tiled_swapping@non-threaded:
- shard-snb: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-snb2/igt@gem_tiled_swapping@non-threaded.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-snb1/igt@gem_tiled_swapping@non-threaded.html
- shard-tglu: [PASS][5] -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-tglu-4/igt@gem_tiled_swapping@non-threaded.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-8/igt@gem_tiled_swapping@non-threaded.html
Known issues
------------
Here are the changes found in Patchwork_141846v2_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-dg1: NOTRUN -> [SKIP][7] ([i915#8411]) +1 other test skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-17/igt@api_intel_bb@blit-reloc-purge-cache.html
* igt@device_reset@unbind-reset-rebind:
- shard-dg1: NOTRUN -> [ABORT][8] ([i915#11814] / [i915#11815])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-17/igt@device_reset@unbind-reset-rebind.html
* igt@drm_fdinfo@busy-check-all@bcs0:
- shard-dg1: NOTRUN -> [SKIP][9] ([i915#8414]) +13 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-14/igt@drm_fdinfo@busy-check-all@bcs0.html
* igt@drm_fdinfo@most-busy-check-all@bcs0:
- shard-dg2: NOTRUN -> [SKIP][10] ([i915#8414]) +31 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-1/igt@drm_fdinfo@most-busy-check-all@bcs0.html
* igt@gem_basic@multigpu-create-close:
- shard-tglu-1: NOTRUN -> [SKIP][11] ([i915#7697]) +1 other test skip
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@gem_basic@multigpu-create-close.html
* igt@gem_ccs@block-multicopy-inplace:
- shard-dg1: NOTRUN -> [SKIP][12] ([i915#3555] / [i915#9323])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@gem_ccs@block-multicopy-inplace.html
* igt@gem_ccs@suspend-resume:
- shard-dg1: NOTRUN -> [SKIP][13] ([i915#9323])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@gem_ccs@suspend-resume.html
* igt@gem_close_race@multigpu-basic-process:
- shard-dg2: NOTRUN -> [SKIP][14] ([i915#7697])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@gem_close_race@multigpu-basic-process.html
- shard-dg1: NOTRUN -> [SKIP][15] ([i915#7697])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-14/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_create@busy-create:
- shard-rkl: [PASS][16] -> [DMESG-WARN][17] ([i915#12964]) +5 other tests dmesg-warn
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-rkl-2/igt@gem_create@busy-create.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-rkl-2/igt@gem_create@busy-create.html
* igt@gem_create@create-ext-set-pat:
- shard-dg2: NOTRUN -> [SKIP][18] ([i915#8562])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-8/igt@gem_create@create-ext-set-pat.html
- shard-dg1: NOTRUN -> [SKIP][19] ([i915#8562])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_freq@sysfs:
- shard-dg2: [PASS][20] -> [FAIL][21] ([i915#9561]) +1 other test fail
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-dg2-3/igt@gem_ctx_freq@sysfs.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-6/igt@gem_ctx_freq@sysfs.html
* igt@gem_ctx_persistence@heartbeat-hostile:
- shard-dg2: NOTRUN -> [SKIP][22] ([i915#8555]) +1 other test skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@gem_ctx_persistence@heartbeat-hostile.html
- shard-dg1: NOTRUN -> [SKIP][23] ([i915#8555]) +2 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-14/igt@gem_ctx_persistence@heartbeat-hostile.html
* igt@gem_ctx_sseu@mmap-args:
- shard-dg2: NOTRUN -> [SKIP][24] ([i915#280])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_eio@unwedge-stress:
- shard-snb: NOTRUN -> [FAIL][25] ([i915#8898])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-snb5/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-tglu-1: NOTRUN -> [FAIL][26] ([i915#6117])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_balancer@sliced:
- shard-dg2: NOTRUN -> [SKIP][27] ([i915#4812]) +1 other test skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@gem_exec_balancer@sliced.html
* igt@gem_exec_fence@submit:
- shard-dg1: NOTRUN -> [SKIP][28] ([i915#4812]) +2 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@gem_exec_fence@submit.html
* igt@gem_exec_flush@basic-uc-ro-default:
- shard-dg2: NOTRUN -> [SKIP][29] ([i915#3539] / [i915#4852]) +2 other tests skip
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@gem_exec_flush@basic-uc-ro-default.html
* igt@gem_exec_flush@basic-uc-set-default:
- shard-dg2: NOTRUN -> [SKIP][30] ([i915#3539])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-1/igt@gem_exec_flush@basic-uc-set-default.html
* igt@gem_exec_flush@basic-wb-prw-default:
- shard-dg1: NOTRUN -> [SKIP][31] ([i915#3539] / [i915#4852])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@gem_exec_flush@basic-wb-prw-default.html
* igt@gem_exec_reloc@basic-wc:
- shard-dg2: NOTRUN -> [SKIP][32] ([i915#3281]) +6 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-1/igt@gem_exec_reloc@basic-wc.html
* igt@gem_exec_reloc@basic-wc-gtt-noreloc:
- shard-dg1: NOTRUN -> [SKIP][33] ([i915#3281]) +17 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-17/igt@gem_exec_reloc@basic-wc-gtt-noreloc.html
* igt@gem_fence_thrash@bo-write-verify-y:
- shard-dg1: NOTRUN -> [SKIP][34] ([i915#4860]) +1 other test skip
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@gem_fence_thrash@bo-write-verify-y.html
* igt@gem_fenced_exec_thrash@2-spare-fences:
- shard-dg2: NOTRUN -> [SKIP][35] ([i915#4860]) +2 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@gem_fenced_exec_thrash@2-spare-fences.html
* igt@gem_lmem_swapping@heavy-verify-random-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][36] ([i915#4613]) +1 other test skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@gem_lmem_swapping@heavy-verify-random-ccs.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg1: [PASS][37] -> [TIMEOUT][38] ([i915#5493]) +1 other test timeout
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-tglu: NOTRUN -> [SKIP][39] ([i915#4613]) +2 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-2/igt@gem_lmem_swapping@verify-ccs.html
- shard-dg1: NOTRUN -> [SKIP][40] ([i915#12193])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@gem_lmem_swapping@verify-ccs.html
* igt@gem_lmem_swapping@verify-ccs@lmem0:
- shard-dg1: NOTRUN -> [SKIP][41] ([i915#4565])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@gem_lmem_swapping@verify-ccs@lmem0.html
* igt@gem_mmap_gtt@basic-small-bo:
- shard-dg2: NOTRUN -> [SKIP][42] ([i915#4077]) +8 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-1/igt@gem_mmap_gtt@basic-small-bo.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy:
- shard-dg1: NOTRUN -> [SKIP][43] ([i915#4077]) +11 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
* igt@gem_mmap_wc@read-write:
- shard-dg2: NOTRUN -> [SKIP][44] ([i915#4083]) +3 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-11/igt@gem_mmap_wc@read-write.html
* igt@gem_mmap_wc@write-cpu-read-wc-unflushed:
- shard-dg1: NOTRUN -> [SKIP][45] ([i915#4083]) +6 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@gem_mmap_wc@write-cpu-read-wc-unflushed.html
* igt@gem_pwrite@basic-exhaustion:
- shard-dg1: NOTRUN -> [SKIP][46] ([i915#3282]) +6 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@gem_pwrite@basic-exhaustion.html
- shard-tglu: NOTRUN -> [WARN][47] ([i915#2658])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-2/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pwrite@basic-self:
- shard-dg2: NOTRUN -> [SKIP][48] ([i915#3282])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-11/igt@gem_pwrite@basic-self.html
* igt@gem_pxp@protected-encrypted-src-copy-not-readible:
- shard-dg1: NOTRUN -> [SKIP][49] ([i915#4270]) +4 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
* igt@gem_pxp@reject-modify-context-protection-off-2:
- shard-dg2: NOTRUN -> [SKIP][50] ([i915#4270]) +2 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-1/igt@gem_pxp@reject-modify-context-protection-off-2.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled:
- shard-dg2: NOTRUN -> [SKIP][51] ([i915#5190] / [i915#8428]) +5 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-1/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html
* igt@gem_set_tiling_vs_blt@untiled-to-tiled:
- shard-dg2: NOTRUN -> [SKIP][52] ([i915#4079])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
* igt@gem_tiled_pread_pwrite:
- shard-dg1: NOTRUN -> [SKIP][53] ([i915#4079]) +1 other test skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-17/igt@gem_tiled_pread_pwrite.html
* igt@gem_userptr_blits@access-control:
- shard-tglu-1: NOTRUN -> [SKIP][54] ([i915#3297])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@gem_userptr_blits@access-control.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-dg2: NOTRUN -> [SKIP][55] ([i915#3297]) +2 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-1/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-dg1: NOTRUN -> [SKIP][56] ([i915#3297]) +1 other test skip
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_userptr_blits@forbidden-operations:
- shard-dg2: NOTRUN -> [SKIP][57] ([i915#3282] / [i915#3297])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-1/igt@gem_userptr_blits@forbidden-operations.html
* igt@gem_userptr_blits@map-fixed-invalidate:
- shard-dg2: NOTRUN -> [SKIP][58] ([i915#3297] / [i915#4880])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-1/igt@gem_userptr_blits@map-fixed-invalidate.html
* igt@gem_userptr_blits@relocations:
- shard-dg2: NOTRUN -> [SKIP][59] ([i915#3281] / [i915#3297])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-8/igt@gem_userptr_blits@relocations.html
- shard-dg1: NOTRUN -> [SKIP][60] ([i915#3281] / [i915#3297])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@gem_userptr_blits@relocations.html
* igt@gem_userptr_blits@sd-probe:
- shard-dg1: NOTRUN -> [SKIP][61] ([i915#3297] / [i915#4958])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@gem_userptr_blits@sd-probe.html
* igt@gem_userptr_blits@unsync-overlap:
- shard-tglu: NOTRUN -> [SKIP][62] ([i915#3297])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-9/igt@gem_userptr_blits@unsync-overlap.html
* igt@gen7_exec_parse@bitmasks:
- shard-dg2: NOTRUN -> [SKIP][63] +11 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-8/igt@gen7_exec_parse@bitmasks.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][64] -> [ABORT][65] ([i915#5566])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-glk5/igt@gen9_exec_parse@allowed-single.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-glk9/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@batch-zero-length:
- shard-tglu: NOTRUN -> [SKIP][66] ([i915#2527] / [i915#2856]) +2 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-2/igt@gen9_exec_parse@batch-zero-length.html
* igt@gen9_exec_parse@bb-chained:
- shard-tglu-1: NOTRUN -> [SKIP][67] ([i915#2527] / [i915#2856]) +1 other test skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@gen9_exec_parse@bb-chained.html
* igt@gen9_exec_parse@bb-secure:
- shard-dg1: NOTRUN -> [SKIP][68] ([i915#2527]) +4 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@gen9_exec_parse@bb-secure.html
* igt@gen9_exec_parse@valid-registers:
- shard-dg2: NOTRUN -> [SKIP][69] ([i915#2856]) +3 other tests skip
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@gen9_exec_parse@valid-registers.html
* igt@i915_fb_tiling:
- shard-dg1: NOTRUN -> [SKIP][70] ([i915#4881])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@i915_fb_tiling.html
* igt@i915_module_load@resize-bar:
- shard-dg1: NOTRUN -> [SKIP][71] ([i915#7178])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@i915_module_load@resize-bar.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-tglu: NOTRUN -> [WARN][72] ([i915#2681]) +1 other test warn
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-5/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-glk: NOTRUN -> [FAIL][73] ([i915#12548] / [i915#3591]) +1 other test fail
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-glk1/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0:
- shard-dg1: NOTRUN -> [FAIL][74] ([i915#12739] / [i915#3591])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0:
- shard-dg1: NOTRUN -> [FAIL][75] ([i915#12548] / [i915#3591]) +1 other test fail
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
* igt@i915_pm_rps@thresholds-park:
- shard-dg2: NOTRUN -> [SKIP][76] ([i915#11681])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-1/igt@i915_pm_rps@thresholds-park.html
* igt@i915_selftest@live@workarounds:
- shard-mtlp: [PASS][77] -> [ABORT][78] ([i915#12061]) +1 other test abort
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-mtlp-7/igt@i915_selftest@live@workarounds.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-mtlp-4/igt@i915_selftest@live@workarounds.html
* igt@i915_selftest@mock@memory_region:
- shard-dg1: NOTRUN -> [DMESG-WARN][79] ([i915#9311]) +1 other test dmesg-warn
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@i915_selftest@mock@memory_region.html
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- shard-dg2: NOTRUN -> [SKIP][80] ([i915#4212])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
* igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
- shard-tglu-1: NOTRUN -> [SKIP][81] ([i915#12454] / [i915#12712])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- shard-dg1: NOTRUN -> [SKIP][82] ([i915#4212]) +2 other tests skip
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-dg1: [PASS][83] -> [DMESG-WARN][84] ([i915#4423]) +2 other tests dmesg-warn
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-dg1-13/igt@kms_async_flips@alternate-sync-async-flip.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-18/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc-ccs:
- shard-dg1: NOTRUN -> [SKIP][85] ([i915#8709]) +7 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc-ccs.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-dp-4-4-rc-ccs-cc:
- shard-dg2: NOTRUN -> [SKIP][86] ([i915#8709]) +11 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-10/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-dp-4-4-rc-ccs-cc.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-glk: NOTRUN -> [SKIP][87] ([i915#1769])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-glk1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-dg1: NOTRUN -> [SKIP][88] ([i915#1769] / [i915#3555]) +1 other test skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-17/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-3:
- shard-dg2: [PASS][89] -> [FAIL][90] ([i915#5956]) +1 other test fail
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-dg2-7/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-3.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-1/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-3.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-270:
- shard-tglu-1: NOTRUN -> [SKIP][91] ([i915#5286]) +1 other test skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-addfb:
- shard-dg1: NOTRUN -> [SKIP][92] ([i915#5286])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@kms_big_fb@4-tiled-addfb.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-tglu: NOTRUN -> [SKIP][93] ([i915#5286]) +3 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-dg1: NOTRUN -> [SKIP][94] ([i915#4538] / [i915#5286]) +5 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@linear-64bpp-rotate-90:
- shard-dg1: NOTRUN -> [SKIP][95] ([i915#3638]) +5 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@kms_big_fb@linear-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- shard-dg2: NOTRUN -> [SKIP][96] ([i915#5190]) +2 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-1/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-dg2: NOTRUN -> [SKIP][97] ([i915#4538] / [i915#5190]) +8 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180:
- shard-dg1: NOTRUN -> [SKIP][98] ([i915#4538]) +4 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][99] ([i915#6095]) +44 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-2/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-1.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][100] ([i915#10307] / [i915#10434] / [i915#6095]) +3 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-8/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs:
- shard-snb: NOTRUN -> [SKIP][101] +41 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-snb1/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][102] ([i915#10307] / [i915#6095]) +186 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][103] ([i915#6095]) +161 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-14/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][104] ([i915#6095]) +93 other tests skip
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-rkl-7/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][105] ([i915#12805])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
- shard-dg1: NOTRUN -> [SKIP][106] ([i915#12805])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-14/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
- shard-dg2: NOTRUN -> [SKIP][107] ([i915#12805])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][108] ([i915#6095]) +39 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-b-dp-4:
- shard-dg2: NOTRUN -> [SKIP][109] ([i915#6095]) +7 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-10/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-b-dp-4.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
- shard-tglu: NOTRUN -> [SKIP][110] ([i915#12313])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-5/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html
* igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [SKIP][111] +48 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-glk1/igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-1.html
* igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs:
- shard-dg1: NOTRUN -> [SKIP][112] ([i915#12313])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][113] ([i915#7213]) +3 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-3/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html
* igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][114] ([i915#4087]) +3 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-4/igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1.html
* igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k:
- shard-dg2: NOTRUN -> [SKIP][115] ([i915#7828]) +7 other tests skip
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html
* igt@kms_chamelium_hpd@dp-hpd-after-suspend:
- shard-tglu: NOTRUN -> [SKIP][116] ([i915#7828]) +4 other tests skip
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-5/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html
* igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
- shard-tglu-1: NOTRUN -> [SKIP][117] ([i915#7828]) +3 other tests skip
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html
- shard-dg1: NOTRUN -> [SKIP][118] ([i915#7828]) +13 other tests skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-14/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html
* igt@kms_content_protection@atomic-dpms:
- shard-dg1: NOTRUN -> [SKIP][119] ([i915#7116] / [i915#9424])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@content-type-change:
- shard-dg1: NOTRUN -> [SKIP][120] ([i915#9424])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@kms_content_protection@content-type-change.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-dg1: NOTRUN -> [SKIP][121] ([i915#3299]) +1 other test skip
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-dg2: NOTRUN -> [SKIP][122] ([i915#3299])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@legacy:
- shard-tglu: NOTRUN -> [SKIP][123] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-5/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@mei-interface:
- shard-tglu-1: NOTRUN -> [SKIP][124] ([i915#6944] / [i915#9424])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@type1:
- shard-dg2: NOTRUN -> [SKIP][125] ([i915#7118] / [i915#9424])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-1/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@cursor-offscreen-32x32:
- shard-tglu-1: NOTRUN -> [SKIP][126] ([i915#3555]) +6 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@kms_cursor_crc@cursor-offscreen-32x32.html
* igt@kms_cursor_crc@cursor-offscreen-512x170:
- shard-tglu: NOTRUN -> [SKIP][127] ([i915#13049]) +1 other test skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-2/igt@kms_cursor_crc@cursor-offscreen-512x170.html
* igt@kms_cursor_crc@cursor-random-32x10:
- shard-tglu: NOTRUN -> [SKIP][128] ([i915#3555]) +1 other test skip
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-2/igt@kms_cursor_crc@cursor-random-32x10.html
* igt@kms_cursor_crc@cursor-random-32x32:
- shard-dg1: NOTRUN -> [SKIP][129] ([i915#3555]) +8 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@kms_cursor_crc@cursor-random-32x32.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-dg2: NOTRUN -> [SKIP][130] ([i915#13049])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
- shard-tglu-1: NOTRUN -> [SKIP][131] ([i915#13049])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-dg1: NOTRUN -> [SKIP][132] ([i915#13049]) +3 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- shard-tglu-1: NOTRUN -> [SKIP][133] ([i915#4103])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
- shard-dg1: NOTRUN -> [SKIP][134] ([i915#9067])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
- shard-tglu: NOTRUN -> [SKIP][135] ([i915#4103]) +1 other test skip
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
- shard-dg1: NOTRUN -> [SKIP][136] ([i915#4103] / [i915#4213])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
* igt@kms_cursor_legacy@short-flip-before-cursor-toggle:
- shard-glk: [PASS][137] -> [FAIL][138] ([i915#2346])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-glk3/igt@kms_cursor_legacy@short-flip-before-cursor-toggle.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-glk8/igt@kms_cursor_legacy@short-flip-before-cursor-toggle.html
* igt@kms_dirtyfb@psr-dirtyfb-ioctl:
- shard-dg1: NOTRUN -> [SKIP][139] ([i915#9723])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
- shard-dg2: NOTRUN -> [SKIP][140] ([i915#9833])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-8/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
* igt@kms_dp_linktrain_fallback@dp-fallback:
- shard-dg2: [PASS][141] -> [SKIP][142] ([i915#12402])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-dg2-10/igt@kms_dp_linktrain_fallback@dp-fallback.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-11/igt@kms_dp_linktrain_fallback@dp-fallback.html
* igt@kms_draw_crc@draw-method-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][143] ([i915#8812])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@kms_draw_crc@draw-method-mmap-gtt.html
* igt@kms_dsc@dsc-basic:
- shard-tglu: NOTRUN -> [SKIP][144] ([i915#3555] / [i915#3840])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-5/igt@kms_dsc@dsc-basic.html
* igt@kms_fbcon_fbt@psr:
- shard-dg2: NOTRUN -> [SKIP][145] ([i915#3469])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_fbcon_fbt@psr.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-dg1: NOTRUN -> [SKIP][146] ([i915#3469])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_feature_discovery@display-3x:
- shard-dg2: NOTRUN -> [SKIP][147] ([i915#1839]) +2 other tests skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-1/igt@kms_feature_discovery@display-3x.html
* igt@kms_flip@2x-nonexisting-fb-interruptible:
- shard-tglu: NOTRUN -> [SKIP][148] ([i915#3637]) +3 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-9/igt@kms_flip@2x-nonexisting-fb-interruptible.html
* igt@kms_flip@2x-plain-flip:
- shard-dg2: NOTRUN -> [SKIP][149] ([i915#9934]) +8 other tests skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_flip@2x-plain-flip.html
- shard-tglu-1: NOTRUN -> [SKIP][150] ([i915#3637]) +3 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@kms_flip@2x-plain-flip.html
- shard-dg1: NOTRUN -> [SKIP][151] ([i915#9934]) +8 other tests skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-14/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@a-hdmi-a1:
- shard-tglu: [PASS][152] -> [FAIL][153] ([i915#11989]) +8 other tests fail
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-tglu-4/igt@kms_flip@flip-vs-blocking-wf-vblank@a-hdmi-a1.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-6/igt@kms_flip@flip-vs-blocking-wf-vblank@a-hdmi-a1.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@c-hdmi-a3:
- shard-dg2: NOTRUN -> [FAIL][154] ([i915#11989]) +2 other tests fail
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-3/igt@kms_flip@flip-vs-blocking-wf-vblank@c-hdmi-a3.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@d-hdmi-a4:
- shard-dg1: NOTRUN -> [FAIL][155] ([i915#11989]) +2 other tests fail
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-14/igt@kms_flip@flip-vs-blocking-wf-vblank@d-hdmi-a4.html
* igt@kms_flip@flip-vs-fences-interruptible:
- shard-dg2: NOTRUN -> [SKIP][156] ([i915#8381]) +1 other test skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_flip@flip-vs-fences-interruptible.html
- shard-dg1: NOTRUN -> [SKIP][157] ([i915#8381])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-14/igt@kms_flip@flip-vs-fences-interruptible.html
* igt@kms_flip@plain-flip-fb-recreate@a-vga1:
- shard-snb: [PASS][158] -> [FAIL][159] ([i915#11989]) +6 other tests fail
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-snb2/igt@kms_flip@plain-flip-fb-recreate@a-vga1.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-snb1/igt@kms_flip@plain-flip-fb-recreate@a-vga1.html
* igt@kms_flip@wf_vblank-ts-check@b-edp1:
- shard-mtlp: [PASS][160] -> [FAIL][161] ([i915#11989]) +1 other test fail
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-mtlp-6/igt@kms_flip@wf_vblank-ts-check@b-edp1.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-mtlp-3/igt@kms_flip@wf_vblank-ts-check@b-edp1.html
* igt@kms_flip@wf_vblank-ts-check@c-edp1:
- shard-mtlp: [PASS][162] -> [FAIL][163] ([i915#11989] / [i915#13071])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-mtlp-6/igt@kms_flip@wf_vblank-ts-check@c-edp1.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-mtlp-3/igt@kms_flip@wf_vblank-ts-check@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][164] ([i915#2587] / [i915#2672]) +9 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling:
- shard-tglu-1: NOTRUN -> [SKIP][165] ([i915#2672] / [i915#3555])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-tglu-1: NOTRUN -> [SKIP][166] ([i915#2587] / [i915#2672])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
- shard-dg2: NOTRUN -> [SKIP][167] ([i915#2672] / [i915#3555]) +2 other tests skip
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][168] ([i915#2587] / [i915#2672]) +2 other tests skip
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
- shard-dg1: NOTRUN -> [SKIP][169] ([i915#2587] / [i915#2672] / [i915#3555])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
- shard-tglu: NOTRUN -> [SKIP][170] ([i915#2587] / [i915#2672] / [i915#3555]) +1 other test skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling:
- shard-tglu: NOTRUN -> [SKIP][171] ([i915#2672] / [i915#3555])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
- shard-dg1: NOTRUN -> [SKIP][172] ([i915#2672] / [i915#3555]) +8 other tests skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling:
- shard-dg2: NOTRUN -> [SKIP][173] ([i915#2672] / [i915#3555] / [i915#5190]) +1 other test skip
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][174] ([i915#2672]) +4 other tests skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
- shard-dg2: [PASS][175] -> [FAIL][176] ([i915#6880])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render:
- shard-tglu: NOTRUN -> [SKIP][177] +48 other tests skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt:
- shard-snb: [PASS][178] -> [SKIP][179] +4 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-snb5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-dg1: NOTRUN -> [SKIP][180] ([i915#5439])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][181] ([i915#8708]) +18 other tests skip
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-pwrite:
- shard-dg1: NOTRUN -> [SKIP][182] +55 other tests skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][183] ([i915#8708]) +12 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][184] ([i915#3458]) +17 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][185] ([i915#5354]) +29 other tests skip
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite:
- shard-dg1: NOTRUN -> [SKIP][186] ([i915#3458]) +25 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-14/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-dg1: NOTRUN -> [SKIP][187] ([i915#3555] / [i915#8228]) +2 other tests skip
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@kms_hdr@bpc-switch-dpms.html
- shard-tglu: NOTRUN -> [SKIP][188] ([i915#3555] / [i915#8228])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-2/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_hdr@invalid-hdr:
- shard-dg2: NOTRUN -> [SKIP][189] ([i915#3555] / [i915#8228])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-1/igt@kms_hdr@invalid-hdr.html
* igt@kms_hdr@static-swap:
- shard-dg2: [PASS][190] -> [SKIP][191] ([i915#3555] / [i915#8228])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-dg2-10/igt@kms_hdr@static-swap.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-11/igt@kms_hdr@static-swap.html
* igt@kms_hdr@static-toggle-dpms:
- shard-tglu-1: NOTRUN -> [SKIP][192] ([i915#3555] / [i915#8228])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_joiner@basic-force-ultra-joiner:
- shard-dg1: NOTRUN -> [SKIP][193] ([i915#12394])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-17/igt@kms_joiner@basic-force-ultra-joiner.html
* igt@kms_joiner@basic-ultra-joiner:
- shard-dg1: NOTRUN -> [SKIP][194] ([i915#12339])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@kms_joiner@basic-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- shard-dg1: NOTRUN -> [SKIP][195] ([i915#12388])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-dg2: NOTRUN -> [SKIP][196] ([i915#4816])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-8/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
- shard-dg1: NOTRUN -> [SKIP][197] ([i915#1839]) +1 other test skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes:
- shard-tglu-1: NOTRUN -> [SKIP][198] +36 other tests skip
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes.html
* igt@kms_plane_lowres@tiling-yf:
- shard-dg2: NOTRUN -> [SKIP][199] ([i915#3555] / [i915#8821])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format:
- shard-tglu-1: NOTRUN -> [SKIP][200] ([i915#12247]) +14 other tests skip
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html
- shard-dg1: NOTRUN -> [SKIP][201] ([i915#12247]) +18 other tests skip
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-14/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html
- shard-dg2: NOTRUN -> [SKIP][202] ([i915#12247] / [i915#9423])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-d:
- shard-dg2: NOTRUN -> [SKIP][203] ([i915#12247]) +11 other tests skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-d.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation:
- shard-tglu: NOTRUN -> [SKIP][204] ([i915#12247]) +8 other tests skip
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-5/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25:
- shard-dg1: NOTRUN -> [SKIP][205] ([i915#12247] / [i915#6953])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@kms_plane_scaling@planes-downscale-factor-0-25.html
- shard-tglu: NOTRUN -> [SKIP][206] ([i915#12247] / [i915#6953])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-2/igt@kms_plane_scaling@planes-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25:
- shard-dg2: NOTRUN -> [SKIP][207] ([i915#12247] / [i915#6953] / [i915#9423])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-1/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25:
- shard-dg2: NOTRUN -> [SKIP][208] ([i915#12247] / [i915#3555] / [i915#9423])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-1/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html
* igt@kms_pm_backlight@fade-with-dpms:
- shard-dg1: NOTRUN -> [SKIP][209] ([i915#5354]) +3 other tests skip
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-17/igt@kms_pm_backlight@fade-with-dpms.html
* igt@kms_pm_dc@dc5-retention-flops:
- shard-tglu: NOTRUN -> [SKIP][210] ([i915#3828])
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-5/igt@kms_pm_dc@dc5-retention-flops.html
* igt@kms_pm_dc@dc6-dpms:
- shard-dg1: NOTRUN -> [SKIP][211] ([i915#3361])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-dg2: NOTRUN -> [SKIP][212] ([i915#9340])
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_lpsp@screens-disabled:
- shard-tglu-1: NOTRUN -> [SKIP][213] ([i915#8430])
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@kms_pm_lpsp@screens-disabled.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-dg2: [PASS][214] -> [SKIP][215] ([i915#9519])
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-dg2-8/igt@kms_pm_rpm@modeset-lpsp-stress.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-2/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-rkl: [PASS][216] -> [SKIP][217] ([i915#9519]) +2 other tests skip
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-rkl-3/igt@kms_pm_rpm@modeset-non-lpsp.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-rkl-7/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-tglu-1: NOTRUN -> [SKIP][218] ([i915#9519])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_prime@basic-crc-hybrid:
- shard-dg2: NOTRUN -> [SKIP][219] ([i915#6524] / [i915#6805])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_prop_blob@blob-prop-core:
- shard-dg1: NOTRUN -> [DMESG-WARN][220] ([i915#4423]) +3 other tests dmesg-warn
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@kms_prop_blob@blob-prop-core.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
- shard-tglu-1: NOTRUN -> [SKIP][221] ([i915#11520]) +3 other tests skip
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
- shard-tglu: NOTRUN -> [SKIP][222] ([i915#11520]) +4 other tests skip
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-5/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area:
- shard-dg1: NOTRUN -> [SKIP][223] ([i915#11520]) +10 other tests skip
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area.html
- shard-glk: NOTRUN -> [SKIP][224] ([i915#11520]) +1 other test skip
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-glk1/igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area-big-fb:
- shard-dg2: NOTRUN -> [SKIP][225] ([i915#11520]) +5 other tests skip
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-1/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
- shard-snb: NOTRUN -> [SKIP][226] ([i915#11520]) +1 other test skip
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-snb5/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr@fbc-psr-no-drrs:
- shard-tglu: NOTRUN -> [SKIP][227] ([i915#9732]) +12 other tests skip
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-2/igt@kms_psr@fbc-psr-no-drrs.html
* igt@kms_psr@fbc-psr2-sprite-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][228] ([i915#1072] / [i915#9732]) +28 other tests skip
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@kms_psr@fbc-psr2-sprite-mmap-gtt.html
* igt@kms_psr@psr2-cursor-mmap-gtt:
- shard-tglu-1: NOTRUN -> [SKIP][229] ([i915#9732]) +10 other tests skip
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@kms_psr@psr2-cursor-mmap-gtt.html
* igt@kms_psr@psr2-primary-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][230] ([i915#1072] / [i915#9732]) +22 other tests skip
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_psr@psr2-primary-mmap-gtt.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-dg2: NOTRUN -> [SKIP][231] ([i915#9685])
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-dg1: NOTRUN -> [SKIP][232] ([i915#9685])
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-dg2: NOTRUN -> [SKIP][233] ([i915#12755] / [i915#5190]) +1 other test skip
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-dg2: NOTRUN -> [SKIP][234] ([i915#12755])
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@kms_setmode@invalid-clone-single-crtc:
- shard-dg2: NOTRUN -> [SKIP][235] ([i915#3555]) +4 other tests skip
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_setmode@invalid-clone-single-crtc.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-dg1: NOTRUN -> [SKIP][236] ([i915#8623])
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@kms_tiled_display@basic-test-pattern.html
- shard-glk: NOTRUN -> [FAIL][237] ([i915#10959])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-glk1/igt@kms_tiled_display@basic-test-pattern.html
- shard-dg2: NOTRUN -> [SKIP][238] ([i915#8623])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-8/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_universal_plane@cursor-fb-leak:
- shard-dg1: NOTRUN -> [FAIL][239] ([i915#9196]) +1 other test fail
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@kms_universal_plane@cursor-fb-leak.html
- shard-mtlp: [PASS][240] -> [FAIL][241] ([i915#9196]) +1 other test fail
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-mtlp-8/igt@kms_universal_plane@cursor-fb-leak.html
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-mtlp-3/igt@kms_universal_plane@cursor-fb-leak.html
* igt@kms_vblank@wait-forked-busy-hang@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [DMESG-WARN][242] ([i915#12964]) +9 other tests dmesg-warn
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-rkl-3/igt@kms_vblank@wait-forked-busy-hang@pipe-a-hdmi-a-2.html
* igt@kms_vrr@lobf:
- shard-dg1: NOTRUN -> [SKIP][243] ([i915#11920])
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@kms_vrr@lobf.html
* igt@kms_vrr@max-min:
- shard-tglu-1: NOTRUN -> [SKIP][244] ([i915#9906])
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@kms_vrr@max-min.html
- shard-dg1: NOTRUN -> [SKIP][245] ([i915#9906])
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-14/igt@kms_vrr@max-min.html
- shard-dg2: NOTRUN -> [SKIP][246] ([i915#9906]) +1 other test skip
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_vrr@max-min.html
* igt@kms_vrr@negative-basic:
- shard-dg1: NOTRUN -> [SKIP][247] ([i915#3555] / [i915#9906])
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-17/igt@kms_vrr@negative-basic.html
* igt@kms_writeback@writeback-check-output-xrgb2101010:
- shard-glk: NOTRUN -> [SKIP][248] ([i915#2437])
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-glk1/igt@kms_writeback@writeback-check-output-xrgb2101010.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-dg2: NOTRUN -> [SKIP][249] ([i915#2437] / [i915#9412])
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
- shard-tglu-1: NOTRUN -> [SKIP][250] ([i915#2437] / [i915#9412])
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-1/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
- shard-dg1: NOTRUN -> [SKIP][251] ([i915#2437] / [i915#9412]) +1 other test skip
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-14/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-dg1: NOTRUN -> [SKIP][252] ([i915#2437])
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-17/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@mi-rpc:
- shard-dg2: NOTRUN -> [SKIP][253] ([i915#2434])
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-8/igt@perf@mi-rpc.html
- shard-dg1: NOTRUN -> [SKIP][254] ([i915#2434])
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@perf@mi-rpc.html
* igt@perf_pmu@frequency@gt0:
- shard-dg1: NOTRUN -> [FAIL][255] ([i915#12549] / [i915#6806]) +1 other test fail
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@perf_pmu@frequency@gt0.html
* igt@prime_mmap@test_aperture_limit:
- shard-dg2: NOTRUN -> [WARN][256] ([i915#9351])
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@prime_mmap@test_aperture_limit.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: NOTRUN -> [CRASH][257] ([i915#9351])
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-5/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
* igt@prime_vgem@basic-fence-mmap:
- shard-dg1: NOTRUN -> [SKIP][258] ([i915#3708] / [i915#4077])
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-gtt:
- shard-dg2: NOTRUN -> [SKIP][259] ([i915#3708] / [i915#4077])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-1/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@fence-flip-hang:
- shard-dg1: NOTRUN -> [SKIP][260] ([i915#3708])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-13/igt@prime_vgem@fence-flip-hang.html
- shard-dg2: NOTRUN -> [SKIP][261] ([i915#3708])
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-8/igt@prime_vgem@fence-flip-hang.html
* igt@sriov_basic@enable-vfs-bind-unbind-each:
- shard-dg1: NOTRUN -> [SKIP][262] ([i915#9917])
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-12/igt@sriov_basic@enable-vfs-bind-unbind-each.html
#### Possible fixes ####
* igt@drm_fdinfo@isolation:
- shard-rkl: [DMESG-WARN][263] ([i915#12917] / [i915#12964]) -> [PASS][264] +1 other test pass
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-rkl-4/igt@drm_fdinfo@isolation.html
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-rkl-1/igt@drm_fdinfo@isolation.html
* igt@gem_ccs@suspend-resume:
- shard-dg2: [INCOMPLETE][265] ([i915#7297]) -> [PASS][266] +1 other test pass
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-dg2-1/igt@gem_ccs@suspend-resume.html
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-8/igt@gem_ccs@suspend-resume.html
* igt@gem_exec_suspend@basic-s4-devices:
- shard-tglu: [ABORT][267] ([i915#7975] / [i915#8213]) -> [PASS][268] +1 other test pass
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-tglu-10/igt@gem_exec_suspend@basic-s4-devices.html
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-9/igt@gem_exec_suspend@basic-s4-devices.html
- shard-dg2: [ABORT][269] ([i915#7975] / [i915#8213]) -> [PASS][270] +1 other test pass
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-dg2-10/igt@gem_exec_suspend@basic-s4-devices.html
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-11/igt@gem_exec_suspend@basic-s4-devices.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-mtlp: [ABORT][271] ([i915#10131] / [i915#10887]) -> [PASS][272]
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-mtlp-3/igt@i915_module_load@reload-with-fault-injection.html
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-mtlp-5/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rps@min-max-config-idle:
- shard-rkl: [DMESG-WARN][273] ([i915#12964]) -> [PASS][274]
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-rkl-4/igt@i915_pm_rps@min-max-config-idle.html
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-rkl-3/igt@i915_pm_rps@min-max-config-idle.html
* igt@i915_suspend@fence-restore-untiled:
- shard-glk: [INCOMPLETE][275] ([i915#4817]) -> [PASS][276]
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-glk1/igt@i915_suspend@fence-restore-untiled.html
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-glk1/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-4:
- shard-dg1: [FAIL][277] ([i915#5956]) -> [PASS][278] +1 other test pass
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-dg1-14/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-4.html
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-14/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-4.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
- shard-mtlp: [FAIL][279] ([i915#5138]) -> [PASS][280]
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
- shard-mtlp: [FAIL][281] ([i915#2346]) -> [PASS][282]
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-mtlp-7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-mtlp-7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
* igt@kms_flip@2x-blocking-wf_vblank@ab-vga1-hdmi-a1:
- shard-snb: [FAIL][283] ([i915#11989]) -> [PASS][284] +7 other tests pass
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-snb5/igt@kms_flip@2x-blocking-wf_vblank@ab-vga1-hdmi-a1.html
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-snb7/igt@kms_flip@2x-blocking-wf_vblank@ab-vga1-hdmi-a1.html
* igt@kms_flip@2x-flip-vs-fences-interruptible:
- shard-snb: [INCOMPLETE][285] -> [PASS][286] +2 other tests pass
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-snb2/igt@kms_flip@2x-flip-vs-fences-interruptible.html
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-snb1/igt@kms_flip@2x-flip-vs-fences-interruptible.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1:
- shard-mtlp: [FAIL][287] ([i915#11989]) -> [PASS][288] +2 other tests pass
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-mtlp-3/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-mtlp-2/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- shard-dg2: [SKIP][289] ([i915#12388]) -> [PASS][290]
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-dg2-2/igt@kms_joiner@invalid-modeset-force-big-joiner.html
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-10/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@kms_pm_dc@dc9-dpms:
- shard-tglu: [SKIP][291] ([i915#4281]) -> [PASS][292]
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-tglu-9/igt@kms_pm_dc@dc9-dpms.html
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-2/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-rkl: [SKIP][293] ([i915#9519]) -> [PASS][294] +1 other test pass
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-rkl-2/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
#### Warnings ####
* igt@kms_flip@2x-flip-vs-suspend:
- shard-glk: [INCOMPLETE][295] ([i915#12745] / [i915#1982] / [i915#4839]) -> [INCOMPLETE][296] ([i915#12745] / [i915#4839])
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-glk5/igt@kms_flip@2x-flip-vs-suspend.html
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-glk5/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2:
- shard-glk: [INCOMPLETE][297] ([i915#1982] / [i915#4839]) -> [INCOMPLETE][298] ([i915#4839])
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-glk5/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-glk5/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-blocking-wf-vblank:
- shard-dg1: [FAIL][299] ([i915#11989] / [i915#12517]) -> [FAIL][300] ([i915#11989] / [i915#12517] / [i915#12740])
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-dg1-12/igt@kms_flip@flip-vs-blocking-wf-vblank.html
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-14/igt@kms_flip@flip-vs-blocking-wf-vblank.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt:
- shard-dg2: [SKIP][301] ([i915#10433] / [i915#3458]) -> [SKIP][302] ([i915#3458]) +2 other tests skip
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt.html
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-3/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt:
- shard-dg2: [SKIP][303] ([i915#3458]) -> [SKIP][304] ([i915#10433] / [i915#3458])
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-dg2-10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_hdr@brightness-with-hdr:
- shard-dg2: [SKIP][305] -> [SKIP][306] ([i915#12713])
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-dg2-10/igt@kms_hdr@brightness-with-hdr.html
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-4/igt@kms_hdr@brightness-with-hdr.html
- shard-dg1: [SKIP][307] ([i915#1187] / [i915#12713]) -> [SKIP][308] ([i915#12713])
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-dg1-13/igt@kms_hdr@brightness-with-hdr.html
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg1-18/igt@kms_hdr@brightness-with-hdr.html
- shard-tglu: [SKIP][309] ([i915#1187] / [i915#12713]) -> [SKIP][310] ([i915#12713])
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-tglu-2/igt@kms_hdr@brightness-with-hdr.html
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-tglu-10/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][311] ([i915#4816]) -> [SKIP][312] ([i915#4070] / [i915#4816])
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-rkl-7/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-rkl-2/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-dg2: [FAIL][313] ([i915#8292]) -> [SKIP][314] ([i915#6953] / [i915#9423])
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-dg2-10/igt@kms_plane_scaling@intel-max-src-size.html
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-dg2-4/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-rkl: [SKIP][315] ([i915#3828]) -> [SKIP][316] ([i915#9340])
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-rkl-4/igt@kms_pm_lpsp@kms-lpsp.html
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-rkl-1/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-rkl: [DMESG-WARN][317] ([i915#12964]) -> [SKIP][318] ([i915#9519]) +1 other test skip
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15759/shard-rkl-3/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/shard-rkl-7/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10055]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10055
[i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#10887]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10887
[i915#10959]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10959
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#11527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11527
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#11814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11814
[i915#11815]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11815
[i915#1187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1187
[i915#11920]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11920
[i915#11965]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11965
[i915#11989]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11989
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12193]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12193
[i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
[i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
[i915#12339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12339
[i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
[i915#12394]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12394
[i915#12402]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12402
[i915#12454]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12454
[i915#12517]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12517
[i915#12548]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12548
[i915#12549]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12549
[i915#12558]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12558
[i915#12712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12712
[i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
[i915#12739]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12739
[i915#12740]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12740
[i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
[i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
[i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
[i915#12917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12917
[i915#12964]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12964
[i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
[i915#13071]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13071
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
[i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2681
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#3936]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3936
[i915#4070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4087
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
[i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
[i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
[i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
[i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4881
[i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
[i915#4958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4958
[i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
[i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
[i915#5566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5566
[i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6117
[i915#6228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6228
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
[i915#6805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6805
[i915#6806]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6806
[i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7178]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7178
[i915#7213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7213
[i915#7297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7297
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
[i915#8213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8289
[i915#8292]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8292
[i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
[i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
[i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
[i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
[i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
[i915#8812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8812
[i915#8821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8821
[i915#8898]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8898
[i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
[i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
[i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
[i915#9351]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9351
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
[i915#9561]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9561
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9833]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9833
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_15759 -> Patchwork_141846v2
CI-20190529: 20190529
CI_DRM_15759: 5379d0a88558b73308ad82f163e80b863626e90b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8129: 363499a879fee5b9b7eda8acf7c772bce3423493 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_141846v2: 5379d0a88558b73308ad82f163e80b863626e90b @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141846v2/index.html
[-- Attachment #2: Type: text/html, Size: 109057 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2024-11-29 19:12 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-11-28 15:38 [PATCH v2 0/6] drm/i915/display: power conversion to struct intel_display Jani Nikula
2024-11-28 15:38 ` [PATCH v2 1/6] drm/i915/display: convert for_each_power_well() " Jani Nikula
2024-11-28 15:38 ` [PATCH v2 2/6] drm/i915/display: convert for_each_power_domain_well() " Jani Nikula
2024-11-28 15:38 ` [PATCH v2 3/6] drm/i915/display: convert power wells " Jani Nikula
2024-11-28 15:38 ` [PATCH v2 4/6] drm/i915/display: convert power domain code internally " Jani Nikula
2024-11-29 14:17 ` Imre Deak
2024-11-29 14:46 ` Jani Nikula
2024-11-28 15:38 ` [PATCH v2 5/6] drm/i915/display: convert high level power interfaces " Jani Nikula
2024-11-28 15:38 ` [PATCH v2 6/6] drm/i915/display: convert power map " Jani Nikula
2024-11-28 18:13 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: power conversion to struct intel_display (rev2) Patchwork
2024-11-28 18:13 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-11-28 18:22 ` ✗ i915.CI.BAT: failure " Patchwork
2024-11-29 8:19 ` Jani Nikula
2024-11-29 16:08 ` Illipilli, TejasreeX
2024-11-29 14:00 ` ✓ i915.CI.BAT: success " Patchwork
2024-11-29 14:18 ` [PATCH v2 0/6] drm/i915/display: power conversion to struct intel_display Imre Deak
2024-11-29 19:12 ` ✗ i915.CI.Full: failure for drm/i915/display: power conversion to struct intel_display (rev2) Patchwork
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