* [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display
@ 2025-04-08 13:38 Jani Nikula
2025-04-08 13:38 ` [PATCH v2 1/7] drm/i915/wm: convert intel_wm.h external interfaces " Jani Nikula
` (11 more replies)
0 siblings, 12 replies; 14+ messages in thread
From: Jani Nikula @ 2025-04-08 13:38 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
v2 of [1], basically just a rebase.
BR,
Jani.
[1] https://lore.kernel.org/r/cover.1743671373.git.jani.nikula@intel.com
Jani Nikula (7):
drm/i915/wm: convert intel_wm.h external interfaces to struct
intel_display
drm/i915/wm: convert intel_wm.c internally to struct intel_display
drm/i915/wm: convert skl_watermark.h external interfaces to struct
intel_display
drm/i915/wm: convert skl_watermarks.c internally to struct
intel_display
drm/i915/wm: convert i9xx_wm.h external interfaces to struct
intel_display
drm/i915/wm: convert i9xx_wm.c to intel_de_*() register interface
drm/i915/wm: convert i9xx_wm.c internally to struct intel_display
drivers/gpu/drm/i915/display/i9xx_wm.c | 1222 ++++++++---------
drivers/gpu/drm/i915/display/i9xx_wm.h | 18 +-
drivers/gpu/drm/i915/display/intel_bw.c | 24 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 22 +-
.../gpu/drm/i915/display/intel_display_core.h | 6 +-
.../drm/i915/display/intel_display_debugfs.c | 3 +-
.../drm/i915/display/intel_display_driver.c | 12 +-
drivers/gpu/drm/i915/display/intel_dsb.c | 4 +-
.../drm/i915/display/intel_modeset_setup.c | 11 +-
drivers/gpu/drm/i915/display/intel_wm.c | 171 +--
drivers/gpu/drm/i915/display/intel_wm.h | 14 +-
drivers/gpu/drm/i915/display/skl_watermark.c | 616 ++++-----
drivers/gpu/drm/i915/display/skl_watermark.h | 23 +-
drivers/gpu/drm/i915/i915_driver.c | 2 +-
drivers/gpu/drm/xe/display/xe_display.c | 2 +-
16 files changed, 1057 insertions(+), 1097 deletions(-)
--
2.39.5
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 1/7] drm/i915/wm: convert intel_wm.h external interfaces to struct intel_display
2025-04-08 13:38 [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display Jani Nikula
@ 2025-04-08 13:38 ` Jani Nikula
2025-04-08 13:38 ` [PATCH v2 2/7] drm/i915/wm: convert intel_wm.c internally " Jani Nikula
` (10 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2025-04-08 13:38 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Going forward, struct intel_display is the main display device data
pointer. Convert the intel_wm.h interface as well as the hooks in struct
intel_wm_funcs to struct intel_display.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 51 +++++++++++--------
drivers/gpu/drm/i915/display/intel_display.c | 10 ++--
.../gpu/drm/i915/display/intel_display_core.h | 6 +--
.../drm/i915/display/intel_display_debugfs.c | 3 +-
.../drm/i915/display/intel_display_driver.c | 2 +-
.../drm/i915/display/intel_modeset_setup.c | 11 ++--
drivers/gpu/drm/i915/display/intel_wm.c | 41 ++++++++-------
drivers/gpu/drm/i915/display/intel_wm.h | 14 ++---
drivers/gpu/drm/i915/display/skl_watermark.c | 10 ++--
9 files changed, 80 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 7c80e37c1c5f..e6a1b9b10b01 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -641,8 +641,9 @@ static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
return enabled;
}
-static void pnv_update_wm(struct drm_i915_private *dev_priv)
+static void pnv_update_wm(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_crtc *crtc;
const struct cxsr_latency *latency;
u32 reg;
@@ -2123,8 +2124,9 @@ static void vlv_optimize_watermarks(struct intel_atomic_state *state,
mutex_unlock(&dev_priv->display.wm.wm_mutex);
}
-static void i965_update_wm(struct drm_i915_private *dev_priv)
+static void i965_update_wm(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_crtc *crtc;
int srwm = 1;
int cursor_sr = 16;
@@ -2216,8 +2218,9 @@ static struct intel_crtc *intel_crtc_for_plane(struct drm_i915_private *i915,
return NULL;
}
-static void i9xx_update_wm(struct drm_i915_private *dev_priv)
+static void i9xx_update_wm(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
const struct intel_watermark_params *wm_info;
u32 fwater_lo;
u32 fwater_hi;
@@ -2359,8 +2362,9 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
intel_set_memory_cxsr(dev_priv, true);
}
-static void i845_update_wm(struct drm_i915_private *dev_priv)
+static void i845_update_wm(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_crtc *crtc;
u32 fwater_lo;
int planea_wm;
@@ -2813,6 +2817,7 @@ static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
bool changed;
/*
@@ -2828,13 +2833,14 @@ static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm,
"WM latency values increased to avoid potential underruns\n");
- intel_print_wm_latency(dev_priv, "Primary", dev_priv->display.wm.pri_latency);
- intel_print_wm_latency(dev_priv, "Sprite", dev_priv->display.wm.spr_latency);
- intel_print_wm_latency(dev_priv, "Cursor", dev_priv->display.wm.cur_latency);
+ intel_print_wm_latency(display, "Primary", dev_priv->display.wm.pri_latency);
+ intel_print_wm_latency(display, "Sprite", dev_priv->display.wm.spr_latency);
+ intel_print_wm_latency(display, "Cursor", dev_priv->display.wm.cur_latency);
}
static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
/*
* On some SNB machines (Thinkpad X220 Tablet at least)
* LP3 usage can cause vblank interrupts to be lost.
@@ -2857,13 +2863,15 @@ static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm,
"LP3 watermarks disabled due to potential for lost interrupts\n");
- intel_print_wm_latency(dev_priv, "Primary", dev_priv->display.wm.pri_latency);
- intel_print_wm_latency(dev_priv, "Sprite", dev_priv->display.wm.spr_latency);
- intel_print_wm_latency(dev_priv, "Cursor", dev_priv->display.wm.cur_latency);
+ intel_print_wm_latency(display, "Primary", dev_priv->display.wm.pri_latency);
+ intel_print_wm_latency(display, "Sprite", dev_priv->display.wm.spr_latency);
+ intel_print_wm_latency(display, "Cursor", dev_priv->display.wm.cur_latency);
}
static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
+
if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
hsw_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency);
else if (DISPLAY_VER(dev_priv) >= 6)
@@ -2879,9 +2887,9 @@ static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
intel_fixup_spr_wm_latency(dev_priv, dev_priv->display.wm.spr_latency);
intel_fixup_cur_wm_latency(dev_priv, dev_priv->display.wm.cur_latency);
- intel_print_wm_latency(dev_priv, "Primary", dev_priv->display.wm.pri_latency);
- intel_print_wm_latency(dev_priv, "Sprite", dev_priv->display.wm.spr_latency);
- intel_print_wm_latency(dev_priv, "Cursor", dev_priv->display.wm.cur_latency);
+ intel_print_wm_latency(display, "Primary", dev_priv->display.wm.pri_latency);
+ intel_print_wm_latency(display, "Sprite", dev_priv->display.wm.spr_latency);
+ intel_print_wm_latency(display, "Cursor", dev_priv->display.wm.cur_latency);
if (DISPLAY_VER(dev_priv) == 6) {
snb_wm_latency_quirk(dev_priv);
@@ -3759,8 +3767,9 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
#undef _FW_WM
#undef _FW_WM_VLV
-static void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)
+static void g4x_wm_get_hw_state(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct g4x_wm_values *wm = &dev_priv->display.wm.g4x;
struct intel_crtc *crtc;
@@ -3852,9 +3861,9 @@ static void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)
str_yes_no(wm->fbc_en));
}
-static void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
+static void g4x_wm_sanitize(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_plane *plane;
struct intel_crtc *crtc;
@@ -3902,8 +3911,9 @@ static void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
mutex_unlock(&dev_priv->display.wm.wm_mutex);
}
-static void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
+static void vlv_wm_get_hw_state(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct vlv_wm_values *wm = &dev_priv->display.wm.vlv;
struct intel_crtc *crtc;
u32 val;
@@ -4002,9 +4012,9 @@ static void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
}
-static void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
+static void vlv_wm_sanitize(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_plane *plane;
struct intel_crtc *crtc;
@@ -4065,8 +4075,9 @@ static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
*/
}
-static void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
+static void ilk_wm_get_hw_state(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct ilk_wm_values *hw = &dev_priv->display.wm.hw;
struct intel_crtc *crtc;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 16fd7c00ba01..16c4e25f958a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1054,7 +1054,7 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
- intel_update_watermarks(dev_priv);
+ intel_update_watermarks(display);
intel_fbc_post_update(state, crtc);
@@ -1258,7 +1258,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
*/
if (!intel_initial_watermarks(state, crtc))
if (new_crtc_state->update_wm_pre)
- intel_update_watermarks(dev_priv);
+ intel_update_watermarks(display);
}
/*
@@ -2072,7 +2072,6 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
struct intel_display *display = to_intel_display(crtc);
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
if (drm_WARN_ON(display->drm, crtc->active))
@@ -2096,7 +2095,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
intel_color_modeset(new_crtc_state);
if (!intel_initial_watermarks(state, crtc))
- intel_update_watermarks(dev_priv);
+ intel_update_watermarks(display);
intel_enable_transcoder(new_crtc_state);
intel_crtc_vblank_on(new_crtc_state);
@@ -2112,7 +2111,6 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(state);
- struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
enum pipe pipe = crtc->pipe;
@@ -2149,7 +2147,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
if (!display->funcs.wm->initial_watermarks)
- intel_update_watermarks(dev_priv);
+ intel_update_watermarks(display);
/* clock the pipe down to 640x480@60 to potentially save power */
if (display->platform.i830)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 3673275f9061..eb6d6f2d0f75 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -80,7 +80,7 @@ struct intel_display_funcs {
/* functions used for watermark calcs for display. */
struct intel_wm_funcs {
/* update_wm is for legacy wm management */
- void (*update_wm)(struct drm_i915_private *dev_priv);
+ void (*update_wm)(struct intel_display *display);
int (*compute_watermarks)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void (*initial_watermarks)(struct intel_atomic_state *state,
@@ -90,8 +90,8 @@ struct intel_wm_funcs {
void (*optimize_watermarks)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int (*compute_global_watermarks)(struct intel_atomic_state *state);
- void (*get_hw_state)(struct drm_i915_private *i915);
- void (*sanitize)(struct drm_i915_private *i915);
+ void (*get_hw_state)(struct intel_display *display);
+ void (*sanitize)(struct intel_display *display);
};
struct intel_audio_state {
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 4c784bb7e14b..8f1f95637e09 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -826,7 +826,6 @@ static const struct drm_info_list intel_display_debugfs_list[] = {
void intel_display_debugfs_register(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
struct drm_minor *minor = display->drm->primary;
debugfs_create_file("i915_fifo_underrun_reset", 0644, minor->debugfs_root,
@@ -844,7 +843,7 @@ void intel_display_debugfs_register(struct intel_display *display)
intel_hpd_debugfs_register(display);
intel_opregion_debugfs_register(display);
intel_psr_debugfs_register(display);
- intel_wm_debugfs_register(i915);
+ intel_wm_debugfs_register(display);
intel_display_debugfs_params(display);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 4edadebad13b..44cf34517a62 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -422,7 +422,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
if (!HAS_DISPLAY(display))
return 0;
- intel_wm_init(i915);
+ intel_wm_init(display);
intel_panel_sanitize_ssc(display);
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 2dc641da0c3b..9e963bce340f 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -155,9 +155,8 @@ static void reset_crtc_encoder_state(struct intel_crtc *crtc)
static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_pmdemand_state *pmdemand_state =
- to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
+ to_intel_pmdemand_state(display->pmdemand.obj.state);
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
enum pipe pipe = crtc->pipe;
@@ -169,7 +168,7 @@ static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
reset_crtc_encoder_state(crtc);
intel_fbc_disable(crtc);
- intel_update_watermarks(i915);
+ intel_update_watermarks(display);
intel_display_power_put_all_in_set(display, &crtc->enabled_power_domains);
@@ -874,7 +873,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
/* TODO move here (or even earlier?) on all platforms */
if (DISPLAY_VER(display) >= 9)
- intel_wm_get_hw_state(i915);
+ intel_wm_get_hw_state(display);
intel_bw_update_hw_state(display);
intel_cdclk_update_hw_state(display);
@@ -988,8 +987,8 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
/* TODO move earlier on all platforms */
if (DISPLAY_VER(display) < 9)
- intel_wm_get_hw_state(i915);
- intel_wm_sanitize(i915);
+ intel_wm_get_hw_state(display);
+ intel_wm_sanitize(display);
for_each_intel_crtc(&i915->drm, crtc) {
struct intel_crtc_state *crtc_state =
diff --git a/drivers/gpu/drm/i915/display/intel_wm.c b/drivers/gpu/drm/i915/display/intel_wm.c
index f00f4cfc58e5..c6aff3ba8e3d 100644
--- a/drivers/gpu/drm/i915/display/intel_wm.c
+++ b/drivers/gpu/drm/i915/display/intel_wm.c
@@ -13,7 +13,7 @@
/**
* intel_update_watermarks - update FIFO watermark values based on current modes
- * @i915: i915 device
+ * @display: display device
*
* Calculate watermark values for the various WM regs based on current mode
* and plane configuration.
@@ -44,10 +44,10 @@
* We don't use the sprite, so we can ignore that. And on Crestline we have
* to set the non-SR watermarks to 8.
*/
-void intel_update_watermarks(struct drm_i915_private *i915)
+void intel_update_watermarks(struct intel_display *display)
{
- if (i915->display.funcs.wm->update_wm)
- i915->display.funcs.wm->update_wm(i915);
+ if (display->funcs.wm->update_wm)
+ display->funcs.wm->update_wm(display);
}
int intel_wm_compute(struct intel_atomic_state *state,
@@ -102,16 +102,16 @@ int intel_compute_global_watermarks(struct intel_atomic_state *state)
return 0;
}
-void intel_wm_get_hw_state(struct drm_i915_private *i915)
+void intel_wm_get_hw_state(struct intel_display *display)
{
- if (i915->display.funcs.wm->get_hw_state)
- return i915->display.funcs.wm->get_hw_state(i915);
+ if (display->funcs.wm->get_hw_state)
+ return display->funcs.wm->get_hw_state(display);
}
-void intel_wm_sanitize(struct drm_i915_private *i915)
+void intel_wm_sanitize(struct intel_display *display)
{
- if (i915->display.funcs.wm->sanitize)
- return i915->display.funcs.wm->sanitize(i915);
+ if (display->funcs.wm->sanitize)
+ return display->funcs.wm->sanitize(display);
}
bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
@@ -137,16 +137,16 @@ bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
return plane_state->uapi.visible;
}
-void intel_print_wm_latency(struct drm_i915_private *dev_priv,
+void intel_print_wm_latency(struct intel_display *display,
const char *name, const u16 wm[])
{
int level;
- for (level = 0; level < dev_priv->display.wm.num_levels; level++) {
+ for (level = 0; level < display->wm.num_levels; level++) {
unsigned int latency = wm[level];
if (latency == 0) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"%s WM%d latency not provided\n",
name, level);
continue;
@@ -156,20 +156,22 @@ void intel_print_wm_latency(struct drm_i915_private *dev_priv,
* - latencies are in us on gen9.
* - before then, WM1+ latency values are in 0.5us units
*/
- if (DISPLAY_VER(dev_priv) >= 9)
+ if (DISPLAY_VER(display) >= 9)
latency *= 10;
else if (level > 0)
latency *= 5;
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"%s WM%d latency %u (%u.%u usec)\n", name, level,
wm[level], latency / 10, latency % 10);
}
}
-void intel_wm_init(struct drm_i915_private *i915)
+void intel_wm_init(struct intel_display *display)
{
- if (DISPLAY_VER(i915) >= 9)
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
+ if (DISPLAY_VER(display) >= 9)
skl_wm_init(i915);
else
i9xx_wm_init(i915);
@@ -385,9 +387,10 @@ static const struct file_operations i915_cur_wm_latency_fops = {
.write = cur_wm_latency_write
};
-void intel_wm_debugfs_register(struct drm_i915_private *i915)
+void intel_wm_debugfs_register(struct intel_display *display)
{
- struct drm_minor *minor = i915->drm.primary;
+ struct drm_i915_private *i915 = to_i915(display->drm);
+ struct drm_minor *minor = display->drm->primary;
debugfs_create_file("i915_pri_wm_latency", 0644, minor->debugfs_root,
i915, &i915_pri_wm_latency_fops);
diff --git a/drivers/gpu/drm/i915/display/intel_wm.h b/drivers/gpu/drm/i915/display/intel_wm.h
index 7d3a447054b3..9ad4e9eae5ca 100644
--- a/drivers/gpu/drm/i915/display/intel_wm.h
+++ b/drivers/gpu/drm/i915/display/intel_wm.h
@@ -8,13 +8,13 @@
#include <linux/types.h>
-struct drm_i915_private;
struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
+struct intel_display;
struct intel_plane_state;
-void intel_update_watermarks(struct drm_i915_private *i915);
+void intel_update_watermarks(struct intel_display *display);
int intel_wm_compute(struct intel_atomic_state *state,
struct intel_crtc *crtc);
bool intel_initial_watermarks(struct intel_atomic_state *state,
@@ -24,13 +24,13 @@ void intel_atomic_update_watermarks(struct intel_atomic_state *state,
void intel_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int intel_compute_global_watermarks(struct intel_atomic_state *state);
-void intel_wm_get_hw_state(struct drm_i915_private *i915);
-void intel_wm_sanitize(struct drm_i915_private *i915);
+void intel_wm_get_hw_state(struct intel_display *display);
+void intel_wm_sanitize(struct intel_display *display);
bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
-void intel_print_wm_latency(struct drm_i915_private *i915,
+void intel_print_wm_latency(struct intel_display *display,
const char *name, const u16 wm[]);
-void intel_wm_init(struct drm_i915_private *i915);
-void intel_wm_debugfs_register(struct drm_i915_private *i915);
+void intel_wm_init(struct intel_display *display);
+void intel_wm_debugfs_register(struct intel_display *display);
#endif /* __INTEL_WM_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 9381aec797c9..9ca86f44f365 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3106,9 +3106,9 @@ static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
}
}
-static void skl_wm_get_hw_state(struct drm_i915_private *i915)
+static void skl_wm_get_hw_state(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
struct intel_dbuf_state *dbuf_state =
to_intel_dbuf_state(i915->display.dbuf.obj.state);
struct intel_crtc *crtc;
@@ -3339,7 +3339,7 @@ static void skl_setup_wm_latency(struct drm_i915_private *i915)
else
skl_read_wm_latency(i915, display->wm.skl_latency);
- intel_print_wm_latency(i915, "Gen9 Plane", display->wm.skl_latency);
+ intel_print_wm_latency(display, "Gen9 Plane", display->wm.skl_latency);
}
static struct intel_global_state *intel_dbuf_duplicate_state(struct intel_global_obj *obj)
@@ -3800,8 +3800,10 @@ static void skl_dbuf_sanitize(struct drm_i915_private *i915)
}
}
-static void skl_wm_sanitize(struct drm_i915_private *i915)
+static void skl_wm_sanitize(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
skl_mbus_sanitize(i915);
skl_dbuf_sanitize(i915);
}
--
2.39.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 2/7] drm/i915/wm: convert intel_wm.c internally to struct intel_display
2025-04-08 13:38 [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display Jani Nikula
2025-04-08 13:38 ` [PATCH v2 1/7] drm/i915/wm: convert intel_wm.h external interfaces " Jani Nikula
@ 2025-04-08 13:38 ` Jani Nikula
2025-04-08 13:38 ` [PATCH v2 3/7] drm/i915/wm: convert skl_watermark.h external interfaces " Jani Nikula
` (9 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2025-04-08 13:38 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Going forward, struct intel_display is the main display device data
pointer. Convert as much as possible of intel_wm.c to struct
intel_display.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_wm.c | 122 ++++++++++++------------
1 file changed, 61 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_wm.c b/drivers/gpu/drm/i915/display/intel_wm.c
index c6aff3ba8e3d..9899e4c3ae96 100644
--- a/drivers/gpu/drm/i915/display/intel_wm.c
+++ b/drivers/gpu/drm/i915/display/intel_wm.c
@@ -64,10 +64,10 @@ int intel_wm_compute(struct intel_atomic_state *state,
bool intel_initial_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
- if (i915->display.funcs.wm->initial_watermarks) {
- i915->display.funcs.wm->initial_watermarks(state, crtc);
+ if (display->funcs.wm->initial_watermarks) {
+ display->funcs.wm->initial_watermarks(state, crtc);
return true;
}
@@ -77,27 +77,27 @@ bool intel_initial_watermarks(struct intel_atomic_state *state,
void intel_atomic_update_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
- if (i915->display.funcs.wm->atomic_update_watermarks)
- i915->display.funcs.wm->atomic_update_watermarks(state, crtc);
+ if (display->funcs.wm->atomic_update_watermarks)
+ display->funcs.wm->atomic_update_watermarks(state, crtc);
}
void intel_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
- if (i915->display.funcs.wm->optimize_watermarks)
- i915->display.funcs.wm->optimize_watermarks(state, crtc);
+ if (display->funcs.wm->optimize_watermarks)
+ display->funcs.wm->optimize_watermarks(state, crtc);
}
int intel_compute_global_watermarks(struct intel_atomic_state *state)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
- if (i915->display.funcs.wm->compute_global_watermarks)
- return i915->display.funcs.wm->compute_global_watermarks(state);
+ if (display->funcs.wm->compute_global_watermarks)
+ return display->funcs.wm->compute_global_watermarks(state);
return 0;
}
@@ -179,22 +179,22 @@ void intel_wm_init(struct intel_display *display)
static void wm_latency_show(struct seq_file *m, const u16 wm[8])
{
- struct drm_i915_private *dev_priv = m->private;
+ struct intel_display *display = m->private;
int level;
- drm_modeset_lock_all(&dev_priv->drm);
+ drm_modeset_lock_all(display->drm);
- for (level = 0; level < dev_priv->display.wm.num_levels; level++) {
+ for (level = 0; level < display->wm.num_levels; level++) {
unsigned int latency = wm[level];
/*
* - WM1+ latency values in 0.5us units
* - latencies are in us on gen9/vlv/chv
*/
- if (DISPLAY_VER(dev_priv) >= 9 ||
- IS_VALLEYVIEW(dev_priv) ||
- IS_CHERRYVIEW(dev_priv) ||
- IS_G4X(dev_priv))
+ if (DISPLAY_VER(display) >= 9 ||
+ display->platform.valleyview ||
+ display->platform.cherryview ||
+ display->platform.g4x)
latency *= 10;
else if (level > 0)
latency *= 5;
@@ -203,18 +203,18 @@ static void wm_latency_show(struct seq_file *m, const u16 wm[8])
level, wm[level], latency / 10, latency % 10);
}
- drm_modeset_unlock_all(&dev_priv->drm);
+ drm_modeset_unlock_all(display->drm);
}
static int pri_wm_latency_show(struct seq_file *m, void *data)
{
- struct drm_i915_private *dev_priv = m->private;
+ struct intel_display *display = m->private;
const u16 *latencies;
- if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->display.wm.skl_latency;
+ if (DISPLAY_VER(display) >= 9)
+ latencies = display->wm.skl_latency;
else
- latencies = dev_priv->display.wm.pri_latency;
+ latencies = display->wm.pri_latency;
wm_latency_show(m, latencies);
@@ -223,13 +223,13 @@ static int pri_wm_latency_show(struct seq_file *m, void *data)
static int spr_wm_latency_show(struct seq_file *m, void *data)
{
- struct drm_i915_private *dev_priv = m->private;
+ struct intel_display *display = m->private;
const u16 *latencies;
- if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->display.wm.skl_latency;
+ if (DISPLAY_VER(display) >= 9)
+ latencies = display->wm.skl_latency;
else
- latencies = dev_priv->display.wm.spr_latency;
+ latencies = display->wm.spr_latency;
wm_latency_show(m, latencies);
@@ -238,13 +238,13 @@ static int spr_wm_latency_show(struct seq_file *m, void *data)
static int cur_wm_latency_show(struct seq_file *m, void *data)
{
- struct drm_i915_private *dev_priv = m->private;
+ struct intel_display *display = m->private;
const u16 *latencies;
- if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->display.wm.skl_latency;
+ if (DISPLAY_VER(display) >= 9)
+ latencies = display->wm.skl_latency;
else
- latencies = dev_priv->display.wm.cur_latency;
+ latencies = display->wm.cur_latency;
wm_latency_show(m, latencies);
@@ -253,39 +253,39 @@ static int cur_wm_latency_show(struct seq_file *m, void *data)
static int pri_wm_latency_open(struct inode *inode, struct file *file)
{
- struct drm_i915_private *dev_priv = inode->i_private;
+ struct intel_display *display = inode->i_private;
- if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
+ if (DISPLAY_VER(display) < 5 && !display->platform.g4x)
return -ENODEV;
- return single_open(file, pri_wm_latency_show, dev_priv);
+ return single_open(file, pri_wm_latency_show, display);
}
static int spr_wm_latency_open(struct inode *inode, struct file *file)
{
- struct drm_i915_private *dev_priv = inode->i_private;
+ struct intel_display *display = inode->i_private;
- if (HAS_GMCH(dev_priv))
+ if (HAS_GMCH(display))
return -ENODEV;
- return single_open(file, spr_wm_latency_show, dev_priv);
+ return single_open(file, spr_wm_latency_show, display);
}
static int cur_wm_latency_open(struct inode *inode, struct file *file)
{
- struct drm_i915_private *dev_priv = inode->i_private;
+ struct intel_display *display = inode->i_private;
- if (HAS_GMCH(dev_priv))
+ if (HAS_GMCH(display))
return -ENODEV;
- return single_open(file, cur_wm_latency_show, dev_priv);
+ return single_open(file, cur_wm_latency_show, display);
}
static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
size_t len, loff_t *offp, u16 wm[8])
{
struct seq_file *m = file->private_data;
- struct drm_i915_private *dev_priv = m->private;
+ struct intel_display *display = m->private;
u16 new[8] = {};
int level;
int ret;
@@ -302,15 +302,15 @@ static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
&new[0], &new[1], &new[2], &new[3],
&new[4], &new[5], &new[6], &new[7]);
- if (ret != dev_priv->display.wm.num_levels)
+ if (ret != display->wm.num_levels)
return -EINVAL;
- drm_modeset_lock_all(&dev_priv->drm);
+ drm_modeset_lock_all(display->drm);
- for (level = 0; level < dev_priv->display.wm.num_levels; level++)
+ for (level = 0; level < display->wm.num_levels; level++)
wm[level] = new[level];
- drm_modeset_unlock_all(&dev_priv->drm);
+ drm_modeset_unlock_all(display->drm);
return len;
}
@@ -319,13 +319,13 @@ static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
size_t len, loff_t *offp)
{
struct seq_file *m = file->private_data;
- struct drm_i915_private *dev_priv = m->private;
+ struct intel_display *display = m->private;
u16 *latencies;
- if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->display.wm.skl_latency;
+ if (DISPLAY_VER(display) >= 9)
+ latencies = display->wm.skl_latency;
else
- latencies = dev_priv->display.wm.pri_latency;
+ latencies = display->wm.pri_latency;
return wm_latency_write(file, ubuf, len, offp, latencies);
}
@@ -334,13 +334,13 @@ static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
size_t len, loff_t *offp)
{
struct seq_file *m = file->private_data;
- struct drm_i915_private *dev_priv = m->private;
+ struct intel_display *display = m->private;
u16 *latencies;
- if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->display.wm.skl_latency;
+ if (DISPLAY_VER(display) >= 9)
+ latencies = display->wm.skl_latency;
else
- latencies = dev_priv->display.wm.spr_latency;
+ latencies = display->wm.spr_latency;
return wm_latency_write(file, ubuf, len, offp, latencies);
}
@@ -349,13 +349,13 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
size_t len, loff_t *offp)
{
struct seq_file *m = file->private_data;
- struct drm_i915_private *dev_priv = m->private;
+ struct intel_display *display = m->private;
u16 *latencies;
- if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->display.wm.skl_latency;
+ if (DISPLAY_VER(display) >= 9)
+ latencies = display->wm.skl_latency;
else
- latencies = dev_priv->display.wm.cur_latency;
+ latencies = display->wm.cur_latency;
return wm_latency_write(file, ubuf, len, offp, latencies);
}
@@ -393,13 +393,13 @@ void intel_wm_debugfs_register(struct intel_display *display)
struct drm_minor *minor = display->drm->primary;
debugfs_create_file("i915_pri_wm_latency", 0644, minor->debugfs_root,
- i915, &i915_pri_wm_latency_fops);
+ display, &i915_pri_wm_latency_fops);
debugfs_create_file("i915_spr_wm_latency", 0644, minor->debugfs_root,
- i915, &i915_spr_wm_latency_fops);
+ display, &i915_spr_wm_latency_fops);
debugfs_create_file("i915_cur_wm_latency", 0644, minor->debugfs_root,
- i915, &i915_cur_wm_latency_fops);
+ display, &i915_cur_wm_latency_fops);
skl_watermark_debugfs_register(i915);
}
--
2.39.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 3/7] drm/i915/wm: convert skl_watermark.h external interfaces to struct intel_display
2025-04-08 13:38 [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display Jani Nikula
2025-04-08 13:38 ` [PATCH v2 1/7] drm/i915/wm: convert intel_wm.h external interfaces " Jani Nikula
2025-04-08 13:38 ` [PATCH v2 2/7] drm/i915/wm: convert intel_wm.c internally " Jani Nikula
@ 2025-04-08 13:38 ` Jani Nikula
2025-04-08 13:38 ` [PATCH v2 4/7] drm/i915/wm: convert skl_watermarks.c internally " Jani Nikula
` (8 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2025-04-08 13:38 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Going forward, struct intel_display is the main display device data
pointer. Convert the skl_watermark.h interface to struct intel_display.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 24 ++--
drivers/gpu/drm/i915/display/intel_cdclk.c | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
.../drm/i915/display/intel_display_driver.c | 8 +-
drivers/gpu/drm/i915/display/intel_dsb.c | 4 +-
drivers/gpu/drm/i915/display/intel_wm.c | 5 +-
drivers/gpu/drm/i915/display/skl_watermark.c | 106 ++++++++++--------
drivers/gpu/drm/i915/display/skl_watermark.h | 23 ++--
drivers/gpu/drm/i915/i915_driver.c | 2 +-
drivers/gpu/drm/xe/display/xe_display.c | 2 +-
10 files changed, 90 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index e819db78dfbd..a5dd2932b852 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -976,7 +976,6 @@ static int mtl_find_qgv_points(struct intel_display *display,
unsigned int num_active_planes,
struct intel_bw_state *new_bw_state)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
unsigned int best_rate = UINT_MAX;
unsigned int num_qgv_points = display->bw.max[0].num_qgv_points;
unsigned int qgv_peak_bw = 0;
@@ -992,7 +991,7 @@ static int mtl_find_qgv_points(struct intel_display *display,
* for qgv peak bw in PM Demand request. So assign UINT_MAX if SAGV is
* not enabled. PM Demand code will clamp the value for the register
*/
- if (!intel_can_enable_sagv(i915, new_bw_state)) {
+ if (!intel_can_enable_sagv(display, new_bw_state)) {
new_bw_state->qgv_point_peakbw = U16_MAX;
drm_dbg_kms(display->drm, "No SAGV, use UINT_MAX as peak bw.");
return 0;
@@ -1049,7 +1048,6 @@ static int icl_find_qgv_points(struct intel_display *display,
const struct intel_bw_state *old_bw_state,
struct intel_bw_state *new_bw_state)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
unsigned int num_psf_gv_points = display->bw.max[0].num_psf_gv_points;
unsigned int num_qgv_points = display->bw.max[0].num_qgv_points;
u16 psf_points = 0;
@@ -1106,7 +1104,7 @@ static int icl_find_qgv_points(struct intel_display *display,
* we can't enable SAGV due to the increased memory latency it may
* cause.
*/
- if (!intel_can_enable_sagv(i915, new_bw_state)) {
+ if (!intel_can_enable_sagv(display, new_bw_state)) {
qgv_points = icl_max_bw_qgv_point_mask(display, num_active_planes);
drm_dbg_kms(display->drm, "No SAGV, using single QGV point mask 0x%x\n",
qgv_points);
@@ -1195,8 +1193,7 @@ static void skl_plane_calc_dbuf_bw(struct intel_dbuf_bw *dbuf_bw,
unsigned int data_rate)
{
struct intel_display *display = to_intel_display(crtc);
- struct drm_i915_private *i915 = to_i915(display->drm);
- unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
+ unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(display, ddb);
enum dbuf_slice slice;
/*
@@ -1446,7 +1443,6 @@ static int intel_bw_modeset_checks(struct intel_atomic_state *state)
static int intel_bw_check_sagv_mask(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
- struct drm_i915_private *i915 = to_i915(display->drm);
const struct intel_crtc_state *old_crtc_state;
const struct intel_crtc_state *new_crtc_state;
const struct intel_bw_state *old_bw_state = NULL;
@@ -1475,8 +1471,8 @@ static int intel_bw_check_sagv_mask(struct intel_atomic_state *state)
if (!new_bw_state)
return 0;
- if (intel_can_enable_sagv(i915, new_bw_state) !=
- intel_can_enable_sagv(i915, old_bw_state)) {
+ if (intel_can_enable_sagv(display, new_bw_state) !=
+ intel_can_enable_sagv(display, old_bw_state)) {
ret = intel_atomic_serialize_global_state(&new_bw_state->base);
if (ret)
return ret;
@@ -1492,13 +1488,12 @@ static int intel_bw_check_sagv_mask(struct intel_atomic_state *state)
int intel_bw_atomic_check(struct intel_atomic_state *state, bool any_ms)
{
struct intel_display *display = to_intel_display(state);
- struct drm_i915_private *i915 = to_i915(display->drm);
bool changed = false;
struct intel_bw_state *new_bw_state;
const struct intel_bw_state *old_bw_state;
int ret;
- if (DISPLAY_VER(i915) < 9)
+ if (DISPLAY_VER(display) < 9)
return 0;
if (any_ms) {
@@ -1523,8 +1518,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state, bool any_ms)
new_bw_state = intel_atomic_get_new_bw_state(state);
if (new_bw_state &&
- intel_can_enable_sagv(i915, old_bw_state) !=
- intel_can_enable_sagv(i915, new_bw_state))
+ intel_can_enable_sagv(display, old_bw_state) !=
+ intel_can_enable_sagv(display, new_bw_state))
changed = true;
/*
@@ -1628,7 +1623,6 @@ static const struct intel_global_state_funcs intel_bw_funcs = {
int intel_bw_init(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
struct intel_bw_state *state;
state = kzalloc(sizeof(*state), GFP_KERNEL);
@@ -1642,7 +1636,7 @@ int intel_bw_init(struct intel_display *display)
* Limit this only if we have SAGV. And for Display version 14 onwards
* sagv is handled though pmdemand requests
*/
- if (intel_has_sagv(i915) && IS_DISPLAY_VER(display, 11, 13))
+ if (intel_has_sagv(display) && IS_DISPLAY_VER(display, 11, 13))
icl_force_disable_sagv(display, state);
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ea2fbee2d62f..6830950aae3f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1972,9 +1972,7 @@ int intel_mdclk_cdclk_ratio(struct intel_display *display,
static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display,
const struct intel_cdclk_config *cdclk_config)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
-
- intel_dbuf_mdclk_cdclk_ratio_update(i915,
+ intel_dbuf_mdclk_cdclk_ratio_update(display,
intel_mdclk_cdclk_ratio(display, cdclk_config),
cdclk_config->joined_mbus);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 16c4e25f958a..745eef470bad 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4162,8 +4162,6 @@ static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct drm_display_mode *pipe_mode =
&crtc_state->hw.pipe_mode;
int linetime_wm;
@@ -4176,7 +4174,7 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
/* Display WA #1135: BXT:ALL GLK:ALL */
if ((display->platform.geminilake || display->platform.broxton) &&
- skl_watermark_ipc_enabled(dev_priv))
+ skl_watermark_ipc_enabled(display))
linetime_wm /= 2;
return min(linetime_wm, 0x1ff);
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 44cf34517a62..f6d5d51dda0f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -252,7 +252,7 @@ int intel_display_driver_probe_noirq(struct intel_display *display)
if (ret)
goto cleanup_vga_client_pw_domain_dmc;
- ret = intel_dbuf_init(i915);
+ ret = intel_dbuf_init(display);
if (ret)
goto cleanup_vga_client_pw_domain_dmc;
@@ -491,7 +491,6 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
/* part #3: call after gem init */
int intel_display_driver_probe(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
int ret;
if (!HAS_DISPLAY(display))
@@ -519,7 +518,7 @@ int intel_display_driver_probe(struct intel_display *display)
/* Only enable hotplug handling once the fbdev is fully set up. */
intel_hpd_init(display);
- skl_watermark_ipc_init(i915);
+ skl_watermark_ipc_init(display);
return 0;
}
@@ -726,7 +725,6 @@ __intel_display_driver_resume(struct intel_display *display,
void intel_display_driver_resume(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
struct drm_atomic_state *state = display->restore.modeset_state;
struct drm_modeset_acquire_ctx ctx;
int ret;
@@ -754,7 +752,7 @@ void intel_display_driver_resume(struct intel_display *display)
if (!ret)
ret = __intel_display_driver_resume(display, state, &ctx);
- skl_watermark_ipc_update(i915);
+ skl_watermark_ipc_update(display);
drm_modeset_drop_locks(&ctx);
drm_modeset_acquire_fini(&ctx);
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 0ddcdedf5453..72fe390c5af2 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -143,10 +143,10 @@ static int dsb_vtotal(struct intel_atomic_state *state,
static int dsb_dewake_scanline_start(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
+ struct intel_display *display = to_intel_display(state);
const struct intel_crtc_state *crtc_state =
intel_pre_commit_crtc_state(state, crtc);
- struct drm_i915_private *i915 = to_i915(state->base.dev);
- unsigned int latency = skl_watermark_max_latency(i915, 0);
+ unsigned int latency = skl_watermark_max_latency(display, 0);
return intel_mode_vdisplay(&crtc_state->hw.adjusted_mode) -
intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, latency);
diff --git a/drivers/gpu/drm/i915/display/intel_wm.c b/drivers/gpu/drm/i915/display/intel_wm.c
index 9899e4c3ae96..43c69a672bb3 100644
--- a/drivers/gpu/drm/i915/display/intel_wm.c
+++ b/drivers/gpu/drm/i915/display/intel_wm.c
@@ -172,7 +172,7 @@ void intel_wm_init(struct intel_display *display)
struct drm_i915_private *i915 = to_i915(display->drm);
if (DISPLAY_VER(display) >= 9)
- skl_wm_init(i915);
+ skl_wm_init(display);
else
i9xx_wm_init(i915);
}
@@ -389,7 +389,6 @@ static const struct file_operations i915_cur_wm_latency_fops = {
void intel_wm_debugfs_register(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
struct drm_minor *minor = display->drm->primary;
debugfs_create_file("i915_pri_wm_latency", 0644, minor->debugfs_root,
@@ -401,5 +400,5 @@ void intel_wm_debugfs_register(struct intel_display *display)
debugfs_create_file("i915_cur_wm_latency", 0644, minor->debugfs_root,
display, &i915_cur_wm_latency_fops);
- skl_watermark_debugfs_register(i915);
+ skl_watermark_debugfs_register(display);
}
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 9ca86f44f365..74df2cae4146 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -76,10 +76,8 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *i915)
}
bool
-intel_has_sagv(struct drm_i915_private *i915)
+intel_has_sagv(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
-
return HAS_SAGV(display) && display->sagv.status != I915_SAGV_NOT_CONTROLLED;
}
@@ -135,7 +133,7 @@ static void intel_sagv_init(struct drm_i915_private *i915)
display->sagv.block_time_us = intel_sagv_block_time(i915);
drm_dbg_kms(display->drm, "SAGV supported: %s, original SAGV block time: %u us\n",
- str_yes_no(intel_has_sagv(i915)), display->sagv.block_time_us);
+ str_yes_no(intel_has_sagv(display)), display->sagv.block_time_us);
/* avoid overflow when adding with wm0 latency/etc. */
if (drm_WARN(display->drm, display->sagv.block_time_us > U16_MAX,
@@ -143,7 +141,7 @@ static void intel_sagv_init(struct drm_i915_private *i915)
display->sagv.block_time_us))
display->sagv.block_time_us = 0;
- if (!intel_has_sagv(i915))
+ if (!intel_has_sagv(display))
display->sagv.block_time_us = 0;
}
@@ -160,9 +158,10 @@ static void intel_sagv_init(struct drm_i915_private *i915)
*/
static void skl_sagv_enable(struct drm_i915_private *i915)
{
+ struct intel_display *display = &i915->display;
int ret;
- if (!intel_has_sagv(i915))
+ if (!intel_has_sagv(display))
return;
if (i915->display.sagv.status == I915_SAGV_ENABLED)
@@ -192,9 +191,10 @@ static void skl_sagv_enable(struct drm_i915_private *i915)
static void skl_sagv_disable(struct drm_i915_private *i915)
{
+ struct intel_display *display = &i915->display;
int ret;
- if (!intel_has_sagv(i915))
+ if (!intel_has_sagv(display))
return;
if (i915->display.sagv.status == I915_SAGV_DISABLED)
@@ -224,6 +224,7 @@ static void skl_sagv_disable(struct drm_i915_private *i915)
static void skl_sagv_pre_plane_update(struct intel_atomic_state *state)
{
+ struct intel_display *display = to_intel_display(state);
struct drm_i915_private *i915 = to_i915(state->base.dev);
const struct intel_bw_state *new_bw_state =
intel_atomic_get_new_bw_state(state);
@@ -231,12 +232,13 @@ static void skl_sagv_pre_plane_update(struct intel_atomic_state *state)
if (!new_bw_state)
return;
- if (!intel_can_enable_sagv(i915, new_bw_state))
+ if (!intel_can_enable_sagv(display, new_bw_state))
skl_sagv_disable(i915);
}
static void skl_sagv_post_plane_update(struct intel_atomic_state *state)
{
+ struct intel_display *display = to_intel_display(state);
struct drm_i915_private *i915 = to_i915(state->base.dev);
const struct intel_bw_state *new_bw_state =
intel_atomic_get_new_bw_state(state);
@@ -244,7 +246,7 @@ static void skl_sagv_post_plane_update(struct intel_atomic_state *state)
if (!new_bw_state)
return;
- if (intel_can_enable_sagv(i915, new_bw_state))
+ if (intel_can_enable_sagv(display, new_bw_state))
skl_sagv_enable(i915);
}
@@ -316,6 +318,7 @@ static void icl_sagv_post_plane_update(struct intel_atomic_state *state)
void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
{
+ struct intel_display *display = to_intel_display(state);
struct drm_i915_private *i915 = to_i915(state->base.dev);
/*
@@ -325,7 +328,7 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
* disabled in a BIOS, we are not even allowed to send a PCode request,
* as it will throw an error. So have to check it here.
*/
- if (!intel_has_sagv(i915))
+ if (!intel_has_sagv(display))
return;
if (DISPLAY_VER(i915) >= 11)
@@ -336,6 +339,7 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
void intel_sagv_post_plane_update(struct intel_atomic_state *state)
{
+ struct intel_display *display = to_intel_display(state);
struct drm_i915_private *i915 = to_i915(state->base.dev);
/*
@@ -345,7 +349,7 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
* disabled in a BIOS, we are not even allowed to send a PCode request,
* as it will throw an error. So have to check it here.
*/
- if (!intel_has_sagv(i915))
+ if (!intel_has_sagv(display))
return;
if (DISPLAY_VER(i915) >= 11)
@@ -356,12 +360,13 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
enum plane_id plane_id;
int max_level = INT_MAX;
- if (!intel_has_sagv(i915))
+ if (!intel_has_sagv(display))
return false;
if (!crtc_state->hw.active)
@@ -448,10 +453,10 @@ bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
return skl_crtc_can_enable_sagv(crtc_state);
}
-bool intel_can_enable_sagv(struct drm_i915_private *i915,
+bool intel_can_enable_sagv(struct intel_display *display,
const struct intel_bw_state *bw_state)
{
- if (DISPLAY_VER(i915) < 11 &&
+ if (DISPLAY_VER(display) < 11 &&
bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
return false;
@@ -506,9 +511,10 @@ static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask
return ddb.start;
}
-u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *i915,
+u32 skl_ddb_dbuf_slice_mask(struct intel_display *display,
const struct skl_ddb_entry *entry)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
int slice_size = intel_dbuf_slice_size(i915);
enum dbuf_slice start_slice, end_slice;
u8 slice_mask = 0;
@@ -674,6 +680,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
static unsigned int skl_wm_latency(struct drm_i915_private *i915, int level,
const struct skl_wm_params *wp)
{
+ struct intel_display *display = &i915->display;
unsigned int latency = i915->display.wm.skl_latency[level];
if (latency == 0)
@@ -684,7 +691,7 @@ static unsigned int skl_wm_latency(struct drm_i915_private *i915, int level,
* Display WA #1141: kbl,cfl
*/
if ((IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) &&
- skl_watermark_ipc_enabled(i915))
+ skl_watermark_ipc_enabled(display))
latency += 4;
if (skl_needs_memory_bw_wa(i915) && wp && wp->x_tiled)
@@ -2050,11 +2057,12 @@ static void skl_compute_transition_wm(struct drm_i915_private *i915,
const struct skl_wm_level *wm0,
const struct skl_wm_params *wp)
{
+ struct intel_display *display = &i915->display;
u16 trans_min, trans_amount, trans_y_tile_min;
u16 wm0_blocks, trans_offset, blocks;
/* Transition WM don't make any sense if ipc is disabled */
- if (!skl_watermark_ipc_enabled(i915))
+ if (!skl_watermark_ipc_enabled(display))
return;
/*
@@ -2939,7 +2947,6 @@ void
intel_program_dpkgc_latency(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
- struct drm_i915_private *i915 = to_i915(display->drm);
struct intel_crtc *crtc;
struct intel_crtc_state *new_crtc_state;
u32 latency = LNL_PKG_C_LATENCY_MASK;
@@ -2965,7 +2972,7 @@ intel_program_dpkgc_latency(struct intel_atomic_state *state)
added_wake_time = DSB_EXE_TIME +
display->sagv.block_time_us;
- latency = skl_watermark_max_latency(i915, 1);
+ latency = skl_watermark_max_latency(display, 1);
/* Wa_22020432604 */
if ((DISPLAY_VER(display) == 20 || DISPLAY_VER(display) == 30) && !latency) {
@@ -3172,7 +3179,7 @@ static void skl_wm_get_hw_state(struct intel_display *display)
/* The slices actually used by the planes on the pipe */
dbuf_state->slices[pipe] =
- skl_ddb_dbuf_slice_mask(i915, &crtc_state->wm.skl.ddb);
+ skl_ddb_dbuf_slice_mask(display, &crtc_state->wm.skl.ddb);
drm_dbg_kms(display->drm,
"[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x, mbus joined: %s\n",
@@ -3185,18 +3192,18 @@ static void skl_wm_get_hw_state(struct intel_display *display)
dbuf_state->enabled_slices = display->dbuf.enabled_slices;
}
-bool skl_watermark_ipc_enabled(struct drm_i915_private *i915)
+bool skl_watermark_ipc_enabled(struct intel_display *display)
{
- return i915->display.wm.ipc_enabled;
+ return display->wm.ipc_enabled;
}
-void skl_watermark_ipc_update(struct drm_i915_private *i915)
+void skl_watermark_ipc_update(struct intel_display *display)
{
- if (!HAS_IPC(i915))
+ if (!HAS_IPC(display))
return;
- intel_de_rmw(i915, DISP_ARB_CTL2, DISP_IPC_ENABLE,
- skl_watermark_ipc_enabled(i915) ? DISP_IPC_ENABLE : 0);
+ intel_de_rmw(display, DISP_ARB_CTL2, DISP_IPC_ENABLE,
+ skl_watermark_ipc_enabled(display) ? DISP_IPC_ENABLE : 0);
}
static bool skl_watermark_ipc_can_enable(struct drm_i915_private *i915)
@@ -3214,14 +3221,16 @@ static bool skl_watermark_ipc_can_enable(struct drm_i915_private *i915)
return true;
}
-void skl_watermark_ipc_init(struct drm_i915_private *i915)
+void skl_watermark_ipc_init(struct intel_display *display)
{
- if (!HAS_IPC(i915))
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
+ if (!HAS_IPC(display))
return;
- i915->display.wm.ipc_enabled = skl_watermark_ipc_can_enable(i915);
+ display->wm.ipc_enabled = skl_watermark_ipc_can_enable(i915);
- skl_watermark_ipc_update(i915);
+ skl_watermark_ipc_update(display);
}
static void
@@ -3377,9 +3386,8 @@ intel_atomic_get_dbuf_state(struct intel_atomic_state *state)
return to_intel_dbuf_state(dbuf_state);
}
-int intel_dbuf_init(struct drm_i915_private *i915)
+int intel_dbuf_init(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
struct intel_dbuf_state *dbuf_state;
dbuf_state = kzalloc(sizeof(*dbuf_state), GFP_KERNEL);
@@ -3501,10 +3509,9 @@ int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
return intel_atomic_lock_global_state(&dbuf_state->base);
}
-void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915,
+void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,
int ratio, bool joined_mbus)
{
- struct intel_display *display = &i915->display;
enum dbuf_slice slice;
if (!HAS_MBUS_JOINING(display))
@@ -3528,7 +3535,7 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915,
static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
const struct intel_dbuf_state *old_dbuf_state =
intel_atomic_get_old_dbuf_state(state);
const struct intel_dbuf_state *new_dbuf_state =
@@ -3543,7 +3550,7 @@ static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state
mdclk_cdclk_ratio = new_dbuf_state->mdclk_cdclk_ratio;
}
- intel_dbuf_mdclk_cdclk_ratio_update(i915, mdclk_cdclk_ratio,
+ intel_dbuf_mdclk_cdclk_ratio_update(display, mdclk_cdclk_ratio,
new_dbuf_state->joined_mbus);
}
@@ -3725,7 +3732,7 @@ static void skl_mbus_sanitize(struct drm_i915_private *i915)
dbuf_state->active_pipes);
dbuf_state->joined_mbus = false;
- intel_dbuf_mdclk_cdclk_ratio_update(i915,
+ intel_dbuf_mdclk_cdclk_ratio_update(display,
dbuf_state->mdclk_cdclk_ratio,
dbuf_state->joined_mbus);
pipe_mbus_dbox_ctl_update(i915, dbuf_state);
@@ -3983,21 +3990,24 @@ static const struct intel_wm_funcs skl_wm_funcs = {
.sanitize = skl_wm_sanitize,
};
-void skl_wm_init(struct drm_i915_private *i915)
+void skl_wm_init(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
intel_sagv_init(i915);
skl_setup_wm_latency(i915);
- i915->display.funcs.wm = &skl_wm_funcs;
+ display->funcs.wm = &skl_wm_funcs;
}
static int skl_watermark_ipc_status_show(struct seq_file *m, void *data)
{
struct drm_i915_private *i915 = m->private;
+ struct intel_display *display = &i915->display;
seq_printf(m, "Isochronous Priority Control: %s\n",
- str_yes_no(skl_watermark_ipc_enabled(i915)));
+ str_yes_no(skl_watermark_ipc_enabled(display)));
return 0;
}
@@ -4023,11 +4033,11 @@ static ssize_t skl_watermark_ipc_status_write(struct file *file,
return ret;
with_intel_display_rpm(display) {
- if (!skl_watermark_ipc_enabled(i915) && enable)
+ if (!skl_watermark_ipc_enabled(display) && enable)
drm_info(display->drm,
"Enabling IPC: WM will be proper only after next commit\n");
display->wm.ipc_enabled = enable;
- skl_watermark_ipc_update(i915);
+ skl_watermark_ipc_update(display);
}
return len;
@@ -4045,6 +4055,7 @@ static const struct file_operations skl_watermark_ipc_status_fops = {
static int intel_sagv_status_show(struct seq_file *m, void *unused)
{
struct drm_i915_private *i915 = m->private;
+ struct intel_display *display = &i915->display;
static const char * const sagv_status[] = {
[I915_SAGV_UNKNOWN] = "unknown",
[I915_SAGV_DISABLED] = "disabled",
@@ -4052,7 +4063,7 @@ static int intel_sagv_status_show(struct seq_file *m, void *unused)
[I915_SAGV_NOT_CONTROLLED] = "not controlled",
};
- seq_printf(m, "SAGV available: %s\n", str_yes_no(intel_has_sagv(i915)));
+ seq_printf(m, "SAGV available: %s\n", str_yes_no(intel_has_sagv(display)));
seq_printf(m, "SAGV modparam: %s\n",
str_enabled_disabled(i915->display.params.enable_sagv));
seq_printf(m, "SAGV status: %s\n", sagv_status[i915->display.sagv.status]);
@@ -4063,9 +4074,9 @@ static int intel_sagv_status_show(struct seq_file *m, void *unused)
DEFINE_SHOW_ATTRIBUTE(intel_sagv_status);
-void skl_watermark_debugfs_register(struct drm_i915_private *i915)
+void skl_watermark_debugfs_register(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
struct drm_minor *minor = display->drm->primary;
if (HAS_IPC(display))
@@ -4077,11 +4088,12 @@ void skl_watermark_debugfs_register(struct drm_i915_private *i915)
&intel_sagv_status_fops);
}
-unsigned int skl_watermark_max_latency(struct drm_i915_private *i915, int initial_wm_level)
+unsigned int skl_watermark_max_latency(struct intel_display *display, int initial_wm_level)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
int level;
- for (level = i915->display.wm.num_levels - 1; level >= initial_wm_level; level--) {
+ for (level = display->wm.num_levels - 1; level >= initial_wm_level; level--) {
unsigned int latency = skl_wm_latency(i915, level, NULL);
if (latency)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index 7e8107f808b6..95b0b599d5c3 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -12,7 +12,6 @@
#include "intel_global_state.h"
#include "intel_wm_types.h"
-struct drm_i915_private;
struct intel_atomic_state;
struct intel_bw_state;
struct intel_crtc;
@@ -28,11 +27,11 @@ u8 intel_enabled_dbuf_slices_mask(struct intel_display *display);
void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
void intel_sagv_post_plane_update(struct intel_atomic_state *state);
bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
-bool intel_can_enable_sagv(struct drm_i915_private *i915,
+bool intel_can_enable_sagv(struct intel_display *display,
const struct intel_bw_state *bw_state);
-bool intel_has_sagv(struct drm_i915_private *i915);
+bool intel_has_sagv(struct intel_display *display);
-u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *i915,
+u32 skl_ddb_dbuf_slice_mask(struct intel_display *display,
const struct skl_ddb_entry *entry);
bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
@@ -46,14 +45,14 @@ void skl_wm_crtc_disable_noatomic(struct intel_crtc *crtc);
void skl_wm_plane_disable_noatomic(struct intel_crtc *crtc,
struct intel_plane *plane);
-void skl_watermark_ipc_init(struct drm_i915_private *i915);
-void skl_watermark_ipc_update(struct drm_i915_private *i915);
-bool skl_watermark_ipc_enabled(struct drm_i915_private *i915);
-void skl_watermark_debugfs_register(struct drm_i915_private *i915);
+void skl_watermark_ipc_init(struct intel_display *display);
+void skl_watermark_ipc_update(struct intel_display *display);
+bool skl_watermark_ipc_enabled(struct intel_display *display);
+void skl_watermark_debugfs_register(struct intel_display *display);
-unsigned int skl_watermark_max_latency(struct drm_i915_private *i915,
+unsigned int skl_watermark_max_latency(struct intel_display *display,
int initial_wm_level);
-void skl_wm_init(struct drm_i915_private *i915);
+void skl_wm_init(struct intel_display *display);
const struct skl_wm_level *skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
enum plane_id plane_id,
@@ -87,13 +86,13 @@ intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
#define intel_atomic_get_new_dbuf_state(state) \
to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_intel_display(state)->dbuf.obj))
-int intel_dbuf_init(struct drm_i915_private *i915);
+int intel_dbuf_init(struct intel_display *display);
int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
int ratio);
void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
-void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915,
+void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,
int ratio, bool joined_mbus);
void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state);
void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index d78de7f620dd..f5262b8ad237 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1647,7 +1647,7 @@ static int intel_runtime_resume(struct device *kdev)
intel_hpd_poll_disable(display);
}
- skl_watermark_ipc_update(dev_priv);
+ skl_watermark_ipc_update(display);
enable_rpm_wakeref_asserts(rpm);
diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index 23937ed3b33d..20c3bcd953b7 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -522,7 +522,7 @@ void xe_display_pm_runtime_resume(struct xe_device *xe)
intel_hpd_init(display);
intel_hpd_poll_disable(display);
- skl_watermark_ipc_update(xe);
+ skl_watermark_ipc_update(display);
}
--
2.39.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 4/7] drm/i915/wm: convert skl_watermarks.c internally to struct intel_display
2025-04-08 13:38 [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display Jani Nikula
` (2 preceding siblings ...)
2025-04-08 13:38 ` [PATCH v2 3/7] drm/i915/wm: convert skl_watermark.h external interfaces " Jani Nikula
@ 2025-04-08 13:38 ` Jani Nikula
2025-04-08 13:38 ` [PATCH v2 5/7] drm/i915/wm: convert i9xx_wm.h external interfaces " Jani Nikula
` (7 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2025-04-08 13:38 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Going forward, struct intel_display is the main display device data
pointer. Convert as much as possible of skl_watermarks.c to struct
intel_display.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/skl_watermark.c | 536 +++++++++----------
1 file changed, 250 insertions(+), 286 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 74df2cae4146..8080f777910a 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -35,7 +35,7 @@
*/
#define DSB_EXE_TIME 100
-static void skl_sagv_disable(struct drm_i915_private *i915);
+static void skl_sagv_disable(struct intel_display *display);
/* Stores plane specific WM parameters */
struct skl_wm_params {
@@ -70,9 +70,9 @@ u8 intel_enabled_dbuf_slices_mask(struct intel_display *display)
* FIXME: We still don't have the proper code detect if we need to apply the WA,
* so assume we'll always need it in order to avoid underruns.
*/
-static bool skl_needs_memory_bw_wa(struct drm_i915_private *i915)
+static bool skl_needs_memory_bw_wa(struct intel_display *display)
{
- return DISPLAY_VER(i915) == 9;
+ return DISPLAY_VER(display) == 9;
}
bool
@@ -82,9 +82,9 @@ intel_has_sagv(struct intel_display *display)
}
static u32
-intel_sagv_block_time(struct drm_i915_private *i915)
+intel_sagv_block_time(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
if (DISPLAY_VER(display) >= 14) {
u32 val;
@@ -114,10 +114,8 @@ intel_sagv_block_time(struct drm_i915_private *i915)
}
}
-static void intel_sagv_init(struct drm_i915_private *i915)
+static void intel_sagv_init(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
-
if (!HAS_SAGV(display))
display->sagv.status = I915_SAGV_NOT_CONTROLLED;
@@ -126,11 +124,11 @@ static void intel_sagv_init(struct drm_i915_private *i915)
* For icl+ this was already determined by intel_bw_init_hw().
*/
if (DISPLAY_VER(display) < 11)
- skl_sagv_disable(i915);
+ skl_sagv_disable(display);
drm_WARN_ON(display->drm, display->sagv.status == I915_SAGV_UNKNOWN);
- display->sagv.block_time_us = intel_sagv_block_time(i915);
+ display->sagv.block_time_us = intel_sagv_block_time(display);
drm_dbg_kms(display->drm, "SAGV supported: %s, original SAGV block time: %u us\n",
str_yes_no(intel_has_sagv(display)), display->sagv.block_time_us);
@@ -156,18 +154,18 @@ static void intel_sagv_init(struct drm_i915_private *i915)
* - All planes can enable watermarks for latencies >= SAGV engine block time
* - We're not using an interlaced display configuration
*/
-static void skl_sagv_enable(struct drm_i915_private *i915)
+static void skl_sagv_enable(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
int ret;
if (!intel_has_sagv(display))
return;
- if (i915->display.sagv.status == I915_SAGV_ENABLED)
+ if (display->sagv.status == I915_SAGV_ENABLED)
return;
- drm_dbg_kms(&i915->drm, "Enabling SAGV\n");
+ drm_dbg_kms(display->drm, "Enabling SAGV\n");
ret = snb_pcode_write(&i915->uncore, GEN9_PCODE_SAGV_CONTROL,
GEN9_SAGV_ENABLE);
@@ -177,30 +175,30 @@ static void skl_sagv_enable(struct drm_i915_private *i915)
* Some skl systems, pre-release machines in particular,
* don't actually have SAGV.
*/
- if (IS_SKYLAKE(i915) && ret == -ENXIO) {
- drm_dbg(&i915->drm, "No SAGV found on system, ignoring\n");
- i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
+ if (display->platform.skylake && ret == -ENXIO) {
+ drm_dbg(display->drm, "No SAGV found on system, ignoring\n");
+ display->sagv.status = I915_SAGV_NOT_CONTROLLED;
return;
} else if (ret < 0) {
- drm_err(&i915->drm, "Failed to enable SAGV\n");
+ drm_err(display->drm, "Failed to enable SAGV\n");
return;
}
- i915->display.sagv.status = I915_SAGV_ENABLED;
+ display->sagv.status = I915_SAGV_ENABLED;
}
-static void skl_sagv_disable(struct drm_i915_private *i915)
+static void skl_sagv_disable(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
int ret;
if (!intel_has_sagv(display))
return;
- if (i915->display.sagv.status == I915_SAGV_DISABLED)
+ if (display->sagv.status == I915_SAGV_DISABLED)
return;
- drm_dbg_kms(&i915->drm, "Disabling SAGV\n");
+ drm_dbg_kms(display->drm, "Disabling SAGV\n");
/* bspec says to keep retrying for at least 1 ms */
ret = skl_pcode_request(&i915->uncore, GEN9_PCODE_SAGV_CONTROL,
GEN9_SAGV_DISABLE,
@@ -210,22 +208,21 @@ static void skl_sagv_disable(struct drm_i915_private *i915)
* Some skl systems, pre-release machines in particular,
* don't actually have SAGV.
*/
- if (IS_SKYLAKE(i915) && ret == -ENXIO) {
- drm_dbg(&i915->drm, "No SAGV found on system, ignoring\n");
- i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
+ if (display->platform.skylake && ret == -ENXIO) {
+ drm_dbg(display->drm, "No SAGV found on system, ignoring\n");
+ display->sagv.status = I915_SAGV_NOT_CONTROLLED;
return;
} else if (ret < 0) {
- drm_err(&i915->drm, "Failed to disable SAGV (%d)\n", ret);
+ drm_err(display->drm, "Failed to disable SAGV (%d)\n", ret);
return;
}
- i915->display.sagv.status = I915_SAGV_DISABLED;
+ display->sagv.status = I915_SAGV_DISABLED;
}
static void skl_sagv_pre_plane_update(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
- struct drm_i915_private *i915 = to_i915(state->base.dev);
const struct intel_bw_state *new_bw_state =
intel_atomic_get_new_bw_state(state);
@@ -233,13 +230,12 @@ static void skl_sagv_pre_plane_update(struct intel_atomic_state *state)
return;
if (!intel_can_enable_sagv(display, new_bw_state))
- skl_sagv_disable(i915);
+ skl_sagv_disable(display);
}
static void skl_sagv_post_plane_update(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
- struct drm_i915_private *i915 = to_i915(state->base.dev);
const struct intel_bw_state *new_bw_state =
intel_atomic_get_new_bw_state(state);
@@ -247,13 +243,12 @@ static void skl_sagv_post_plane_update(struct intel_atomic_state *state)
return;
if (intel_can_enable_sagv(display, new_bw_state))
- skl_sagv_enable(i915);
+ skl_sagv_enable(display);
}
static void icl_sagv_pre_plane_update(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
- struct drm_i915_private *i915 = to_i915(display->drm);
const struct intel_bw_state *old_bw_state =
intel_atomic_get_old_bw_state(state);
const struct intel_bw_state *new_bw_state =
@@ -271,7 +266,7 @@ static void icl_sagv_pre_plane_update(struct intel_atomic_state *state)
WARN_ON(!new_bw_state->base.changed);
- drm_dbg_kms(&i915->drm, "Restricting QGV points: 0x%x -> 0x%x\n",
+ drm_dbg_kms(display->drm, "Restricting QGV points: 0x%x -> 0x%x\n",
old_mask, new_mask);
/*
@@ -286,7 +281,6 @@ static void icl_sagv_pre_plane_update(struct intel_atomic_state *state)
static void icl_sagv_post_plane_update(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
- struct drm_i915_private *i915 = to_i915(display->drm);
const struct intel_bw_state *old_bw_state =
intel_atomic_get_old_bw_state(state);
const struct intel_bw_state *new_bw_state =
@@ -304,7 +298,7 @@ static void icl_sagv_post_plane_update(struct intel_atomic_state *state)
WARN_ON(!new_bw_state->base.changed);
- drm_dbg_kms(&i915->drm, "Relaxing QGV points: 0x%x -> 0x%x\n",
+ drm_dbg_kms(display->drm, "Relaxing QGV points: 0x%x -> 0x%x\n",
old_mask, new_mask);
/*
@@ -319,7 +313,6 @@ static void icl_sagv_post_plane_update(struct intel_atomic_state *state)
void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
- struct drm_i915_private *i915 = to_i915(state->base.dev);
/*
* Just return if we can't control SAGV or don't have it.
@@ -331,7 +324,7 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
if (!intel_has_sagv(display))
return;
- if (DISPLAY_VER(i915) >= 11)
+ if (DISPLAY_VER(display) >= 11)
icl_sagv_pre_plane_update(state);
else
skl_sagv_pre_plane_update(state);
@@ -340,7 +333,6 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
void intel_sagv_post_plane_update(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
- struct drm_i915_private *i915 = to_i915(state->base.dev);
/*
* Just return if we can't control SAGV or don't have it.
@@ -352,7 +344,7 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
if (!intel_has_sagv(display))
return;
- if (DISPLAY_VER(i915) >= 11)
+ if (DISPLAY_VER(display) >= 11)
icl_sagv_post_plane_update(state);
else
skl_sagv_post_plane_update(state);
@@ -362,7 +354,6 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
enum plane_id plane_id;
int max_level = INT_MAX;
@@ -385,7 +376,7 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
continue;
/* Find the highest enabled wm level for this plane */
- for (level = i915->display.wm.num_levels - 1;
+ for (level = display->wm.num_levels - 1;
!wm->wm[level].enable; --level)
{ }
@@ -433,10 +424,9 @@ static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc_state);
- if (!i915->display.params.enable_sagv)
+ if (!display->params.enable_sagv)
return false;
/*
@@ -447,7 +437,7 @@ bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
if (crtc_state->inherited)
return false;
- if (DISPLAY_VER(i915) >= 12)
+ if (DISPLAY_VER(display) >= 12)
return tgl_crtc_can_enable_sagv(crtc_state);
else
return skl_crtc_can_enable_sagv(crtc_state);
@@ -472,17 +462,17 @@ static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry,
return end;
}
-static int intel_dbuf_slice_size(struct drm_i915_private *i915)
+static int intel_dbuf_slice_size(struct intel_display *display)
{
- return DISPLAY_INFO(i915)->dbuf.size /
- hweight8(DISPLAY_INFO(i915)->dbuf.slice_mask);
+ return DISPLAY_INFO(display)->dbuf.size /
+ hweight8(DISPLAY_INFO(display)->dbuf.slice_mask);
}
static void
-skl_ddb_entry_for_slices(struct drm_i915_private *i915, u8 slice_mask,
+skl_ddb_entry_for_slices(struct intel_display *display, u8 slice_mask,
struct skl_ddb_entry *ddb)
{
- int slice_size = intel_dbuf_slice_size(i915);
+ int slice_size = intel_dbuf_slice_size(display);
if (!slice_mask) {
ddb->start = 0;
@@ -494,10 +484,10 @@ skl_ddb_entry_for_slices(struct drm_i915_private *i915, u8 slice_mask,
ddb->end = fls(slice_mask) * slice_size;
WARN_ON(ddb->start >= ddb->end);
- WARN_ON(ddb->end > DISPLAY_INFO(i915)->dbuf.size);
+ WARN_ON(ddb->end > DISPLAY_INFO(display)->dbuf.size);
}
-static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask)
+static unsigned int mbus_ddb_offset(struct intel_display *display, u8 slice_mask)
{
struct skl_ddb_entry ddb;
@@ -506,7 +496,7 @@ static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask
else if (slice_mask & (BIT(DBUF_S3) | BIT(DBUF_S4)))
slice_mask = BIT(DBUF_S3);
- skl_ddb_entry_for_slices(i915, slice_mask, &ddb);
+ skl_ddb_entry_for_slices(display, slice_mask, &ddb);
return ddb.start;
}
@@ -514,8 +504,7 @@ static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask
u32 skl_ddb_dbuf_slice_mask(struct intel_display *display,
const struct skl_ddb_entry *entry)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
- int slice_size = intel_dbuf_slice_size(i915);
+ int slice_size = intel_dbuf_slice_size(display);
enum dbuf_slice start_slice, end_slice;
u8 slice_mask = 0;
@@ -561,15 +550,14 @@ static void intel_crtc_dbuf_weights(const struct intel_dbuf_state *dbuf_state,
unsigned int *weight_end,
unsigned int *weight_total)
{
- struct drm_i915_private *i915 =
- to_i915(dbuf_state->base.state->base.dev);
+ struct intel_display *display = to_intel_display(dbuf_state->base.state->base.dev);
enum pipe pipe;
*weight_start = 0;
*weight_end = 0;
*weight_total = 0;
- for_each_pipe(i915, pipe) {
+ for_each_pipe(display, pipe) {
int weight = dbuf_state->weight[pipe];
/*
@@ -595,7 +583,7 @@ static void intel_crtc_dbuf_weights(const struct intel_dbuf_state *dbuf_state,
static int
skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
unsigned int weight_total, weight_start, weight_end;
const struct intel_dbuf_state *old_dbuf_state =
intel_atomic_get_old_dbuf_state(state);
@@ -617,8 +605,8 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
dbuf_slice_mask = new_dbuf_state->slices[pipe];
- skl_ddb_entry_for_slices(i915, dbuf_slice_mask, &ddb_slices);
- mbus_offset = mbus_ddb_offset(i915, dbuf_slice_mask);
+ skl_ddb_entry_for_slices(display, dbuf_slice_mask, &ddb_slices);
+ mbus_offset = mbus_ddb_offset(display, dbuf_slice_mask);
ddb_range_size = skl_ddb_entry_size(&ddb_slices);
intel_crtc_dbuf_weights(new_dbuf_state, pipe,
@@ -652,7 +640,7 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start;
crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end;
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"[CRTC:%d:%s] dbuf slices 0x%x -> 0x%x, ddb (%d - %d) -> (%d - %d), active pipes 0x%x -> 0x%x\n",
crtc->base.base.id, crtc->base.name,
old_dbuf_state->slices[pipe], new_dbuf_state->slices[pipe],
@@ -677,11 +665,10 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */);
-static unsigned int skl_wm_latency(struct drm_i915_private *i915, int level,
+static unsigned int skl_wm_latency(struct intel_display *display, int level,
const struct skl_wm_params *wp)
{
- struct intel_display *display = &i915->display;
- unsigned int latency = i915->display.wm.skl_latency[level];
+ unsigned int latency = display->wm.skl_latency[level];
if (latency == 0)
return 0;
@@ -690,11 +677,11 @@ static unsigned int skl_wm_latency(struct drm_i915_private *i915, int level,
* WaIncreaseLatencyIPCEnabled: kbl,cfl
* Display WA #1141: kbl,cfl
*/
- if ((IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) &&
- skl_watermark_ipc_enabled(display))
+ if ((display->platform.kabylake || display->platform.coffeelake ||
+ display->platform.cometlake) && skl_watermark_ipc_enabled(display))
latency += 4;
- if (skl_needs_memory_bw_wa(i915) && wp && wp->x_tiled)
+ if (skl_needs_memory_bw_wa(display) && wp && wp->x_tiled)
latency += 15;
return latency;
@@ -704,8 +691,8 @@ static unsigned int
skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
int num_active)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_plane *plane = to_intel_plane(crtc_state->uapi.crtc->cursor);
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
struct skl_wm_level wm = {};
int ret, min_ddb_alloc = 0;
struct skl_wm_params wp;
@@ -716,10 +703,10 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
DRM_FORMAT_MOD_LINEAR,
DRM_MODE_ROTATE_0,
crtc_state->pixel_rate, &wp, 0, 0);
- drm_WARN_ON(&i915->drm, ret);
+ drm_WARN_ON(display->drm, ret);
- for (level = 0; level < i915->display.wm.num_levels; level++) {
- unsigned int latency = skl_wm_latency(i915, level, &wp);
+ for (level = 0; level < display->wm.num_levels; level++) {
+ unsigned int latency = skl_wm_latency(display, level, &wp);
skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm);
if (wm.min_ddb_alloc == U16_MAX)
@@ -741,14 +728,13 @@ static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
}
static void
-skl_ddb_get_hw_plane_state(struct drm_i915_private *i915,
+skl_ddb_get_hw_plane_state(struct intel_display *display,
const enum pipe pipe,
const enum plane_id plane_id,
struct skl_ddb_entry *ddb,
struct skl_ddb_entry *ddb_y,
u16 *min_ddb, u16 *interim_ddb)
{
- struct intel_display *display = &i915->display;
u32 val;
/* Cursor doesn't support NV12/planar, so no extra calculation needed */
@@ -781,7 +767,6 @@ static void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
u16 *min_ddb, u16 *interim_ddb)
{
struct intel_display *display = to_intel_display(crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
enum intel_display_power_domain power_domain;
enum pipe pipe = crtc->pipe;
intel_wakeref_t wakeref;
@@ -793,7 +778,7 @@ static void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
return;
for_each_plane_id_on_crtc(crtc, plane_id)
- skl_ddb_get_hw_plane_state(i915, pipe,
+ skl_ddb_get_hw_plane_state(display, pipe,
plane_id,
&ddb[plane_id],
&ddb_y[plane_id],
@@ -1311,16 +1296,16 @@ static u8 dg2_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbu
static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes, bool join_mbus)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
enum pipe pipe = crtc->pipe;
- if (IS_DG2(i915))
+ if (display->platform.dg2)
return dg2_compute_dbuf_slices(pipe, active_pipes, join_mbus);
- else if (DISPLAY_VER(i915) >= 13)
+ else if (DISPLAY_VER(display) >= 13)
return adlp_compute_dbuf_slices(pipe, active_pipes, join_mbus);
- else if (DISPLAY_VER(i915) == 12)
+ else if (DISPLAY_VER(display) == 12)
return tgl_compute_dbuf_slices(pipe, active_pipes, join_mbus);
- else if (DISPLAY_VER(i915) == 11)
+ else if (DISPLAY_VER(display) == 11)
return icl_compute_dbuf_slices(pipe, active_pipes, join_mbus);
/*
* For anything else just return one slice yet.
@@ -1360,8 +1345,8 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
static u64
skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
enum plane_id plane_id;
u64 data_rate = 0;
@@ -1371,7 +1356,7 @@ skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state)
data_rate += crtc_state->rel_data_rate[plane_id];
- if (DISPLAY_VER(i915) < 11)
+ if (DISPLAY_VER(display) < 11)
data_rate += crtc_state->rel_data_rate_y[plane_id];
}
@@ -1433,7 +1418,7 @@ skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
}
}
-static bool skl_need_wm_copy_wa(struct drm_i915_private *i915, int level,
+static bool skl_need_wm_copy_wa(struct intel_display *display, int level,
const struct skl_plane_wm *wm)
{
/*
@@ -1487,7 +1472,6 @@ static int
skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_dbuf_state *dbuf_state =
@@ -1529,7 +1513,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
* Find the highest watermark level for which we can satisfy the block
* requirement of active planes.
*/
- for (level = i915->display.wm.num_levels - 1; level >= 0; level--) {
+ for (level = display->wm.num_levels - 1; level >= 0; level--) {
blocks = 0;
for_each_plane_id_on_crtc(crtc, plane_id) {
const struct skl_plane_wm *wm =
@@ -1540,7 +1524,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
&crtc_state->wm.skl.plane_ddb[plane_id];
if (wm->wm[level].min_ddb_alloc > skl_ddb_entry_size(ddb)) {
- drm_WARN_ON(&i915->drm,
+ drm_WARN_ON(display->drm,
wm->wm[level].min_ddb_alloc != U16_MAX);
blocks = U32_MAX;
break;
@@ -1559,9 +1543,9 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
}
if (level < 0) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Requested display configuration exceeds system DDB limitations");
- drm_dbg_kms(&i915->drm, "minimum required %d/%d\n",
+ drm_dbg_kms(display->drm, "minimum required %d/%d\n",
blocks, iter.size);
return -EINVAL;
}
@@ -1589,7 +1573,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
if (plane_id == PLANE_CURSOR)
continue;
- if (DISPLAY_VER(i915) < 11 &&
+ if (DISPLAY_VER(display) < 11 &&
crtc_state->nv12_planes & BIT(plane_id)) {
skl_allocate_plane_ddb(&iter, ddb_y, &wm->wm[level],
crtc_state->rel_data_rate_y[plane_id]);
@@ -1605,7 +1589,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
*interim_ddb = wm->sagv.wm0.min_ddb_alloc;
}
}
- drm_WARN_ON(&i915->drm, iter.size != 0 || iter.data_rate != 0);
+ drm_WARN_ON(display->drm, iter.size != 0 || iter.data_rate != 0);
/*
* When we calculated watermark values we didn't know how high
@@ -1613,7 +1597,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
* all levels as "enabled." Go back now and disable the ones
* that aren't actually possible.
*/
- for (level++; level < i915->display.wm.num_levels; level++) {
+ for (level++; level < display->wm.num_levels; level++) {
for_each_plane_id_on_crtc(crtc, plane_id) {
const struct skl_ddb_entry *ddb =
&crtc_state->wm.skl.plane_ddb[plane_id];
@@ -1622,7 +1606,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
- if (DISPLAY_VER(i915) < 11 &&
+ if (DISPLAY_VER(display) < 11 &&
crtc_state->nv12_planes & BIT(plane_id))
skl_check_nv12_wm_level(&wm->wm[level],
&wm->uv_wm[level],
@@ -1630,7 +1614,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
else
skl_check_wm_level(&wm->wm[level], ddb);
- if (skl_need_wm_copy_wa(i915, level, wm)) {
+ if (skl_need_wm_copy_wa(display, level, wm)) {
wm->wm[level].blocks = wm->wm[level - 1].blocks;
wm->wm[level].lines = wm->wm[level - 1].lines;
wm->wm[level].ignore_lines = wm->wm[level - 1].ignore_lines;
@@ -1652,7 +1636,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
- if (DISPLAY_VER(i915) < 11 &&
+ if (DISPLAY_VER(display) < 11 &&
crtc_state->nv12_planes & BIT(plane_id)) {
skl_check_wm_level(&wm->trans_wm, ddb_y);
} else {
@@ -1678,7 +1662,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
* 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
*/
static uint_fixed_16_16_t
-skl_wm_method1(const struct drm_i915_private *i915, u32 pixel_rate,
+skl_wm_method1(struct intel_display *display, u32 pixel_rate,
u8 cpp, u32 latency, u32 dbuf_block_size)
{
u32 wm_intermediate_val;
@@ -1690,7 +1674,7 @@ skl_wm_method1(const struct drm_i915_private *i915, u32 pixel_rate,
wm_intermediate_val = latency * pixel_rate * cpp;
ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
- if (DISPLAY_VER(i915) >= 10)
+ if (DISPLAY_VER(display) >= 10)
ret = add_fixed16_u32(ret, 1);
return ret;
@@ -1716,7 +1700,7 @@ skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
static uint_fixed_16_16_t
intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
u32 pixel_rate;
u32 crtc_htotal;
uint_fixed_16_16_t linetime_us;
@@ -1726,7 +1710,7 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
pixel_rate = crtc_state->pixel_rate;
- if (drm_WARN_ON(&i915->drm, pixel_rate == 0))
+ if (drm_WARN_ON(display->drm, pixel_rate == 0))
return u32_to_fixed16(0);
crtc_htotal = crtc_state->hw.pipe_mode.crtc_htotal;
@@ -1742,15 +1726,13 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
u32 plane_pixel_rate, struct skl_wm_params *wp,
int color_plane, unsigned int pan_x)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_display *display = to_intel_display(crtc_state);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
u32 interm_pbpl;
/* only planar format has two planes */
if (color_plane == 1 &&
!intel_format_info_is_yuv_semiplanar(format, modifier)) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Non planar format have single plane\n");
return -EINVAL;
}
@@ -1768,7 +1750,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
wp->cpp = format->cpp[color_plane];
wp->plane_pixel_rate = plane_pixel_rate;
- if (DISPLAY_VER(i915) >= 11 &&
+ if (DISPLAY_VER(display) >= 11 &&
modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 1)
wp->dbuf_block_size = 256;
else
@@ -1793,7 +1775,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
wp->y_min_scanlines = 4;
}
- if (skl_needs_memory_bw_wa(i915))
+ if (skl_needs_memory_bw_wa(display))
wp->y_min_scanlines *= 2;
wp->plane_bytes_per_line = wp->width * wp->cpp;
@@ -1804,7 +1786,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
if (DISPLAY_VER(display) >= 30)
interm_pbpl += (pan_x != 0);
- else if (DISPLAY_VER(i915) >= 10)
+ else if (DISPLAY_VER(display) >= 10)
interm_pbpl++;
wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
@@ -1813,7 +1795,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
wp->dbuf_block_size);
- if (!wp->x_tiled || DISPLAY_VER(i915) >= 10)
+ if (!wp->x_tiled || DISPLAY_VER(display) >= 10)
interm_pbpl++;
wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
@@ -1850,18 +1832,18 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
plane_state->uapi.src.x1);
}
-static bool skl_wm_has_lines(struct drm_i915_private *i915, int level)
+static bool skl_wm_has_lines(struct intel_display *display, int level)
{
- if (DISPLAY_VER(i915) >= 10)
+ if (DISPLAY_VER(display) >= 10)
return true;
/* The number of lines are ignored for the level 0 watermark. */
return level > 0;
}
-static int skl_wm_max_lines(struct drm_i915_private *i915)
+static int skl_wm_max_lines(struct intel_display *display)
{
- if (DISPLAY_VER(i915) >= 13)
+ if (DISPLAY_VER(display) >= 13)
return 255;
else
return 31;
@@ -1882,7 +1864,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
uint_fixed_16_16_t method1, method2;
uint_fixed_16_16_t selected_result;
u32 blocks, lines, min_ddb_alloc = 0;
@@ -1894,7 +1876,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
return;
}
- method1 = skl_wm_method1(i915, wp->plane_pixel_rate,
+ method1 = skl_wm_method1(display, wp->plane_pixel_rate,
wp->cpp, latency, wp->dbuf_block_size);
method2 = skl_wm_method2(wp->plane_pixel_rate,
crtc_state->hw.pipe_mode.crtc_htotal,
@@ -1909,7 +1891,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
(wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
selected_result = method2;
} else if (latency >= wp->linetime_us) {
- if (DISPLAY_VER(i915) == 9)
+ if (DISPLAY_VER(display) == 9)
selected_result = min_fixed16(method1, method2);
else
selected_result = method2;
@@ -1919,7 +1901,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
}
blocks = fixed16_to_u32_round_up(selected_result);
- if (DISPLAY_VER(i915) < 30)
+ if (DISPLAY_VER(display) < 30)
blocks++;
/*
@@ -1938,13 +1920,13 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
* channels' impact on the level 0 memory latency and the relevant
* wm calculations.
*/
- if (skl_wm_has_lines(i915, level))
+ if (skl_wm_has_lines(display, level))
blocks = max(blocks,
fixed16_to_u32_round_up(wp->plane_blocks_per_line));
lines = div_round_up_fixed16(selected_result,
wp->plane_blocks_per_line);
- if (DISPLAY_VER(i915) == 9) {
+ if (DISPLAY_VER(display) == 9) {
/* Display WA #1125: skl,bxt,kbl */
if (level == 0 && wp->rc_surface)
blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
@@ -1969,7 +1951,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
}
}
- if (DISPLAY_VER(i915) >= 11) {
+ if (DISPLAY_VER(display) >= 11) {
if (wp->y_tiled) {
int extra_lines;
@@ -1986,10 +1968,10 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
}
}
- if (!skl_wm_has_lines(i915, level))
+ if (!skl_wm_has_lines(display, level))
lines = 0;
- if (lines > skl_wm_max_lines(i915)) {
+ if (lines > skl_wm_max_lines(display)) {
/* reject it */
result->min_ddb_alloc = U16_MAX;
return;
@@ -2008,8 +1990,8 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
result->enable = true;
result->auto_min_alloc_wm_enable = xe3_auto_min_alloc_capable(plane, level);
- if (DISPLAY_VER(i915) < 12 && i915->display.sagv.block_time_us)
- result->can_sagv = latency >= i915->display.sagv.block_time_us;
+ if (DISPLAY_VER(display) < 12 && display->sagv.block_time_us)
+ result->can_sagv = latency >= display->sagv.block_time_us;
}
static void
@@ -2018,13 +2000,13 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wm_params,
struct skl_wm_level *levels)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
struct skl_wm_level *result_prev = &levels[0];
int level;
- for (level = 0; level < i915->display.wm.num_levels; level++) {
+ for (level = 0; level < display->wm.num_levels; level++) {
struct skl_wm_level *result = &levels[level];
- unsigned int latency = skl_wm_latency(i915, level, wm_params);
+ unsigned int latency = skl_wm_latency(display, level, wm_params);
skl_compute_plane_wm(crtc_state, plane, level, latency,
wm_params, result_prev, result);
@@ -2038,26 +2020,25 @@ static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wm_params,
struct skl_plane_wm *plane_wm)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
struct skl_wm_level *sagv_wm = &plane_wm->sagv.wm0;
struct skl_wm_level *levels = plane_wm->wm;
unsigned int latency = 0;
- if (i915->display.sagv.block_time_us)
- latency = i915->display.sagv.block_time_us +
- skl_wm_latency(i915, 0, wm_params);
+ if (display->sagv.block_time_us)
+ latency = display->sagv.block_time_us +
+ skl_wm_latency(display, 0, wm_params);
skl_compute_plane_wm(crtc_state, plane, 0, latency,
wm_params, &levels[0],
sagv_wm);
}
-static void skl_compute_transition_wm(struct drm_i915_private *i915,
+static void skl_compute_transition_wm(struct intel_display *display,
struct skl_wm_level *trans_wm,
const struct skl_wm_level *wm0,
const struct skl_wm_params *wp)
{
- struct intel_display *display = &i915->display;
u16 trans_min, trans_amount, trans_y_tile_min;
u16 wm0_blocks, trans_offset, blocks;
@@ -2069,16 +2050,16 @@ static void skl_compute_transition_wm(struct drm_i915_private *i915,
* WaDisableTWM:skl,kbl,cfl,bxt
* Transition WM are not recommended by HW team for GEN9
*/
- if (DISPLAY_VER(i915) == 9)
+ if (DISPLAY_VER(display) == 9)
return;
- if (DISPLAY_VER(i915) >= 11)
+ if (DISPLAY_VER(display) >= 11)
trans_min = 4;
else
trans_min = 14;
/* Display WA #1140: glk,cnl */
- if (DISPLAY_VER(i915) == 10)
+ if (DISPLAY_VER(display) == 10)
trans_amount = 0;
else
trans_amount = 10; /* This is configurable amount */
@@ -2120,8 +2101,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
struct intel_plane *plane, int color_plane)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc_state);
struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];
struct skl_wm_params wm_params;
int ret;
@@ -2133,13 +2113,13 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->wm);
- skl_compute_transition_wm(i915, &wm->trans_wm,
+ skl_compute_transition_wm(display, &wm->trans_wm,
&wm->wm[0], &wm_params);
- if (DISPLAY_VER(i915) >= 12) {
+ if (DISPLAY_VER(display) >= 12) {
tgl_compute_sagv_wm(crtc_state, plane, &wm_params, wm);
- skl_compute_transition_wm(i915, &wm->sagv.trans_wm,
+ skl_compute_transition_wm(display, &wm->sagv.trans_wm,
&wm->sagv.wm0, &wm_params);
}
@@ -2199,8 +2179,8 @@ static int skl_build_plane_wm(struct intel_crtc_state *crtc_state,
static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
+ struct intel_display *display = to_intel_display(plane_state);
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- struct drm_i915_private *i915 = to_i915(plane->base.dev);
enum plane_id plane_id = plane->id;
struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
int ret;
@@ -2214,9 +2194,9 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
if (plane_state->planar_linked_plane) {
const struct drm_framebuffer *fb = plane_state->hw.fb;
- drm_WARN_ON(&i915->drm,
+ drm_WARN_ON(display->drm,
!intel_wm_plane_visible(crtc_state, plane_state));
- drm_WARN_ON(&i915->drm, !fb->format->is_yuv ||
+ drm_WARN_ON(display->drm, !fb->format->is_yuv ||
fb->format->num_planes == 1);
ret = skl_build_plane_wm_single(crtc_state, plane_state,
@@ -2356,15 +2336,14 @@ static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state,
int wm0_lines)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc_state);
int level;
- for (level = i915->display.wm.num_levels - 1; level >= 0; level--) {
+ for (level = display->wm.num_levels - 1; level >= 0; level--) {
int latency;
/* FIXME should we care about the latency w/a's? */
- latency = skl_wm_latency(i915, level, NULL);
+ latency = skl_wm_latency(display, level, NULL);
if (latency == 0)
continue;
@@ -2381,8 +2360,8 @@ static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state,
static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
int wm0_lines, level;
if (!crtc_state->hw.active)
@@ -2398,9 +2377,9 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
* PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_*
* based on whether we're limited by the vblank duration.
*/
- crtc_state->wm_level_disabled = level < i915->display.wm.num_levels - 1;
+ crtc_state->wm_level_disabled = level < display->wm.num_levels - 1;
- for (level++; level < i915->display.wm.num_levels; level++) {
+ for (level++; level < display->wm.num_levels; level++) {
enum plane_id plane_id;
for_each_plane_id_on_crtc(crtc, plane_id) {
@@ -2416,10 +2395,10 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
}
}
- if (DISPLAY_VER(i915) >= 12 &&
- i915->display.sagv.block_time_us &&
+ if (DISPLAY_VER(display) >= 12 &&
+ display->sagv.block_time_us &&
skl_is_vblank_too_short(crtc_state, wm0_lines,
- i915->display.sagv.block_time_us)) {
+ display->sagv.block_time_us)) {
enum plane_id plane_id;
for_each_plane_id_on_crtc(crtc, plane_id) {
@@ -2437,7 +2416,7 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
static int skl_build_pipe_wm(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_plane_state *plane_state;
@@ -2453,7 +2432,7 @@ static int skl_build_pipe_wm(struct intel_atomic_state *state,
if (plane->pipe != crtc->pipe)
continue;
- if (DISPLAY_VER(i915) >= 11)
+ if (DISPLAY_VER(display) >= 11)
ret = icl_build_plane_wm(crtc_state, plane_state);
else
ret = skl_build_plane_wm(crtc_state, plane_state);
@@ -2476,11 +2455,10 @@ static bool skl_wm_level_equals(const struct skl_wm_level *l1,
l1->auto_min_alloc_wm_enable == l2->auto_min_alloc_wm_enable;
}
-static bool skl_plane_wm_equals(struct drm_i915_private *i915,
+static bool skl_plane_wm_equals(struct intel_display *display,
const struct skl_plane_wm *wm1,
const struct skl_plane_wm *wm2)
{
- struct intel_display *display = &i915->display;
int level;
for (level = 0; level < display->wm.num_levels; level++) {
@@ -2535,14 +2513,14 @@ static int
skl_ddb_add_affected_planes(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_plane *plane;
- for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
+ for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
struct intel_plane_state *plane_state;
enum plane_id plane_id = plane->id;
@@ -2553,7 +2531,7 @@ skl_ddb_add_affected_planes(struct intel_atomic_state *state,
continue;
if (new_crtc_state->do_async_flip) {
- drm_dbg_kms(&i915->drm, "[PLANE:%d:%s] Can't change DDB during async flip\n",
+ drm_dbg_kms(display->drm, "[PLANE:%d:%s] Can't change DDB during async flip\n",
plane->base.base.id, plane->base.name);
return -EINVAL;
}
@@ -2572,7 +2550,7 @@ skl_ddb_add_affected_planes(struct intel_atomic_state *state,
static u8 intel_dbuf_enabled_slices(const struct intel_dbuf_state *dbuf_state)
{
- struct drm_i915_private *i915 = to_i915(dbuf_state->base.state->base.dev);
+ struct intel_display *display = to_intel_display(dbuf_state->base.state->base.dev);
u8 enabled_slices;
enum pipe pipe;
@@ -2582,7 +2560,7 @@ static u8 intel_dbuf_enabled_slices(const struct intel_dbuf_state *dbuf_state)
*/
enabled_slices = BIT(DBUF_S1);
- for_each_pipe(i915, pipe)
+ for_each_pipe(display, pipe)
enabled_slices |= dbuf_state->slices[pipe];
return enabled_slices;
@@ -2592,7 +2570,6 @@ static int
skl_compute_ddb(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
- struct drm_i915_private *i915 = to_i915(state->base.dev);
const struct intel_dbuf_state *old_dbuf_state;
struct intel_dbuf_state *new_dbuf_state = NULL;
struct intel_crtc_state *new_crtc_state;
@@ -2631,7 +2608,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
}
}
- for_each_intel_crtc(&i915->drm, crtc) {
+ for_each_intel_crtc(display->drm, crtc) {
enum pipe pipe = crtc->pipe;
new_dbuf_state->slices[pipe] =
@@ -2654,11 +2631,11 @@ skl_compute_ddb(struct intel_atomic_state *state)
if (ret)
return ret;
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
old_dbuf_state->enabled_slices,
new_dbuf_state->enabled_slices,
- DISPLAY_INFO(i915)->dbuf.slice_mask,
+ DISPLAY_INFO(display)->dbuf.slice_mask,
str_yes_no(old_dbuf_state->joined_mbus),
str_yes_no(new_dbuf_state->joined_mbus));
}
@@ -2676,7 +2653,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
return ret;
}
- for_each_intel_crtc(&i915->drm, crtc) {
+ for_each_intel_crtc(display->drm, crtc) {
ret = skl_crtc_allocate_ddb(state, crtc);
if (ret)
return ret;
@@ -2703,7 +2680,7 @@ static char enast(bool enable)
static void
skl_print_wm_changes(struct intel_atomic_state *state)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
const struct intel_crtc_state *old_crtc_state;
const struct intel_crtc_state *new_crtc_state;
struct intel_plane *plane;
@@ -2720,7 +2697,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
old_pipe_wm = &old_crtc_state->wm.skl.optimal;
new_pipe_wm = &new_crtc_state->wm.skl.optimal;
- for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
+ for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
enum plane_id plane_id = plane->id;
const struct skl_ddb_entry *old, *new;
@@ -2730,24 +2707,24 @@ skl_print_wm_changes(struct intel_atomic_state *state)
if (skl_ddb_entry_equal(old, new))
continue;
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"[PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n",
plane->base.base.id, plane->base.name,
old->start, old->end, new->start, new->end,
skl_ddb_entry_size(old), skl_ddb_entry_size(new));
}
- for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
+ for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
enum plane_id plane_id = plane->id;
const struct skl_plane_wm *old_wm, *new_wm;
old_wm = &old_pipe_wm->planes[plane_id];
new_wm = &new_pipe_wm->planes[plane_id];
- if (skl_plane_wm_equals(i915, old_wm, new_wm))
+ if (skl_plane_wm_equals(display, old_wm, new_wm))
continue;
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
" -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n",
plane->base.base.id, plane->base.name,
@@ -2766,7 +2743,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
enast(new_wm->sagv.wm0.enable),
enast(new_wm->sagv.trans_wm.enable));
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d"
" -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d\n",
plane->base.base.id, plane->base.name,
@@ -2793,7 +2770,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
enast(new_wm->sagv.wm0.ignore_lines), new_wm->sagv.wm0.lines,
enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.lines);
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
plane->base.base.id, plane->base.name,
@@ -2812,7 +2789,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
new_wm->sagv.wm0.blocks,
new_wm->sagv.trans_wm.blocks);
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
plane->base.base.id, plane->base.name,
@@ -2890,14 +2867,14 @@ static bool skl_plane_selected_wm_equals(struct intel_plane *plane,
static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(state);
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_plane *plane;
- for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
+ for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
struct intel_plane_state *plane_state;
enum plane_id plane_id = plane->id;
@@ -2916,7 +2893,7 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
continue;
if (new_crtc_state->do_async_flip) {
- drm_dbg_kms(&i915->drm, "[PLANE:%d:%s] Can't change watermarks during async flip\n",
+ drm_dbg_kms(display->drm, "[PLANE:%d:%s] Can't change watermarks during async flip\n",
plane->base.base.id, plane->base.name);
return -EINVAL;
}
@@ -3115,9 +3092,8 @@ static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
static void skl_wm_get_hw_state(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
struct intel_dbuf_state *dbuf_state =
- to_intel_dbuf_state(i915->display.dbuf.obj.state);
+ to_intel_dbuf_state(display->dbuf.obj.state);
struct intel_crtc *crtc;
if (HAS_MBUS_JOINING(display))
@@ -3157,7 +3133,7 @@ static void skl_wm_get_hw_state(struct intel_display *display)
if (!crtc_state->hw.active)
continue;
- skl_ddb_get_hw_plane_state(i915, crtc->pipe,
+ skl_ddb_get_hw_plane_state(display, crtc->pipe,
plane_id, ddb, ddb_y,
min_ddb, interim_ddb);
@@ -3173,7 +3149,7 @@ static void skl_wm_get_hw_state(struct intel_display *display)
*/
slices = skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes,
dbuf_state->joined_mbus);
- mbus_offset = mbus_ddb_offset(i915, slices);
+ mbus_offset = mbus_ddb_offset(display, slices);
crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start;
crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end;
@@ -3206,16 +3182,18 @@ void skl_watermark_ipc_update(struct intel_display *display)
skl_watermark_ipc_enabled(display) ? DISP_IPC_ENABLE : 0);
}
-static bool skl_watermark_ipc_can_enable(struct drm_i915_private *i915)
+static bool skl_watermark_ipc_can_enable(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
/* Display WA #0477 WaDisableIPC: skl */
- if (IS_SKYLAKE(i915))
+ if (display->platform.skylake)
return false;
/* Display WA #1141: SKL:all KBL:all CFL */
- if (IS_KABYLAKE(i915) ||
- IS_COFFEELAKE(i915) ||
- IS_COMETLAKE(i915))
+ if (display->platform.kabylake ||
+ display->platform.coffeelake ||
+ display->platform.cometlake)
return i915->dram_info.symmetric_memory;
return true;
@@ -3223,20 +3201,19 @@ static bool skl_watermark_ipc_can_enable(struct drm_i915_private *i915)
void skl_watermark_ipc_init(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
-
if (!HAS_IPC(display))
return;
- display->wm.ipc_enabled = skl_watermark_ipc_can_enable(i915);
+ display->wm.ipc_enabled = skl_watermark_ipc_can_enable(display);
skl_watermark_ipc_update(display);
}
static void
-adjust_wm_latency(struct drm_i915_private *i915,
+adjust_wm_latency(struct intel_display *display,
u16 wm[], int num_levels, int read_latency)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
bool wm_lv_0_adjust_needed = i915->dram_info.wm_lv_0_adjust_needed;
int i, level;
@@ -3277,31 +3254,32 @@ adjust_wm_latency(struct drm_i915_private *i915,
wm[0] += 1;
}
-static void mtl_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
+static void mtl_read_wm_latency(struct intel_display *display, u16 wm[])
{
- int num_levels = i915->display.wm.num_levels;
+ int num_levels = display->wm.num_levels;
u32 val;
- val = intel_de_read(i915, MTL_LATENCY_LP0_LP1);
+ val = intel_de_read(display, MTL_LATENCY_LP0_LP1);
wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
- val = intel_de_read(i915, MTL_LATENCY_LP2_LP3);
+ val = intel_de_read(display, MTL_LATENCY_LP2_LP3);
wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
- val = intel_de_read(i915, MTL_LATENCY_LP4_LP5);
+ val = intel_de_read(display, MTL_LATENCY_LP4_LP5);
wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
- adjust_wm_latency(i915, wm, num_levels, 6);
+ adjust_wm_latency(display, wm, num_levels, 6);
}
-static void skl_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
+static void skl_read_wm_latency(struct intel_display *display, u16 wm[])
{
- int num_levels = i915->display.wm.num_levels;
- int read_latency = DISPLAY_VER(i915) >= 12 ? 3 : 2;
- int mult = IS_DG2(i915) ? 2 : 1;
+ struct drm_i915_private *i915 = to_i915(display->drm);
+ int num_levels = display->wm.num_levels;
+ int read_latency = DISPLAY_VER(display) >= 12 ? 3 : 2;
+ int mult = display->platform.dg2 ? 2 : 1;
u32 val;
int ret;
@@ -3309,7 +3287,7 @@ static void skl_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
val = 0; /* data0 to be programmed to 0 for first set */
ret = snb_pcode_read(&i915->uncore, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
if (ret) {
- drm_err(&i915->drm, "SKL Mailbox read error = %d\n", ret);
+ drm_err(display->drm, "SKL Mailbox read error = %d\n", ret);
return;
}
@@ -3322,7 +3300,7 @@ static void skl_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
val = 1; /* data0 to be programmed to 1 for second set */
ret = snb_pcode_read(&i915->uncore, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
if (ret) {
- drm_err(&i915->drm, "SKL Mailbox read error = %d\n", ret);
+ drm_err(display->drm, "SKL Mailbox read error = %d\n", ret);
return;
}
@@ -3331,22 +3309,20 @@ static void skl_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
wm[6] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult;
wm[7] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult;
- adjust_wm_latency(i915, wm, num_levels, read_latency);
+ adjust_wm_latency(display, wm, num_levels, read_latency);
}
-static void skl_setup_wm_latency(struct drm_i915_private *i915)
+static void skl_setup_wm_latency(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
-
if (HAS_HW_SAGV_WM(display))
display->wm.num_levels = 6;
else
display->wm.num_levels = 8;
if (DISPLAY_VER(display) >= 14)
- mtl_read_wm_latency(i915, display->wm.skl_latency);
+ mtl_read_wm_latency(display, display->wm.skl_latency);
else
- skl_read_wm_latency(i915, display->wm.skl_latency);
+ skl_read_wm_latency(display, display->wm.skl_latency);
intel_print_wm_latency(display, "Gen9 Plane", display->wm.skl_latency);
}
@@ -3376,10 +3352,10 @@ static const struct intel_global_state_funcs intel_dbuf_funcs = {
struct intel_dbuf_state *
intel_atomic_get_dbuf_state(struct intel_atomic_state *state)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
struct intel_global_state *dbuf_state;
- dbuf_state = intel_atomic_get_global_obj_state(state, &i915->display.dbuf.obj);
+ dbuf_state = intel_atomic_get_global_obj_state(state, &display->dbuf.obj);
if (IS_ERR(dbuf_state))
return ERR_CAST(dbuf_state);
@@ -3422,34 +3398,34 @@ static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
static u32 pipe_mbus_dbox_ctl(const struct intel_crtc *crtc,
const struct intel_dbuf_state *dbuf_state)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
u32 val = 0;
- if (DISPLAY_VER(i915) >= 14)
+ if (DISPLAY_VER(display) >= 14)
val |= MBUS_DBOX_I_CREDIT(2);
- if (DISPLAY_VER(i915) >= 12) {
+ if (DISPLAY_VER(display) >= 12) {
val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
}
- if (DISPLAY_VER(i915) >= 14)
+ if (DISPLAY_VER(display) >= 14)
val |= dbuf_state->joined_mbus ?
MBUS_DBOX_A_CREDIT(12) : MBUS_DBOX_A_CREDIT(8);
- else if (IS_ALDERLAKE_P(i915))
+ else if (display->platform.alderlake_p)
/* Wa_22010947358:adl-p */
val |= dbuf_state->joined_mbus ?
MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4);
else
val |= MBUS_DBOX_A_CREDIT(2);
- if (DISPLAY_VER(i915) >= 14) {
+ if (DISPLAY_VER(display) >= 14) {
val |= MBUS_DBOX_B_CREDIT(0xA);
- } else if (IS_ALDERLAKE_P(i915)) {
+ } else if (display->platform.alderlake_p) {
val |= MBUS_DBOX_BW_CREDIT(2);
val |= MBUS_DBOX_B_CREDIT(8);
- } else if (DISPLAY_VER(i915) >= 12) {
+ } else if (DISPLAY_VER(display) >= 12) {
val |= MBUS_DBOX_BW_CREDIT(2);
val |= MBUS_DBOX_B_CREDIT(12);
} else {
@@ -3457,7 +3433,7 @@ static u32 pipe_mbus_dbox_ctl(const struct intel_crtc *crtc,
val |= MBUS_DBOX_B_CREDIT(8);
}
- if (DISPLAY_VERx100(i915) == 1400) {
+ if (DISPLAY_VERx100(display) == 1400) {
if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe, dbuf_state->active_pipes))
val |= MBUS_DBOX_BW_8CREDITS_MTL;
else
@@ -3467,22 +3443,22 @@ static u32 pipe_mbus_dbox_ctl(const struct intel_crtc *crtc,
return val;
}
-static void pipe_mbus_dbox_ctl_update(struct drm_i915_private *i915,
+static void pipe_mbus_dbox_ctl_update(struct intel_display *display,
const struct intel_dbuf_state *dbuf_state)
{
struct intel_crtc *crtc;
- for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, dbuf_state->active_pipes)
- intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe),
+ for_each_intel_crtc_in_pipe_mask(display->drm, crtc, dbuf_state->active_pipes)
+ intel_de_write(display, PIPE_MBUS_DBOX_CTL(crtc->pipe),
pipe_mbus_dbox_ctl(crtc, dbuf_state));
}
static void intel_mbus_dbox_update(struct intel_atomic_state *state)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
- if (DISPLAY_VER(i915) < 11)
+ if (DISPLAY_VER(display) < 11)
return;
new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
@@ -3492,7 +3468,7 @@ static void intel_mbus_dbox_update(struct intel_atomic_state *state)
new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
return;
- pipe_mbus_dbox_ctl_update(i915, new_dbuf_state);
+ pipe_mbus_dbox_ctl_update(display, new_dbuf_state);
}
int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
@@ -3558,13 +3534,12 @@ static enum pipe intel_mbus_joined_pipe(struct intel_atomic_state *state,
const struct intel_dbuf_state *dbuf_state)
{
struct intel_display *display = to_intel_display(state);
- struct drm_i915_private *i915 = to_i915(state->base.dev);
enum pipe pipe = ffs(dbuf_state->active_pipes) - 1;
const struct intel_crtc_state *new_crtc_state;
struct intel_crtc *crtc;
- drm_WARN_ON(&i915->drm, !dbuf_state->joined_mbus);
- drm_WARN_ON(&i915->drm, !is_power_of_2(dbuf_state->active_pipes));
+ drm_WARN_ON(display->drm, !dbuf_state->joined_mbus);
+ drm_WARN_ON(display->drm, !is_power_of_2(dbuf_state->active_pipes));
crtc = intel_crtc_for_pipe(display, pipe);
new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
@@ -3575,7 +3550,7 @@ static enum pipe intel_mbus_joined_pipe(struct intel_atomic_state *state,
return INVALID_PIPE;
}
-static void mbus_ctl_join_update(struct drm_i915_private *i915,
+static void mbus_ctl_join_update(struct intel_display *display,
const struct intel_dbuf_state *dbuf_state,
enum pipe pipe)
{
@@ -3591,7 +3566,7 @@ static void mbus_ctl_join_update(struct drm_i915_private *i915,
else
mbus_ctl |= MBUS_JOIN_PIPE_SELECT_NONE;
- intel_de_rmw(i915, MBUS_CTL,
+ intel_de_rmw(display, MBUS_CTL,
MBUS_HASHING_MODE_MASK | MBUS_JOIN |
MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
}
@@ -3599,18 +3574,18 @@ static void mbus_ctl_join_update(struct drm_i915_private *i915,
static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state,
enum pipe pipe)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
const struct intel_dbuf_state *old_dbuf_state =
intel_atomic_get_old_dbuf_state(state);
const struct intel_dbuf_state *new_dbuf_state =
intel_atomic_get_new_dbuf_state(state);
- drm_dbg_kms(&i915->drm, "Changing mbus joined: %s -> %s (pipe: %c)\n",
+ drm_dbg_kms(display->drm, "Changing mbus joined: %s -> %s (pipe: %c)\n",
str_yes_no(old_dbuf_state->joined_mbus),
str_yes_no(new_dbuf_state->joined_mbus),
pipe != INVALID_PIPE ? pipe_name(pipe) : '*');
- mbus_ctl_join_update(i915, new_dbuf_state, pipe);
+ mbus_ctl_join_update(display, new_dbuf_state, pipe);
}
void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state)
@@ -3715,9 +3690,8 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
gen9_dbuf_slices_update(display, new_slices);
}
-static void skl_mbus_sanitize(struct drm_i915_private *i915)
+static void skl_mbus_sanitize(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
struct intel_dbuf_state *dbuf_state =
to_intel_dbuf_state(display->dbuf.obj.state);
@@ -3735,25 +3709,25 @@ static void skl_mbus_sanitize(struct drm_i915_private *i915)
intel_dbuf_mdclk_cdclk_ratio_update(display,
dbuf_state->mdclk_cdclk_ratio,
dbuf_state->joined_mbus);
- pipe_mbus_dbox_ctl_update(i915, dbuf_state);
- mbus_ctl_join_update(i915, dbuf_state, INVALID_PIPE);
+ pipe_mbus_dbox_ctl_update(display, dbuf_state);
+ mbus_ctl_join_update(display, dbuf_state, INVALID_PIPE);
}
-static bool skl_dbuf_is_misconfigured(struct drm_i915_private *i915)
+static bool skl_dbuf_is_misconfigured(struct intel_display *display)
{
const struct intel_dbuf_state *dbuf_state =
- to_intel_dbuf_state(i915->display.dbuf.obj.state);
+ to_intel_dbuf_state(display->dbuf.obj.state);
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
struct intel_crtc *crtc;
- for_each_intel_crtc(&i915->drm, crtc) {
+ for_each_intel_crtc(display->drm, crtc) {
const struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
entries[crtc->pipe] = crtc_state->wm.skl.ddb;
}
- for_each_intel_crtc(&i915->drm, crtc) {
+ for_each_intel_crtc(display->drm, crtc) {
const struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
u8 slices;
@@ -3771,7 +3745,7 @@ static bool skl_dbuf_is_misconfigured(struct drm_i915_private *i915)
return false;
}
-static void skl_dbuf_sanitize(struct drm_i915_private *i915)
+static void skl_dbuf_sanitize(struct intel_display *display)
{
struct intel_crtc *crtc;
@@ -3786,12 +3760,12 @@ static void skl_dbuf_sanitize(struct drm_i915_private *i915)
* all the planes so that skl_commit_modeset_enables() can
* simply ignore them.
*/
- if (!skl_dbuf_is_misconfigured(i915))
+ if (!skl_dbuf_is_misconfigured(display))
return;
- drm_dbg_kms(&i915->drm, "BIOS has misprogrammed the DBUF, disabling all planes\n");
+ drm_dbg_kms(display->drm, "BIOS has misprogrammed the DBUF, disabling all planes\n");
- for_each_intel_crtc(&i915->drm, crtc) {
+ for_each_intel_crtc(display->drm, crtc) {
struct intel_plane *plane = to_intel_plane(crtc->base.primary);
const struct intel_plane_state *plane_state =
to_intel_plane_state(plane->base.state);
@@ -3801,7 +3775,7 @@ static void skl_dbuf_sanitize(struct drm_i915_private *i915)
if (plane_state->uapi.visible)
intel_plane_disable_noatomic(crtc, plane);
- drm_WARN_ON(&i915->drm, crtc_state->active_planes != 0);
+ drm_WARN_ON(display->drm, crtc_state->active_planes != 0);
memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb));
}
@@ -3809,10 +3783,8 @@ static void skl_dbuf_sanitize(struct drm_i915_private *i915)
static void skl_wm_sanitize(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
-
- skl_mbus_sanitize(i915);
- skl_dbuf_sanitize(i915);
+ skl_mbus_sanitize(display);
+ skl_dbuf_sanitize(display);
}
void skl_wm_crtc_disable_noatomic(struct intel_crtc *crtc)
@@ -3863,7 +3835,6 @@ void intel_wm_state_verify(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(state);
- struct drm_i915_private *i915 = to_i915(state->base.dev);
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct skl_hw_state {
@@ -3878,7 +3849,7 @@ void intel_wm_state_verify(struct intel_atomic_state *state,
u8 hw_enabled_slices;
int level;
- if (DISPLAY_VER(i915) < 9 || !new_crtc_state->hw.active)
+ if (DISPLAY_VER(display) < 9 || !new_crtc_state->hw.active)
return;
hw = kzalloc(sizeof(*hw), GFP_KERNEL);
@@ -3891,26 +3862,26 @@ void intel_wm_state_verify(struct intel_atomic_state *state,
hw_enabled_slices = intel_enabled_dbuf_slices_mask(display);
- if (DISPLAY_VER(i915) >= 11 &&
- hw_enabled_slices != i915->display.dbuf.enabled_slices)
- drm_err(&i915->drm,
+ if (DISPLAY_VER(display) >= 11 &&
+ hw_enabled_slices != display->dbuf.enabled_slices)
+ drm_err(display->drm,
"mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
- i915->display.dbuf.enabled_slices,
+ display->dbuf.enabled_slices,
hw_enabled_slices);
- for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
+ for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
const struct skl_wm_level *hw_wm_level, *sw_wm_level;
/* Watermarks */
- for (level = 0; level < i915->display.wm.num_levels; level++) {
+ for (level = 0; level < display->wm.num_levels; level++) {
hw_wm_level = &hw->wm.planes[plane->id].wm[level];
sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level);
if (skl_wm_level_equals(hw_wm_level, sw_wm_level))
continue;
- drm_err(&i915->drm,
+ drm_err(display->drm,
"[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
plane->base.base.id, plane->base.name, level,
sw_wm_level->enable,
@@ -3925,7 +3896,7 @@ void intel_wm_state_verify(struct intel_atomic_state *state,
sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id);
if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
- drm_err(&i915->drm,
+ drm_err(display->drm,
"[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
plane->base.base.id, plane->base.name,
sw_wm_level->enable,
@@ -3941,7 +3912,7 @@ void intel_wm_state_verify(struct intel_atomic_state *state,
if (HAS_HW_SAGV_WM(display) &&
!skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
- drm_err(&i915->drm,
+ drm_err(display->drm,
"[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
plane->base.base.id, plane->base.name,
sw_wm_level->enable,
@@ -3957,7 +3928,7 @@ void intel_wm_state_verify(struct intel_atomic_state *state,
if (HAS_HW_SAGV_WM(display) &&
!skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
- drm_err(&i915->drm,
+ drm_err(display->drm,
"[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
plane->base.base.id, plane->base.name,
sw_wm_level->enable,
@@ -3973,7 +3944,7 @@ void intel_wm_state_verify(struct intel_atomic_state *state,
sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];
if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
- drm_err(&i915->drm,
+ drm_err(display->drm,
"[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n",
plane->base.base.id, plane->base.name,
sw_ddb_entry->start, sw_ddb_entry->end,
@@ -3992,19 +3963,16 @@ static const struct intel_wm_funcs skl_wm_funcs = {
void skl_wm_init(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
-
- intel_sagv_init(i915);
+ intel_sagv_init(display);
- skl_setup_wm_latency(i915);
+ skl_setup_wm_latency(display);
display->funcs.wm = &skl_wm_funcs;
}
static int skl_watermark_ipc_status_show(struct seq_file *m, void *data)
{
- struct drm_i915_private *i915 = m->private;
- struct intel_display *display = &i915->display;
+ struct intel_display *display = m->private;
seq_printf(m, "Isochronous Priority Control: %s\n",
str_yes_no(skl_watermark_ipc_enabled(display)));
@@ -4013,9 +3981,9 @@ static int skl_watermark_ipc_status_show(struct seq_file *m, void *data)
static int skl_watermark_ipc_status_open(struct inode *inode, struct file *file)
{
- struct drm_i915_private *i915 = inode->i_private;
+ struct intel_display *display = inode->i_private;
- return single_open(file, skl_watermark_ipc_status_show, i915);
+ return single_open(file, skl_watermark_ipc_status_show, display);
}
static ssize_t skl_watermark_ipc_status_write(struct file *file,
@@ -4023,8 +3991,7 @@ static ssize_t skl_watermark_ipc_status_write(struct file *file,
size_t len, loff_t *offp)
{
struct seq_file *m = file->private_data;
- struct drm_i915_private *i915 = m->private;
- struct intel_display *display = &i915->display;
+ struct intel_display *display = m->private;
bool enable;
int ret;
@@ -4054,8 +4021,7 @@ static const struct file_operations skl_watermark_ipc_status_fops = {
static int intel_sagv_status_show(struct seq_file *m, void *unused)
{
- struct drm_i915_private *i915 = m->private;
- struct intel_display *display = &i915->display;
+ struct intel_display *display = m->private;
static const char * const sagv_status[] = {
[I915_SAGV_UNKNOWN] = "unknown",
[I915_SAGV_DISABLED] = "disabled",
@@ -4065,9 +4031,9 @@ static int intel_sagv_status_show(struct seq_file *m, void *unused)
seq_printf(m, "SAGV available: %s\n", str_yes_no(intel_has_sagv(display)));
seq_printf(m, "SAGV modparam: %s\n",
- str_enabled_disabled(i915->display.params.enable_sagv));
- seq_printf(m, "SAGV status: %s\n", sagv_status[i915->display.sagv.status]);
- seq_printf(m, "SAGV block time: %d usec\n", i915->display.sagv.block_time_us);
+ str_enabled_disabled(display->params.enable_sagv));
+ seq_printf(m, "SAGV status: %s\n", sagv_status[display->sagv.status]);
+ seq_printf(m, "SAGV block time: %d usec\n", display->sagv.block_time_us);
return 0;
}
@@ -4076,25 +4042,23 @@ DEFINE_SHOW_ATTRIBUTE(intel_sagv_status);
void skl_watermark_debugfs_register(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
struct drm_minor *minor = display->drm->primary;
if (HAS_IPC(display))
- debugfs_create_file("i915_ipc_status", 0644, minor->debugfs_root, i915,
- &skl_watermark_ipc_status_fops);
+ debugfs_create_file("i915_ipc_status", 0644, minor->debugfs_root,
+ display, &skl_watermark_ipc_status_fops);
if (HAS_SAGV(display))
- debugfs_create_file("i915_sagv_status", 0444, minor->debugfs_root, i915,
- &intel_sagv_status_fops);
+ debugfs_create_file("i915_sagv_status", 0444, minor->debugfs_root,
+ display, &intel_sagv_status_fops);
}
unsigned int skl_watermark_max_latency(struct intel_display *display, int initial_wm_level)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
int level;
for (level = display->wm.num_levels - 1; level >= initial_wm_level; level--) {
- unsigned int latency = skl_wm_latency(i915, level, NULL);
+ unsigned int latency = skl_wm_latency(display, level, NULL);
if (latency)
return latency;
--
2.39.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 5/7] drm/i915/wm: convert i9xx_wm.h external interfaces to struct intel_display
2025-04-08 13:38 [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display Jani Nikula
` (3 preceding siblings ...)
2025-04-08 13:38 ` [PATCH v2 4/7] drm/i915/wm: convert skl_watermarks.c internally " Jani Nikula
@ 2025-04-08 13:38 ` Jani Nikula
2025-04-08 13:38 ` [PATCH v2 6/7] drm/i915/wm: convert i9xx_wm.c to intel_de_*() register interface Jani Nikula
` (6 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2025-04-08 13:38 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Going forward, struct intel_display is the main display device data
pointer. Convert the i9xx_wm.h interface to struct intel_display.
With this, we can make intel_wm.c independent of i915_drv.h.
v2: Also remove i915_drv.h, fix commit message
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 32 +++++++++++--------
drivers/gpu/drm/i915/display/i9xx_wm.h | 18 +++++------
drivers/gpu/drm/i915/display/intel_display.c | 8 ++---
.../drm/i915/display/intel_display_driver.c | 2 +-
drivers/gpu/drm/i915/display/intel_wm.c | 9 +++---
5 files changed, 37 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index e6a1b9b10b01..7202ef503e58 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -200,7 +200,7 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl
/**
* intel_set_memory_cxsr - Configure CxSR state
- * @dev_priv: i915 device
+ * @display: display device
* @enable: Allow vs. disallow CxSR
*
* Allow or disallow the system to enter a special CxSR
@@ -235,8 +235,9 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl
* the hardware w.r.t. HPLL SR when writing to plane registers.
* Disallowing just CxSR is sufficient.
*/
-bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
+bool intel_set_memory_cxsr(struct intel_display *display, bool enable)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
bool ret;
mutex_lock(&dev_priv->display.wm.wm_mutex);
@@ -652,7 +653,7 @@ static void pnv_update_wm(struct intel_display *display)
latency = pnv_get_cxsr_latency(dev_priv);
if (!latency) {
drm_dbg_kms(&dev_priv->drm, "Unknown FSB/MEM, disabling CxSR\n");
- intel_set_memory_cxsr(dev_priv, false);
+ intel_set_memory_cxsr(display, false);
return;
}
@@ -702,9 +703,9 @@ static void pnv_update_wm(struct intel_display *display)
intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv), reg);
drm_dbg_kms(&dev_priv->drm, "DSPFW3 register is %x\n", reg);
- intel_set_memory_cxsr(dev_priv, true);
+ intel_set_memory_cxsr(display, true);
} else {
- intel_set_memory_cxsr(dev_priv, false);
+ intel_set_memory_cxsr(display, false);
}
}
@@ -2177,7 +2178,7 @@ static void i965_update_wm(struct intel_display *display)
} else {
cxsr_enabled = false;
/* Turn off self refresh if both pipes are enabled */
- intel_set_memory_cxsr(dev_priv, false);
+ intel_set_memory_cxsr(display, false);
}
drm_dbg_kms(&dev_priv->drm,
@@ -2198,7 +2199,7 @@ static void i965_update_wm(struct intel_display *display)
FW_WM(cursor_sr, CURSOR_SR));
if (cxsr_enabled)
- intel_set_memory_cxsr(dev_priv, true);
+ intel_set_memory_cxsr(display, true);
}
#undef FW_WM
@@ -2307,7 +2308,7 @@ static void i9xx_update_wm(struct intel_display *display)
cwm = 2;
/* Play safe and disable self-refresh before adjusting watermarks. */
- intel_set_memory_cxsr(dev_priv, false);
+ intel_set_memory_cxsr(display, false);
/* Calc sr entries for one plane configs */
if (HAS_FW_BLC(dev_priv) && crtc) {
@@ -2359,7 +2360,7 @@ static void i9xx_update_wm(struct intel_display *display)
intel_uncore_write(&dev_priv->uncore, FW_BLC2, fwater_hi);
if (crtc)
- intel_set_memory_cxsr(dev_priv, true);
+ intel_set_memory_cxsr(display, true);
}
static void i845_update_wm(struct intel_display *display)
@@ -3411,8 +3412,10 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
dev_priv->display.wm.hw = *results;
}
-bool ilk_disable_cxsr(struct drm_i915_private *dev_priv)
+bool ilk_disable_cxsr(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
}
@@ -3580,8 +3583,9 @@ static int ilk_sanitize_watermarks_add_affected(struct drm_atomic_state *state)
* through the atomic check code to calculate new watermark values in the
* state object.
*/
-void ilk_wm_sanitize(struct drm_i915_private *dev_priv)
+void ilk_wm_sanitize(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct drm_atomic_state *state;
struct intel_atomic_state *intel_state;
struct intel_crtc *crtc;
@@ -4156,8 +4160,10 @@ static const struct intel_wm_funcs i845_wm_funcs = {
static const struct intel_wm_funcs nop_funcs = {
};
-void i9xx_wm_init(struct drm_i915_private *dev_priv)
+void i9xx_wm_init(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
/* For FIFO watermark updates */
if (HAS_PCH_SPLIT(dev_priv)) {
ilk_setup_wm_latency(dev_priv);
@@ -4172,7 +4178,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv)
if (!pnv_get_cxsr_latency(dev_priv)) {
drm_info(&dev_priv->drm, "Unknown FSB/MEM, disabling CxSR\n");
/* Disable CxSR and never update its watermark again */
- intel_set_memory_cxsr(dev_priv, false);
+ intel_set_memory_cxsr(display, false);
dev_priv->display.funcs.wm = &nop_funcs;
} else {
dev_priv->display.funcs.wm = &pnv_wm_funcs;
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.h b/drivers/gpu/drm/i915/display/i9xx_wm.h
index 06ac37c6c94b..7bb363b2a756 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.h
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.h
@@ -8,28 +8,28 @@
#include <linux/types.h>
-struct drm_i915_private;
struct intel_crtc_state;
+struct intel_display;
struct intel_plane_state;
#ifdef I915
-bool ilk_disable_cxsr(struct drm_i915_private *i915);
-void ilk_wm_sanitize(struct drm_i915_private *i915);
-bool intel_set_memory_cxsr(struct drm_i915_private *i915, bool enable);
-void i9xx_wm_init(struct drm_i915_private *i915);
+bool ilk_disable_cxsr(struct intel_display *display);
+void ilk_wm_sanitize(struct intel_display *display);
+bool intel_set_memory_cxsr(struct intel_display *display, bool enable);
+void i9xx_wm_init(struct intel_display *display);
#else
-static inline bool ilk_disable_cxsr(struct drm_i915_private *i915)
+static inline bool ilk_disable_cxsr(struct intel_display *display)
{
return false;
}
-static inline void ilk_wm_sanitize(struct drm_i915_private *i915)
+static inline void ilk_wm_sanitize(struct intel_display *display)
{
}
-static inline bool intel_set_memory_cxsr(struct drm_i915_private *i915, bool enable)
+static inline bool intel_set_memory_cxsr(struct intel_display *display, bool enable)
{
return false;
}
-static inline void i9xx_wm_init(struct drm_i915_private *i915)
+static inline void i9xx_wm_init(struct intel_display *display)
{
}
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 745eef470bad..db524d01e574 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -664,7 +664,6 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
struct intel_plane *plane)
{
struct intel_display *display = to_intel_display(crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
struct intel_plane_state *plane_state =
@@ -697,7 +696,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
* wait-for-vblank between disabling the plane and the pipe.
*/
if (HAS_GMCH(display) &&
- intel_set_memory_cxsr(dev_priv, false))
+ intel_set_memory_cxsr(display, false))
intel_plane_initial_vblank_wait(crtc);
/*
@@ -1169,7 +1168,6 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(state);
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
const struct intel_crtc_state *new_crtc_state =
@@ -1223,7 +1221,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
* wait-for-vblank between disabling the plane and the pipe.
*/
if (HAS_GMCH(display) && old_crtc_state->hw.active &&
- new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
+ new_crtc_state->disable_cxsr && intel_set_memory_cxsr(display, false))
intel_crtc_wait_for_next_vblank(crtc);
/*
@@ -1234,7 +1232,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
* WaCxSRDisabledForSpriteScaling:ivb
*/
if (!HAS_GMCH(display) && old_crtc_state->hw.active &&
- new_crtc_state->disable_cxsr && ilk_disable_cxsr(dev_priv))
+ new_crtc_state->disable_cxsr && ilk_disable_cxsr(display))
intel_crtc_wait_for_next_vblank(crtc);
/*
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index f6d5d51dda0f..efee8925987e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -476,7 +476,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
* since the watermark calculation done here will use pstate->fb.
*/
if (!HAS_GMCH(display))
- ilk_wm_sanitize(i915);
+ ilk_wm_sanitize(display);
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_wm.c b/drivers/gpu/drm/i915/display/intel_wm.c
index 43c69a672bb3..bba82e888db2 100644
--- a/drivers/gpu/drm/i915/display/intel_wm.c
+++ b/drivers/gpu/drm/i915/display/intel_wm.c
@@ -5,8 +5,11 @@
#include <linux/debugfs.h>
-#include "i915_drv.h"
+#include <drm/drm_file.h>
+#include <drm/drm_print.h>
+
#include "i9xx_wm.h"
+#include "intel_display_core.h"
#include "intel_display_types.h"
#include "intel_wm.h"
#include "skl_watermark.h"
@@ -169,12 +172,10 @@ void intel_print_wm_latency(struct intel_display *display,
void intel_wm_init(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
-
if (DISPLAY_VER(display) >= 9)
skl_wm_init(display);
else
- i9xx_wm_init(i915);
+ i9xx_wm_init(display);
}
static void wm_latency_show(struct seq_file *m, const u16 wm[8])
--
2.39.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 6/7] drm/i915/wm: convert i9xx_wm.c to intel_de_*() register interface
2025-04-08 13:38 [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display Jani Nikula
` (4 preceding siblings ...)
2025-04-08 13:38 ` [PATCH v2 5/7] drm/i915/wm: convert i9xx_wm.h external interfaces " Jani Nikula
@ 2025-04-08 13:38 ` Jani Nikula
2025-04-08 13:38 ` [PATCH v2 7/7] drm/i915/wm: convert i9xx_wm.c internally to struct intel_display Jani Nikula
` (5 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2025-04-08 13:38 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
The registers handled in i9xx_wm.c are mostly display registers. The
MCH_SSKPD and MLTR_ILK registers are not. Convert register access to
intel_de_*() interface where applicaple.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 383 +++++++++++++------------
1 file changed, 196 insertions(+), 187 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 7202ef503e58..49ded623c084 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -9,6 +9,7 @@
#include "i9xx_wm_regs.h"
#include "intel_atomic.h"
#include "intel_bo.h"
+#include "intel_de.h"
#include "intel_display.h"
#include "intel_display_trace.h"
#include "intel_fb.h"
@@ -152,39 +153,39 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl
u32 val;
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
- intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
- intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF_VLV);
+ was_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
+ intel_de_write(display, FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
+ intel_de_posting_read(display, FW_BLC_SELF_VLV);
} else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
- was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
- intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
- intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF);
+ was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
+ intel_de_write(display, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
+ intel_de_posting_read(display, FW_BLC_SELF);
} else if (IS_PINEVIEW(dev_priv)) {
- val = intel_uncore_read(&dev_priv->uncore, DSPFW3(dev_priv));
+ val = intel_de_read(display, DSPFW3(display));
was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
if (enable)
val |= PINEVIEW_SELF_REFRESH_EN;
else
val &= ~PINEVIEW_SELF_REFRESH_EN;
- intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv), val);
- intel_uncore_posting_read(&dev_priv->uncore, DSPFW3(dev_priv));
+ intel_de_write(display, DSPFW3(display), val);
+ intel_de_posting_read(display, DSPFW3(display));
} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
- was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
+ was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
_MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
- intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, val);
- intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF);
+ intel_de_write(display, FW_BLC_SELF, val);
+ intel_de_posting_read(display, FW_BLC_SELF);
} else if (IS_I915GM(dev_priv)) {
/*
* FIXME can't find a bit like this for 915G, and
* yet it does have the related watermark in
* FW_BLC_SELF. What's going on?
*/
- was_enabled = intel_uncore_read(&dev_priv->uncore, INSTPM) & INSTPM_SELF_EN;
+ was_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;
val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
_MASKED_BIT_DISABLE(INSTPM_SELF_EN);
- intel_uncore_write(&dev_priv->uncore, INSTPM, val);
- intel_uncore_posting_read(&dev_priv->uncore, INSTPM);
+ intel_de_write(display, INSTPM, val);
+ intel_de_posting_read(display, INSTPM);
} else {
return false;
}
@@ -272,8 +273,8 @@ static const int pessimal_latency_ns = 5000;
static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
enum pipe pipe = crtc->pipe;
int sprite0_start, sprite1_start;
@@ -281,22 +282,20 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
switch (pipe) {
case PIPE_A:
- dsparb = intel_uncore_read(&dev_priv->uncore,
- DSPARB(dev_priv));
- dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
+ dsparb = intel_de_read(display, DSPARB(display));
+ dsparb2 = intel_de_read(display, DSPARB2);
sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
break;
case PIPE_B:
- dsparb = intel_uncore_read(&dev_priv->uncore,
- DSPARB(dev_priv));
- dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
+ dsparb = intel_de_read(display, DSPARB(display));
+ dsparb2 = intel_de_read(display, DSPARB2);
sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
break;
case PIPE_C:
- dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
- dsparb3 = intel_uncore_read(&dev_priv->uncore, DSPARB3);
+ dsparb2 = intel_de_read(display, DSPARB2);
+ dsparb3 = intel_de_read(display, DSPARB3);
sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
break;
@@ -314,7 +313,8 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane)
{
- u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv));
+ struct intel_display *display = &dev_priv->display;
+ u32 dsparb = intel_de_read(display, DSPARB(display));
int size;
size = dsparb & 0x7f;
@@ -330,7 +330,8 @@ static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane)
{
- u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv));
+ struct intel_display *display = &dev_priv->display;
+ u32 dsparb = intel_de_read(display, DSPARB(display));
int size;
size = dsparb & 0x1ff;
@@ -347,7 +348,8 @@ static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane)
{
- u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv));
+ struct intel_display *display = &dev_priv->display;
+ u32 dsparb = intel_de_read(display, DSPARB(display));
int size;
size = dsparb & 0x7f;
@@ -669,10 +671,10 @@ static void pnv_update_wm(struct intel_display *display)
&pnv_display_wm,
pnv_display_wm.fifo_size,
cpp, latency->display_sr);
- reg = intel_uncore_read(&dev_priv->uncore, DSPFW1(dev_priv));
+ reg = intel_de_read(display, DSPFW1(display));
reg &= ~DSPFW_SR_MASK;
reg |= FW_WM(wm, SR);
- intel_uncore_write(&dev_priv->uncore, DSPFW1(dev_priv), reg);
+ intel_de_write(display, DSPFW1(display), reg);
drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg);
/* cursor SR */
@@ -680,27 +682,26 @@ static void pnv_update_wm(struct intel_display *display)
&pnv_cursor_wm,
pnv_display_wm.fifo_size,
4, latency->cursor_sr);
- intel_uncore_rmw(&dev_priv->uncore, DSPFW3(dev_priv),
- DSPFW_CURSOR_SR_MASK,
- FW_WM(wm, CURSOR_SR));
+ intel_de_rmw(display, DSPFW3(display),
+ DSPFW_CURSOR_SR_MASK, FW_WM(wm, CURSOR_SR));
/* Display HPLL off SR */
wm = intel_calculate_wm(dev_priv, pixel_rate,
&pnv_display_hplloff_wm,
pnv_display_hplloff_wm.fifo_size,
cpp, latency->display_hpll_disable);
- intel_uncore_rmw(&dev_priv->uncore, DSPFW3(dev_priv),
- DSPFW_HPLL_SR_MASK, FW_WM(wm, HPLL_SR));
+ intel_de_rmw(display, DSPFW3(display),
+ DSPFW_HPLL_SR_MASK, FW_WM(wm, HPLL_SR));
/* cursor HPLL off SR */
wm = intel_calculate_wm(dev_priv, pixel_rate,
&pnv_cursor_hplloff_wm,
pnv_display_hplloff_wm.fifo_size,
4, latency->cursor_hpll_disable);
- reg = intel_uncore_read(&dev_priv->uncore, DSPFW3(dev_priv));
+ reg = intel_de_read(display, DSPFW3(display));
reg &= ~DSPFW_HPLL_CURSOR_MASK;
reg |= FW_WM(wm, HPLL_CURSOR);
- intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv), reg);
+ intel_de_write(display, DSPFW3(display), reg);
drm_dbg_kms(&dev_priv->drm, "DSPFW3 register is %x\n", reg);
intel_set_memory_cxsr(display, true);
@@ -805,25 +806,25 @@ static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
for_each_pipe(dev_priv, pipe)
trace_g4x_wm(intel_crtc_for_pipe(display, pipe), wm);
- intel_uncore_write(&dev_priv->uncore, DSPFW1(dev_priv),
- FW_WM(wm->sr.plane, SR) |
- FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
- FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
- FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
- intel_uncore_write(&dev_priv->uncore, DSPFW2(dev_priv),
- (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
- FW_WM(wm->sr.fbc, FBC_SR) |
- FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
- FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
- FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
- FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
- intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv),
- (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
- FW_WM(wm->sr.cursor, CURSOR_SR) |
- FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
- FW_WM(wm->hpll.plane, HPLL_SR));
-
- intel_uncore_posting_read(&dev_priv->uncore, DSPFW1(dev_priv));
+ intel_de_write(display, DSPFW1(display),
+ FW_WM(wm->sr.plane, SR) |
+ FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
+ FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
+ FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
+ intel_de_write(display, DSPFW2(display),
+ (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
+ FW_WM(wm->sr.fbc, FBC_SR) |
+ FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
+ FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
+ FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
+ FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
+ intel_de_write(display, DSPFW3(display),
+ (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
+ FW_WM(wm->sr.cursor, CURSOR_SR) |
+ FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
+ FW_WM(wm->hpll.plane, HPLL_SR));
+
+ intel_de_posting_read(display, DSPFW1(display));
}
#define FW_WM_VLV(value, plane) \
@@ -838,11 +839,11 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
for_each_pipe(dev_priv, pipe) {
trace_vlv_wm(intel_crtc_for_pipe(display, pipe), wm);
- intel_uncore_write(&dev_priv->uncore, VLV_DDL(pipe),
- (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
- (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
- (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
- (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
+ intel_de_write(display, VLV_DDL(pipe),
+ (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
+ (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
+ (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
+ (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
}
/*
@@ -850,60 +851,60 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
* high order bits so that there are no out of bounds values
* present in the registers during the reprogramming.
*/
- intel_uncore_write(&dev_priv->uncore, DSPHOWM, 0);
- intel_uncore_write(&dev_priv->uncore, DSPHOWM1, 0);
- intel_uncore_write(&dev_priv->uncore, DSPFW4, 0);
- intel_uncore_write(&dev_priv->uncore, DSPFW5, 0);
- intel_uncore_write(&dev_priv->uncore, DSPFW6, 0);
-
- intel_uncore_write(&dev_priv->uncore, DSPFW1(dev_priv),
- FW_WM(wm->sr.plane, SR) |
- FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
- FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
- FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
- intel_uncore_write(&dev_priv->uncore, DSPFW2(dev_priv),
- FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
- FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
- FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
- intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv),
- FW_WM(wm->sr.cursor, CURSOR_SR));
+ intel_de_write(display, DSPHOWM, 0);
+ intel_de_write(display, DSPHOWM1, 0);
+ intel_de_write(display, DSPFW4, 0);
+ intel_de_write(display, DSPFW5, 0);
+ intel_de_write(display, DSPFW6, 0);
+
+ intel_de_write(display, DSPFW1(display),
+ FW_WM(wm->sr.plane, SR) |
+ FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
+ FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
+ FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
+ intel_de_write(display, DSPFW2(display),
+ FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
+ FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
+ FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
+ intel_de_write(display, DSPFW3(display),
+ FW_WM(wm->sr.cursor, CURSOR_SR));
if (IS_CHERRYVIEW(dev_priv)) {
- intel_uncore_write(&dev_priv->uncore, DSPFW7_CHV,
- FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
- FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
- intel_uncore_write(&dev_priv->uncore, DSPFW8_CHV,
- FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
- FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
- intel_uncore_write(&dev_priv->uncore, DSPFW9_CHV,
- FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
- FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
- intel_uncore_write(&dev_priv->uncore, DSPHOWM,
- FW_WM(wm->sr.plane >> 9, SR_HI) |
- FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
- FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
- FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
- FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
- FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
- FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
- FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
- FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
- FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
+ intel_de_write(display, DSPFW7_CHV,
+ FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
+ FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
+ intel_de_write(display, DSPFW8_CHV,
+ FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
+ FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
+ intel_de_write(display, DSPFW9_CHV,
+ FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
+ FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
+ intel_de_write(display, DSPHOWM,
+ FW_WM(wm->sr.plane >> 9, SR_HI) |
+ FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
+ FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
+ FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
+ FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
+ FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
+ FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
+ FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
+ FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
+ FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
} else {
- intel_uncore_write(&dev_priv->uncore, DSPFW7,
- FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
- FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
- intel_uncore_write(&dev_priv->uncore, DSPHOWM,
- FW_WM(wm->sr.plane >> 9, SR_HI) |
- FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
- FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
- FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
- FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
- FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
- FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
+ intel_de_write(display, DSPFW7,
+ FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
+ FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
+ intel_de_write(display, DSPHOWM,
+ FW_WM(wm->sr.plane >> 9, SR_HI) |
+ FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
+ FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
+ FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
+ FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
+ FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
+ FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
}
- intel_uncore_posting_read(&dev_priv->uncore, DSPFW1(dev_priv));
+ intel_de_posting_read(display, DSPFW1(display));
}
#undef FW_WM_VLV
@@ -1857,6 +1858,7 @@ static int vlv_compute_pipe_wm(struct intel_atomic_state *state,
static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
+ struct intel_display *display = to_intel_display(crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_uncore *uncore = &dev_priv->uncore;
const struct intel_crtc_state *crtc_state =
@@ -1891,8 +1893,8 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
switch (crtc->pipe) {
case PIPE_A:
- dsparb = intel_uncore_read_fw(uncore, DSPARB(dev_priv));
- dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
+ dsparb = intel_de_read_fw(display, DSPARB(display));
+ dsparb2 = intel_de_read_fw(display, DSPARB2);
dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
VLV_FIFO(SPRITEB, 0xff));
@@ -1904,12 +1906,12 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
- intel_uncore_write_fw(uncore, DSPARB(dev_priv), dsparb);
- intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
+ intel_de_write_fw(display, DSPARB(display), dsparb);
+ intel_de_write_fw(display, DSPARB2, dsparb2);
break;
case PIPE_B:
- dsparb = intel_uncore_read_fw(uncore, DSPARB(dev_priv));
- dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
+ dsparb = intel_de_read_fw(display, DSPARB(display));
+ dsparb2 = intel_de_read_fw(display, DSPARB2);
dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
VLV_FIFO(SPRITED, 0xff));
@@ -1921,12 +1923,12 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
- intel_uncore_write_fw(uncore, DSPARB(dev_priv), dsparb);
- intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
+ intel_de_write_fw(display, DSPARB(display), dsparb);
+ intel_de_write_fw(display, DSPARB2, dsparb2);
break;
case PIPE_C:
- dsparb3 = intel_uncore_read_fw(uncore, DSPARB3);
- dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
+ dsparb3 = intel_de_read_fw(display, DSPARB3);
+ dsparb2 = intel_de_read_fw(display, DSPARB2);
dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
VLV_FIFO(SPRITEF, 0xff));
@@ -1938,14 +1940,14 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
- intel_uncore_write_fw(uncore, DSPARB3, dsparb3);
- intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
+ intel_de_write_fw(display, DSPARB3, dsparb3);
+ intel_de_write_fw(display, DSPARB2, dsparb2);
break;
default:
break;
}
- intel_uncore_posting_read_fw(uncore, DSPARB(dev_priv));
+ intel_de_read_fw(display, DSPARB(display));
spin_unlock(&uncore->lock);
}
@@ -2186,17 +2188,17 @@ static void i965_update_wm(struct intel_display *display)
srwm);
/* 965 has limitations... */
- intel_uncore_write(&dev_priv->uncore, DSPFW1(dev_priv),
- FW_WM(srwm, SR) |
- FW_WM(8, CURSORB) |
- FW_WM(8, PLANEB) |
- FW_WM(8, PLANEA));
- intel_uncore_write(&dev_priv->uncore, DSPFW2(dev_priv),
- FW_WM(8, CURSORA) |
- FW_WM(8, PLANEC_OLD));
+ intel_de_write(display, DSPFW1(display),
+ FW_WM(srwm, SR) |
+ FW_WM(8, CURSORB) |
+ FW_WM(8, PLANEB) |
+ FW_WM(8, PLANEA));
+ intel_de_write(display, DSPFW2(display),
+ FW_WM(8, CURSORA) |
+ FW_WM(8, PLANEC_OLD));
/* update cursor SR watermark */
- intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv),
- FW_WM(cursor_sr, CURSOR_SR));
+ intel_de_write(display, DSPFW3(display),
+ FW_WM(cursor_sr, CURSOR_SR));
if (cxsr_enabled)
intel_set_memory_cxsr(display, true);
@@ -2339,10 +2341,10 @@ static void i9xx_update_wm(struct intel_display *display)
srwm = 1;
if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
- intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF,
- FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
+ intel_de_write(display, FW_BLC_SELF,
+ FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
else
- intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, srwm & 0x3f);
+ intel_de_write(display, FW_BLC_SELF, srwm & 0x3f);
}
drm_dbg_kms(&dev_priv->drm,
@@ -2356,8 +2358,8 @@ static void i9xx_update_wm(struct intel_display *display)
fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
fwater_hi = fwater_hi | (1 << 8);
- intel_uncore_write(&dev_priv->uncore, FW_BLC, fwater_lo);
- intel_uncore_write(&dev_priv->uncore, FW_BLC2, fwater_hi);
+ intel_de_write(display, FW_BLC, fwater_lo);
+ intel_de_write(display, FW_BLC2, fwater_hi);
if (crtc)
intel_set_memory_cxsr(display, true);
@@ -2378,13 +2380,13 @@ static void i845_update_wm(struct intel_display *display)
&i845_wm_info,
i845_get_fifo_size(dev_priv, PLANE_A),
4, pessimal_latency_ns);
- fwater_lo = intel_uncore_read(&dev_priv->uncore, FW_BLC) & ~0xfff;
+ fwater_lo = intel_de_read(display, FW_BLC) & ~0xfff;
fwater_lo |= (3<<8) | planea_wm;
drm_dbg_kms(&dev_priv->drm,
"Setting FIFO watermarks - A: %d\n", planea_wm);
- intel_uncore_write(&dev_priv->uncore, FW_BLC, fwater_lo);
+ intel_de_write(display, FW_BLC, fwater_lo);
}
/* latency must be in 0.1us units. */
@@ -3326,22 +3328,23 @@ static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
unsigned int dirty)
{
+ struct intel_display *display = &dev_priv->display;
struct ilk_wm_values *previous = &dev_priv->display.wm.hw;
bool changed = false;
if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM_LP_ENABLE) {
previous->wm_lp[2] &= ~WM_LP_ENABLE;
- intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, previous->wm_lp[2]);
+ intel_de_write(display, WM3_LP_ILK, previous->wm_lp[2]);
changed = true;
}
if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM_LP_ENABLE) {
previous->wm_lp[1] &= ~WM_LP_ENABLE;
- intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, previous->wm_lp[1]);
+ intel_de_write(display, WM2_LP_ILK, previous->wm_lp[1]);
changed = true;
}
if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM_LP_ENABLE) {
previous->wm_lp[0] &= ~WM_LP_ENABLE;
- intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, previous->wm_lp[0]);
+ intel_de_write(display, WM1_LP_ILK, previous->wm_lp[0]);
changed = true;
}
@@ -3360,6 +3363,7 @@ static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
struct ilk_wm_values *results)
{
+ struct intel_display *display = &dev_priv->display;
struct ilk_wm_values *previous = &dev_priv->display.wm.hw;
unsigned int dirty;
@@ -3370,44 +3374,44 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
_ilk_disable_lp_wm(dev_priv, dirty);
if (dirty & WM_DIRTY_PIPE(PIPE_A))
- intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
+ intel_de_write(display, WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
if (dirty & WM_DIRTY_PIPE(PIPE_B))
- intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);
+ intel_de_write(display, WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);
if (dirty & WM_DIRTY_PIPE(PIPE_C))
- intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);
+ intel_de_write(display, WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);
if (dirty & WM_DIRTY_DDB) {
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- intel_uncore_rmw(&dev_priv->uncore, WM_MISC, WM_MISC_DATA_PARTITION_5_6,
- results->partitioning == INTEL_DDB_PART_1_2 ? 0 :
- WM_MISC_DATA_PARTITION_5_6);
+ intel_de_rmw(display, WM_MISC, WM_MISC_DATA_PARTITION_5_6,
+ results->partitioning == INTEL_DDB_PART_1_2 ? 0 :
+ WM_MISC_DATA_PARTITION_5_6);
else
- intel_uncore_rmw(&dev_priv->uncore, DISP_ARB_CTL2, DISP_DATA_PARTITION_5_6,
- results->partitioning == INTEL_DDB_PART_1_2 ? 0 :
- DISP_DATA_PARTITION_5_6);
+ intel_de_rmw(display, DISP_ARB_CTL2, DISP_DATA_PARTITION_5_6,
+ results->partitioning == INTEL_DDB_PART_1_2 ? 0 :
+ DISP_DATA_PARTITION_5_6);
}
if (dirty & WM_DIRTY_FBC)
- intel_uncore_rmw(&dev_priv->uncore, DISP_ARB_CTL, DISP_FBC_WM_DIS,
- results->enable_fbc_wm ? 0 : DISP_FBC_WM_DIS);
+ intel_de_rmw(display, DISP_ARB_CTL, DISP_FBC_WM_DIS,
+ results->enable_fbc_wm ? 0 : DISP_FBC_WM_DIS);
if (dirty & WM_DIRTY_LP(1) &&
previous->wm_lp_spr[0] != results->wm_lp_spr[0])
- intel_uncore_write(&dev_priv->uncore, WM1S_LP_ILK, results->wm_lp_spr[0]);
+ intel_de_write(display, WM1S_LP_ILK, results->wm_lp_spr[0]);
if (DISPLAY_VER(dev_priv) >= 7) {
if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
- intel_uncore_write(&dev_priv->uncore, WM2S_LP_IVB, results->wm_lp_spr[1]);
+ intel_de_write(display, WM2S_LP_IVB, results->wm_lp_spr[1]);
if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
- intel_uncore_write(&dev_priv->uncore, WM3S_LP_IVB, results->wm_lp_spr[2]);
+ intel_de_write(display, WM3S_LP_IVB, results->wm_lp_spr[2]);
}
if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
- intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, results->wm_lp[0]);
+ intel_de_write(display, WM1_LP_ILK, results->wm_lp[0]);
if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
- intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, results->wm_lp[1]);
+ intel_de_write(display, WM2_LP_ILK, results->wm_lp[1]);
if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
- intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, results->wm_lp[2]);
+ intel_de_write(display, WM3_LP_ILK, results->wm_lp[2]);
dev_priv->display.wm.hw = *results;
}
@@ -3500,6 +3504,7 @@ static void ilk_optimize_watermarks(struct intel_atomic_state *state,
static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
{
+ struct intel_display *display = to_intel_display(crtc);
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct ilk_wm_values *hw = &dev_priv->display.wm.hw;
@@ -3507,7 +3512,7 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
enum pipe pipe = crtc->pipe;
- hw->wm_pipe[pipe] = intel_uncore_read(&dev_priv->uncore, WM0_PIPE_ILK(pipe));
+ hw->wm_pipe[pipe] = intel_de_read(display, WM0_PIPE_ILK(pipe));
memset(active, 0, sizeof(*active));
@@ -3672,15 +3677,16 @@ void ilk_wm_sanitize(struct intel_display *display)
static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
struct g4x_wm_values *wm)
{
+ struct intel_display *display = &dev_priv->display;
u32 tmp;
- tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1(dev_priv));
+ tmp = intel_de_read(display, DSPFW1(display));
wm->sr.plane = _FW_WM(tmp, SR);
wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
- tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2(dev_priv));
+ tmp = intel_de_read(display, DSPFW2(display));
wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
wm->sr.fbc = _FW_WM(tmp, FBC_SR);
wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
@@ -3688,7 +3694,7 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
- tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3(dev_priv));
+ tmp = intel_de_read(display, DSPFW3(display));
wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
@@ -3698,11 +3704,12 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
struct vlv_wm_values *wm)
{
+ struct intel_display *display = &dev_priv->display;
enum pipe pipe;
u32 tmp;
for_each_pipe(dev_priv, pipe) {
- tmp = intel_uncore_read(&dev_priv->uncore, VLV_DDL(pipe));
+ tmp = intel_de_read(display, VLV_DDL(pipe));
wm->ddl[pipe].plane[PLANE_PRIMARY] =
(tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
@@ -3714,34 +3721,34 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
(tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
}
- tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1(dev_priv));
+ tmp = intel_de_read(display, DSPFW1(display));
wm->sr.plane = _FW_WM(tmp, SR);
wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
- tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2(dev_priv));
+ tmp = intel_de_read(display, DSPFW2(display));
wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
- tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3(dev_priv));
+ tmp = intel_de_read(display, DSPFW3(display));
wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
if (IS_CHERRYVIEW(dev_priv)) {
- tmp = intel_uncore_read(&dev_priv->uncore, DSPFW7_CHV);
+ tmp = intel_de_read(display, DSPFW7_CHV);
wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
- tmp = intel_uncore_read(&dev_priv->uncore, DSPFW8_CHV);
+ tmp = intel_de_read(display, DSPFW8_CHV);
wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
- tmp = intel_uncore_read(&dev_priv->uncore, DSPFW9_CHV);
+ tmp = intel_de_read(display, DSPFW9_CHV);
wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
- tmp = intel_uncore_read(&dev_priv->uncore, DSPHOWM);
+ tmp = intel_de_read(display, DSPHOWM);
wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
@@ -3753,11 +3760,11 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
} else {
- tmp = intel_uncore_read(&dev_priv->uncore, DSPFW7);
+ tmp = intel_de_read(display, DSPFW7);
wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
- tmp = intel_uncore_read(&dev_priv->uncore, DSPHOWM);
+ tmp = intel_de_read(display, DSPHOWM);
wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
@@ -3779,7 +3786,7 @@ static void g4x_wm_get_hw_state(struct intel_display *display)
g4x_read_wm_values(dev_priv, wm);
- wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
+ wm->cxsr = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
for_each_intel_crtc(&dev_priv->drm, crtc) {
struct intel_crtc_state *crtc_state =
@@ -3924,7 +3931,7 @@ static void vlv_wm_get_hw_state(struct intel_display *display)
vlv_read_wm_values(dev_priv, wm);
- wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
+ wm->cxsr = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
wm->level = VLV_WM_LEVEL_PM2;
if (IS_CHERRYVIEW(dev_priv)) {
@@ -4069,9 +4076,11 @@ static void vlv_wm_sanitize(struct intel_display *display)
*/
static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
{
- intel_uncore_rmw(&dev_priv->uncore, WM3_LP_ILK, WM_LP_ENABLE, 0);
- intel_uncore_rmw(&dev_priv->uncore, WM2_LP_ILK, WM_LP_ENABLE, 0);
- intel_uncore_rmw(&dev_priv->uncore, WM1_LP_ILK, WM_LP_ENABLE, 0);
+ struct intel_display *display = &dev_priv->display;
+
+ intel_de_rmw(display, WM3_LP_ILK, WM_LP_ENABLE, 0);
+ intel_de_rmw(display, WM2_LP_ILK, WM_LP_ENABLE, 0);
+ intel_de_rmw(display, WM1_LP_ILK, WM_LP_ENABLE, 0);
/*
* Don't touch WM_LP_SPRITE_ENABLE here.
@@ -4090,27 +4099,27 @@ static void ilk_wm_get_hw_state(struct intel_display *display)
for_each_intel_crtc(&dev_priv->drm, crtc)
ilk_pipe_wm_get_hw_state(crtc);
- hw->wm_lp[0] = intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK);
- hw->wm_lp[1] = intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK);
- hw->wm_lp[2] = intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK);
+ hw->wm_lp[0] = intel_de_read(display, WM1_LP_ILK);
+ hw->wm_lp[1] = intel_de_read(display, WM2_LP_ILK);
+ hw->wm_lp[2] = intel_de_read(display, WM3_LP_ILK);
- hw->wm_lp_spr[0] = intel_uncore_read(&dev_priv->uncore, WM1S_LP_ILK);
+ hw->wm_lp_spr[0] = intel_de_read(display, WM1S_LP_ILK);
if (DISPLAY_VER(dev_priv) >= 7) {
- hw->wm_lp_spr[1] = intel_uncore_read(&dev_priv->uncore, WM2S_LP_IVB);
- hw->wm_lp_spr[2] = intel_uncore_read(&dev_priv->uncore, WM3S_LP_IVB);
+ hw->wm_lp_spr[1] = intel_de_read(display, WM2S_LP_IVB);
+ hw->wm_lp_spr[2] = intel_de_read(display, WM3S_LP_IVB);
}
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- hw->partitioning = (intel_uncore_read(&dev_priv->uncore, WM_MISC) &
+ hw->partitioning = (intel_de_read(display, WM_MISC) &
WM_MISC_DATA_PARTITION_5_6) ?
INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
else if (IS_IVYBRIDGE(dev_priv))
- hw->partitioning = (intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2) &
+ hw->partitioning = (intel_de_read(display, DISP_ARB_CTL2) &
DISP_DATA_PARTITION_5_6) ?
INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
hw->enable_fbc_wm =
- !(intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) & DISP_FBC_WM_DIS);
+ !(intel_de_read(display, DISP_ARB_CTL) & DISP_FBC_WM_DIS);
}
static const struct intel_wm_funcs ilk_wm_funcs = {
--
2.39.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 7/7] drm/i915/wm: convert i9xx_wm.c internally to struct intel_display
2025-04-08 13:38 [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display Jani Nikula
` (5 preceding siblings ...)
2025-04-08 13:38 ` [PATCH v2 6/7] drm/i915/wm: convert i9xx_wm.c to intel_de_*() register interface Jani Nikula
@ 2025-04-08 13:38 ` Jani Nikula
2025-04-08 14:03 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/wm: convert to struct intel_display (rev2) Patchwork
` (4 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2025-04-08 13:38 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Going forward, struct intel_display is the main display device data
pointer. Convert as much as possible of i9xx_wm.c to struct
intel_display.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 822 ++++++++++++-------------
1 file changed, 397 insertions(+), 425 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 49ded623c084..40751f1547b7 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -82,13 +82,14 @@ static const struct cxsr_latency cxsr_latency_table[] = {
{0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
};
-static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private *i915)
+static const struct cxsr_latency *pnv_get_cxsr_latency(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
int i;
for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
const struct cxsr_latency *latency = &cxsr_latency_table[i];
- bool is_desktop = !IS_MOBILE(i915);
+ bool is_desktop = !display->platform.mobile;
if (is_desktop == latency->is_desktop &&
i915->is_ddr3 == latency->is_ddr3 &&
@@ -97,15 +98,16 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private *
return latency;
}
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Could not find CxSR latency for DDR%s, FSB %u kHz, MEM %u kHz\n",
i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq);
return NULL;
}
-static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
+static void chv_set_memory_dvfs(struct intel_display *display, bool enable)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 val;
vlv_punit_get(dev_priv);
@@ -121,14 +123,15 @@ static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"timed out waiting for Punit DDR DVFS request\n");
vlv_punit_put(dev_priv);
}
-static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
+static void chv_set_memory_pm5(struct intel_display *display, bool enable)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 val;
vlv_punit_get(dev_priv);
@@ -146,21 +149,20 @@ static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
#define FW_WM(value, plane) \
(((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
-static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
+static bool _intel_set_memory_cxsr(struct intel_display *display, bool enable)
{
- struct intel_display *display = &dev_priv->display;
bool was_enabled;
u32 val;
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+ if (display->platform.valleyview || display->platform.cherryview) {
was_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
intel_de_write(display, FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
intel_de_posting_read(display, FW_BLC_SELF_VLV);
- } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
+ } else if (display->platform.g4x || display->platform.i965gm) {
was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
intel_de_write(display, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
intel_de_posting_read(display, FW_BLC_SELF);
- } else if (IS_PINEVIEW(dev_priv)) {
+ } else if (display->platform.pineview) {
val = intel_de_read(display, DSPFW3(display));
was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
if (enable)
@@ -169,13 +171,13 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl
val &= ~PINEVIEW_SELF_REFRESH_EN;
intel_de_write(display, DSPFW3(display), val);
intel_de_posting_read(display, DSPFW3(display));
- } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
+ } else if (display->platform.i945g || display->platform.i945gm) {
was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
_MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
intel_de_write(display, FW_BLC_SELF, val);
intel_de_posting_read(display, FW_BLC_SELF);
- } else if (IS_I915GM(dev_priv)) {
+ } else if (display->platform.i915gm) {
/*
* FIXME can't find a bit like this for 915G, and
* yet it does have the related watermark in
@@ -192,7 +194,7 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl
trace_intel_memory_cxsr(display, was_enabled, enable);
- drm_dbg_kms(&dev_priv->drm, "memory self-refresh is %s (was %s)\n",
+ drm_dbg_kms(display->drm, "memory self-refresh is %s (was %s)\n",
str_enabled_disabled(enable),
str_enabled_disabled(was_enabled));
@@ -238,16 +240,15 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl
*/
bool intel_set_memory_cxsr(struct intel_display *display, bool enable)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
bool ret;
- mutex_lock(&dev_priv->display.wm.wm_mutex);
- ret = _intel_set_memory_cxsr(dev_priv, enable);
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- dev_priv->display.wm.vlv.cxsr = enable;
- else if (IS_G4X(dev_priv))
- dev_priv->display.wm.g4x.cxsr = enable;
- mutex_unlock(&dev_priv->display.wm.wm_mutex);
+ mutex_lock(&display->wm.wm_mutex);
+ ret = _intel_set_memory_cxsr(display, enable);
+ if (display->platform.valleyview || display->platform.cherryview)
+ display->wm.vlv.cxsr = enable;
+ else if (display->platform.g4x)
+ display->wm.g4x.cxsr = enable;
+ mutex_unlock(&display->wm.wm_mutex);
return ret;
}
@@ -310,10 +311,9 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
fifo_state->plane[PLANE_CURSOR] = 63;
}
-static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
+static int i9xx_get_fifo_size(struct intel_display *display,
enum i9xx_plane_id i9xx_plane)
{
- struct intel_display *display = &dev_priv->display;
u32 dsparb = intel_de_read(display, DSPARB(display));
int size;
@@ -321,16 +321,15 @@ static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
if (i9xx_plane == PLANE_B)
size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
- drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n",
+ drm_dbg_kms(display->drm, "FIFO size - (0x%08x) %c: %d\n",
dsparb, plane_name(i9xx_plane), size);
return size;
}
-static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
+static int i830_get_fifo_size(struct intel_display *display,
enum i9xx_plane_id i9xx_plane)
{
- struct intel_display *display = &dev_priv->display;
u32 dsparb = intel_de_read(display, DSPARB(display));
int size;
@@ -339,23 +338,22 @@ static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
size >>= 1; /* Convert to cachelines */
- drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n",
+ drm_dbg_kms(display->drm, "FIFO size - (0x%08x) %c: %d\n",
dsparb, plane_name(i9xx_plane), size);
return size;
}
-static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
+static int i845_get_fifo_size(struct intel_display *display,
enum i9xx_plane_id i9xx_plane)
{
- struct intel_display *display = &dev_priv->display;
u32 dsparb = intel_de_read(display, DSPARB(display));
int size;
size = dsparb & 0x7f;
size >>= 2; /* Convert to cachelines */
- drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n",
+ drm_dbg_kms(display->drm, "FIFO size - (0x%08x) %c: %d\n",
dsparb, plane_name(i9xx_plane), size);
return size;
@@ -540,7 +538,7 @@ static unsigned int intel_wm_method2(unsigned int pixel_rate,
/**
* intel_calculate_wm - calculate watermark level
- * @i915: the device
+ * @display: display device
* @pixel_rate: pixel clock
* @wm: chip FIFO params
* @fifo_size: size of the FIFO buffer
@@ -558,7 +556,7 @@ static unsigned int intel_wm_method2(unsigned int pixel_rate,
* past the watermark point. If the FIFO drains completely, a FIFO underrun
* will occur, and a display engine hang could result.
*/
-static unsigned int intel_calculate_wm(struct drm_i915_private *i915,
+static unsigned int intel_calculate_wm(struct intel_display *display,
int pixel_rate,
const struct intel_watermark_params *wm,
int fifo_size, int cpp,
@@ -576,10 +574,10 @@ static unsigned int intel_calculate_wm(struct drm_i915_private *i915,
latency_ns / 100);
entries = DIV_ROUND_UP(entries, wm->cacheline_size) +
wm->guard_size;
- drm_dbg_kms(&i915->drm, "FIFO entries required for mode: %d\n", entries);
+ drm_dbg_kms(display->drm, "FIFO entries required for mode: %d\n", entries);
wm_size = fifo_size - entries;
- drm_dbg_kms(&i915->drm, "FIFO watermark level: %d\n", wm_size);
+ drm_dbg_kms(display->drm, "FIFO watermark level: %d\n", wm_size);
/* Don't promote wm_size to unsigned... */
if (wm_size > wm->max_wm)
@@ -629,11 +627,11 @@ static bool intel_crtc_active(struct intel_crtc *crtc)
crtc->config->hw.adjusted_mode.crtc_clock;
}
-static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
+static struct intel_crtc *single_enabled_crtc(struct intel_display *display)
{
struct intel_crtc *crtc, *enabled = NULL;
- for_each_intel_crtc(&dev_priv->drm, crtc) {
+ for_each_intel_crtc(display->drm, crtc) {
if (intel_crtc_active(crtc)) {
if (enabled)
return NULL;
@@ -646,20 +644,19 @@ static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
static void pnv_update_wm(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_crtc *crtc;
const struct cxsr_latency *latency;
u32 reg;
unsigned int wm;
- latency = pnv_get_cxsr_latency(dev_priv);
+ latency = pnv_get_cxsr_latency(display);
if (!latency) {
- drm_dbg_kms(&dev_priv->drm, "Unknown FSB/MEM, disabling CxSR\n");
+ drm_dbg_kms(display->drm, "Unknown FSB/MEM, disabling CxSR\n");
intel_set_memory_cxsr(display, false);
return;
}
- crtc = single_enabled_crtc(dev_priv);
+ crtc = single_enabled_crtc(display);
if (crtc) {
const struct drm_framebuffer *fb =
crtc->base.primary->state->fb;
@@ -667,7 +664,7 @@ static void pnv_update_wm(struct intel_display *display)
int cpp = fb->format->cpp[0];
/* Display SR */
- wm = intel_calculate_wm(dev_priv, pixel_rate,
+ wm = intel_calculate_wm(display, pixel_rate,
&pnv_display_wm,
pnv_display_wm.fifo_size,
cpp, latency->display_sr);
@@ -675,10 +672,10 @@ static void pnv_update_wm(struct intel_display *display)
reg &= ~DSPFW_SR_MASK;
reg |= FW_WM(wm, SR);
intel_de_write(display, DSPFW1(display), reg);
- drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg);
+ drm_dbg_kms(display->drm, "DSPFW1 register is %x\n", reg);
/* cursor SR */
- wm = intel_calculate_wm(dev_priv, pixel_rate,
+ wm = intel_calculate_wm(display, pixel_rate,
&pnv_cursor_wm,
pnv_display_wm.fifo_size,
4, latency->cursor_sr);
@@ -686,7 +683,7 @@ static void pnv_update_wm(struct intel_display *display)
DSPFW_CURSOR_SR_MASK, FW_WM(wm, CURSOR_SR));
/* Display HPLL off SR */
- wm = intel_calculate_wm(dev_priv, pixel_rate,
+ wm = intel_calculate_wm(display, pixel_rate,
&pnv_display_hplloff_wm,
pnv_display_hplloff_wm.fifo_size,
cpp, latency->display_hpll_disable);
@@ -694,7 +691,7 @@ static void pnv_update_wm(struct intel_display *display)
DSPFW_HPLL_SR_MASK, FW_WM(wm, HPLL_SR));
/* cursor HPLL off SR */
- wm = intel_calculate_wm(dev_priv, pixel_rate,
+ wm = intel_calculate_wm(display, pixel_rate,
&pnv_cursor_hplloff_wm,
pnv_display_hplloff_wm.fifo_size,
4, latency->cursor_hpll_disable);
@@ -702,7 +699,7 @@ static void pnv_update_wm(struct intel_display *display)
reg &= ~DSPFW_HPLL_CURSOR_MASK;
reg |= FW_WM(wm, HPLL_CURSOR);
intel_de_write(display, DSPFW3(display), reg);
- drm_dbg_kms(&dev_priv->drm, "DSPFW3 register is %x\n", reg);
+ drm_dbg_kms(display->drm, "DSPFW3 register is %x\n", reg);
intel_set_memory_cxsr(display, true);
} else {
@@ -797,13 +794,12 @@ static unsigned int g4x_tlb_miss_wa(int fifo_size, int width, int cpp)
return max(0, tlb_miss);
}
-static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
+static void g4x_write_wm_values(struct intel_display *display,
const struct g4x_wm_values *wm)
{
- struct intel_display *display = &dev_priv->display;
enum pipe pipe;
- for_each_pipe(dev_priv, pipe)
+ for_each_pipe(display, pipe)
trace_g4x_wm(intel_crtc_for_pipe(display, pipe), wm);
intel_de_write(display, DSPFW1(display),
@@ -830,13 +826,12 @@ static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
#define FW_WM_VLV(value, plane) \
(((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
-static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
+static void vlv_write_wm_values(struct intel_display *display,
const struct vlv_wm_values *wm)
{
- struct intel_display *display = &dev_priv->display;
enum pipe pipe;
- for_each_pipe(dev_priv, pipe) {
+ for_each_pipe(display, pipe) {
trace_vlv_wm(intel_crtc_for_pipe(display, pipe), wm);
intel_de_write(display, VLV_DDL(pipe),
@@ -869,7 +864,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
intel_de_write(display, DSPFW3(display),
FW_WM(wm->sr.cursor, CURSOR_SR));
- if (IS_CHERRYVIEW(dev_priv)) {
+ if (display->platform.cherryview) {
intel_de_write(display, DSPFW7_CHV,
FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
@@ -909,14 +904,14 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
#undef FW_WM_VLV
-static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv)
+static void g4x_setup_wm_latency(struct intel_display *display)
{
/* all latencies in usec */
- dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
- dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
- dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
+ display->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
+ display->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
+ display->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
- dev_priv->display.wm.num_levels = G4X_WM_LEVEL_HPLL + 1;
+ display->wm.num_levels = G4X_WM_LEVEL_HPLL + 1;
}
static int g4x_plane_fifo_size(enum plane_id plane_id, int level)
@@ -965,11 +960,11 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
int level)
{
+ struct intel_display *display = to_intel_display(plane_state);
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_display_mode *pipe_mode =
&crtc_state->hw.pipe_mode;
- unsigned int latency = dev_priv->display.wm.pri_latency[level] * 10;
+ unsigned int latency = display->wm.pri_latency[level] * 10;
unsigned int pixel_rate, htotal, cpp, width, wm;
if (latency == 0)
@@ -1020,10 +1015,10 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
int level, enum plane_id plane_id, u16 value)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
bool dirty = false;
- for (; level < dev_priv->display.wm.num_levels; level++) {
+ for (; level < display->wm.num_levels; level++) {
struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
dirty |= raw->plane[plane_id] != value;
@@ -1036,13 +1031,13 @@ static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
int level, u16 value)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
bool dirty = false;
/* NORMAL level doesn't have an FBC watermark */
level = max(level, G4X_WM_LEVEL_SR);
- for (; level < dev_priv->display.wm.num_levels; level++) {
+ for (; level < display->wm.num_levels; level++) {
struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
dirty |= raw->fbc != value;
@@ -1059,8 +1054,8 @@ static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
enum plane_id plane_id = plane->id;
bool dirty = false;
int level;
@@ -1072,7 +1067,7 @@ static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
goto out;
}
- for (level = 0; level < dev_priv->display.wm.num_levels; level++) {
+ for (level = 0; level < display->wm.num_levels; level++) {
struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
int wm, max_wm;
@@ -1112,7 +1107,7 @@ static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
out:
if (dirty) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"%s watermarks: normal=%d, SR=%d, HPLL=%d\n",
plane->base.name,
crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],
@@ -1120,7 +1115,7 @@ static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
if (plane_id == PLANE_PRIMARY)
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"FBC watermarks: SR=%d, HPLL=%d\n",
crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,
crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
@@ -1140,9 +1135,9 @@ static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
int level)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
- if (level >= dev_priv->display.wm.num_levels)
+ if (level >= display->wm.num_levels)
return false;
return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
@@ -1284,7 +1279,7 @@ static int g4x_compute_pipe_wm(struct intel_atomic_state *state,
static int g4x_compute_intermediate_wm(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(state);
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_crtc_state *old_crtc_state =
@@ -1314,7 +1309,7 @@ static int g4x_compute_intermediate_wm(struct intel_atomic_state *state,
max(optimal->wm.plane[plane_id],
active->wm.plane[plane_id]);
- drm_WARN_ON(&dev_priv->drm, intermediate->wm.plane[plane_id] >
+ drm_WARN_ON(display->drm, intermediate->wm.plane[plane_id] >
g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL));
}
@@ -1332,23 +1327,23 @@ static int g4x_compute_intermediate_wm(struct intel_atomic_state *state,
intermediate->hpll.fbc = max(optimal->hpll.fbc,
active->hpll.fbc);
- drm_WARN_ON(&dev_priv->drm,
+ drm_WARN_ON(display->drm,
(intermediate->sr.plane >
g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_SR) ||
intermediate->sr.cursor >
g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_SR)) &&
intermediate->cxsr);
- drm_WARN_ON(&dev_priv->drm,
+ drm_WARN_ON(display->drm,
(intermediate->sr.plane >
g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) ||
intermediate->sr.cursor >
g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) &&
intermediate->hpll_en);
- drm_WARN_ON(&dev_priv->drm,
+ drm_WARN_ON(display->drm,
intermediate->sr.fbc > g4x_fbc_fifo_size(1) &&
intermediate->fbc_en && intermediate->cxsr);
- drm_WARN_ON(&dev_priv->drm,
+ drm_WARN_ON(display->drm,
intermediate->hpll.fbc > g4x_fbc_fifo_size(2) &&
intermediate->fbc_en && intermediate->hpll_en);
@@ -1379,7 +1374,7 @@ static int g4x_compute_watermarks(struct intel_atomic_state *state,
return 0;
}
-static void g4x_merge_wm(struct drm_i915_private *dev_priv,
+static void g4x_merge_wm(struct intel_display *display,
struct g4x_wm_values *wm)
{
struct intel_crtc *crtc;
@@ -1389,7 +1384,7 @@ static void g4x_merge_wm(struct drm_i915_private *dev_priv,
wm->hpll_en = true;
wm->fbc_en = true;
- for_each_intel_crtc(&dev_priv->drm, crtc) {
+ for_each_intel_crtc(display->drm, crtc) {
const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
if (!crtc->active)
@@ -1411,7 +1406,7 @@ static void g4x_merge_wm(struct drm_i915_private *dev_priv,
wm->fbc_en = false;
}
- for_each_intel_crtc(&dev_priv->drm, crtc) {
+ for_each_intel_crtc(display->drm, crtc) {
const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
enum pipe pipe = crtc->pipe;
@@ -1423,23 +1418,23 @@ static void g4x_merge_wm(struct drm_i915_private *dev_priv,
}
}
-static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
+static void g4x_program_watermarks(struct intel_display *display)
{
- struct g4x_wm_values *old_wm = &dev_priv->display.wm.g4x;
+ struct g4x_wm_values *old_wm = &display->wm.g4x;
struct g4x_wm_values new_wm = {};
- g4x_merge_wm(dev_priv, &new_wm);
+ g4x_merge_wm(display, &new_wm);
if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
return;
if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
- _intel_set_memory_cxsr(dev_priv, false);
+ _intel_set_memory_cxsr(display, false);
- g4x_write_wm_values(dev_priv, &new_wm);
+ g4x_write_wm_values(display, &new_wm);
if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
- _intel_set_memory_cxsr(dev_priv, true);
+ _intel_set_memory_cxsr(display, true);
*old_wm = new_wm;
}
@@ -1447,30 +1442,30 @@ static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
static void g4x_initial_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
const struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- mutex_lock(&dev_priv->display.wm.wm_mutex);
+ mutex_lock(&display->wm.wm_mutex);
crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
- g4x_program_watermarks(dev_priv);
- mutex_unlock(&dev_priv->display.wm.wm_mutex);
+ g4x_program_watermarks(display);
+ mutex_unlock(&display->wm.wm_mutex);
}
static void g4x_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
const struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
if (!crtc_state->wm.need_postvbl_update)
return;
- mutex_lock(&dev_priv->display.wm.wm_mutex);
+ mutex_lock(&display->wm.wm_mutex);
crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
- g4x_program_watermarks(dev_priv);
- mutex_unlock(&dev_priv->display.wm.wm_mutex);
+ g4x_program_watermarks(display);
+ mutex_unlock(&display->wm.wm_mutex);
}
/* latency must be in 0.1us units. */
@@ -1489,18 +1484,18 @@ static unsigned int vlv_wm_method2(unsigned int pixel_rate,
return ret;
}
-static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
+static void vlv_setup_wm_latency(struct intel_display *display)
{
/* all latencies in usec */
- dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
+ display->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
- dev_priv->display.wm.num_levels = VLV_WM_LEVEL_PM2 + 1;
+ display->wm.num_levels = VLV_WM_LEVEL_PM2 + 1;
- if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
- dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
+ if (display->platform.cherryview) {
+ display->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
+ display->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
- dev_priv->display.wm.num_levels = VLV_WM_LEVEL_DDR_DVFS + 1;
+ display->wm.num_levels = VLV_WM_LEVEL_DDR_DVFS + 1;
}
}
@@ -1508,13 +1503,13 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
int level)
{
+ struct intel_display *display = to_intel_display(plane_state);
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_display_mode *pipe_mode =
&crtc_state->hw.pipe_mode;
unsigned int pixel_rate, htotal, cpp, width, wm;
- if (dev_priv->display.wm.pri_latency[level] == 0)
+ if (display->wm.pri_latency[level] == 0)
return USHRT_MAX;
if (!intel_wm_plane_visible(crtc_state, plane_state))
@@ -1535,7 +1530,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
wm = 63;
} else {
wm = vlv_wm_method2(pixel_rate, htotal, width, cpp,
- dev_priv->display.wm.pri_latency[level] * 10);
+ display->wm.pri_latency[level] * 10);
}
return min_t(unsigned int, wm, USHRT_MAX);
@@ -1549,8 +1544,8 @@ static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct g4x_pipe_wm *raw =
&crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
@@ -1619,11 +1614,11 @@ static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
fifo_left -= plane_extra;
}
- drm_WARN_ON(&dev_priv->drm, active_planes != 0 && fifo_left != 0);
+ drm_WARN_ON(display->drm, active_planes != 0 && fifo_left != 0);
/* give it all to the first plane if none are active */
if (active_planes == 0) {
- drm_WARN_ON(&dev_priv->drm, fifo_left != fifo_size);
+ drm_WARN_ON(display->drm, fifo_left != fifo_size);
fifo_state->plane[PLANE_PRIMARY] = fifo_left;
}
@@ -1634,9 +1629,9 @@ static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
static void vlv_invalidate_wms(struct intel_crtc *crtc,
struct vlv_wm_state *wm_state, int level)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
- for (; level < dev_priv->display.wm.num_levels; level++) {
+ for (; level < display->wm.num_levels; level++) {
enum plane_id plane_id;
for_each_plane_id_on_crtc(crtc, plane_id)
@@ -1662,10 +1657,10 @@ static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
int level, enum plane_id plane_id, u16 value)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
bool dirty = false;
- for (; level < dev_priv->display.wm.num_levels; level++) {
+ for (; level < display->wm.num_levels; level++) {
struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
dirty |= raw->plane[plane_id] != value;
@@ -1678,8 +1673,8 @@ static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
enum plane_id plane_id = plane->id;
int level;
bool dirty = false;
@@ -1689,7 +1684,7 @@ static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
goto out;
}
- for (level = 0; level < dev_priv->display.wm.num_levels; level++) {
+ for (level = 0; level < display->wm.num_levels; level++) {
struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
int wm = vlv_compute_wm_level(crtc_state, plane_state, level);
int max_wm = plane_id == PLANE_CURSOR ? 63 : 511;
@@ -1706,7 +1701,7 @@ static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
out:
if (dirty)
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n",
plane->base.name,
crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
@@ -1737,8 +1732,8 @@ static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
static int _vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
const struct vlv_fifo_state *fifo_state =
&crtc_state->wm.vlv.fifo_state;
@@ -1748,7 +1743,7 @@ static int _vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
int level;
/* initially allow all levels */
- wm_state->num_levels = dev_priv->display.wm.num_levels;
+ wm_state->num_levels = display->wm.num_levels;
/*
* Note that enabling cxsr with no primary/sprite planes
* enabled can wedge the pipe. Hence we only allow cxsr
@@ -1758,7 +1753,7 @@ static int _vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
for (level = 0; level < wm_state->num_levels; level++) {
const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
- const int sr_fifo_size = INTEL_NUM_PIPES(dev_priv) * 512 - 1;
+ const int sr_fifo_size = INTEL_NUM_PIPES(display) * 512 - 1;
if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
break;
@@ -1875,8 +1870,8 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start;
fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start;
- drm_WARN_ON(&dev_priv->drm, fifo_state->plane[PLANE_CURSOR] != 63);
- drm_WARN_ON(&dev_priv->drm, fifo_size != 511);
+ drm_WARN_ON(display->drm, fifo_state->plane[PLANE_CURSOR] != 63);
+ drm_WARN_ON(display->drm, fifo_size != 511);
trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
@@ -2022,16 +2017,16 @@ static int vlv_compute_watermarks(struct intel_atomic_state *state,
return 0;
}
-static void vlv_merge_wm(struct drm_i915_private *dev_priv,
+static void vlv_merge_wm(struct intel_display *display,
struct vlv_wm_values *wm)
{
struct intel_crtc *crtc;
int num_active_pipes = 0;
- wm->level = dev_priv->display.wm.num_levels - 1;
+ wm->level = display->wm.num_levels - 1;
wm->cxsr = true;
- for_each_intel_crtc(&dev_priv->drm, crtc) {
+ for_each_intel_crtc(display->drm, crtc) {
const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
if (!crtc->active)
@@ -2050,7 +2045,7 @@ static void vlv_merge_wm(struct drm_i915_private *dev_priv,
if (num_active_pipes > 1)
wm->level = VLV_WM_LEVEL_PM2;
- for_each_intel_crtc(&dev_priv->drm, crtc) {
+ for_each_intel_crtc(display->drm, crtc) {
const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
enum pipe pipe = crtc->pipe;
@@ -2065,35 +2060,35 @@ static void vlv_merge_wm(struct drm_i915_private *dev_priv,
}
}
-static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
+static void vlv_program_watermarks(struct intel_display *display)
{
- struct vlv_wm_values *old_wm = &dev_priv->display.wm.vlv;
+ struct vlv_wm_values *old_wm = &display->wm.vlv;
struct vlv_wm_values new_wm = {};
- vlv_merge_wm(dev_priv, &new_wm);
+ vlv_merge_wm(display, &new_wm);
if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
return;
if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
- chv_set_memory_dvfs(dev_priv, false);
+ chv_set_memory_dvfs(display, false);
if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
- chv_set_memory_pm5(dev_priv, false);
+ chv_set_memory_pm5(display, false);
if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
- _intel_set_memory_cxsr(dev_priv, false);
+ _intel_set_memory_cxsr(display, false);
- vlv_write_wm_values(dev_priv, &new_wm);
+ vlv_write_wm_values(display, &new_wm);
if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
- _intel_set_memory_cxsr(dev_priv, true);
+ _intel_set_memory_cxsr(display, true);
if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
- chv_set_memory_pm5(dev_priv, true);
+ chv_set_memory_pm5(display, true);
if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
- chv_set_memory_dvfs(dev_priv, true);
+ chv_set_memory_dvfs(display, true);
*old_wm = new_wm;
}
@@ -2101,42 +2096,41 @@ static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
static void vlv_initial_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
const struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- mutex_lock(&dev_priv->display.wm.wm_mutex);
+ mutex_lock(&display->wm.wm_mutex);
crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
- vlv_program_watermarks(dev_priv);
- mutex_unlock(&dev_priv->display.wm.wm_mutex);
+ vlv_program_watermarks(display);
+ mutex_unlock(&display->wm.wm_mutex);
}
static void vlv_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
const struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
if (!crtc_state->wm.need_postvbl_update)
return;
- mutex_lock(&dev_priv->display.wm.wm_mutex);
+ mutex_lock(&display->wm.wm_mutex);
crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
- vlv_program_watermarks(dev_priv);
- mutex_unlock(&dev_priv->display.wm.wm_mutex);
+ vlv_program_watermarks(display);
+ mutex_unlock(&display->wm.wm_mutex);
}
static void i965_update_wm(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_crtc *crtc;
int srwm = 1;
int cursor_sr = 16;
bool cxsr_enabled;
/* Calc sr entries for one plane configs */
- crtc = single_enabled_crtc(dev_priv);
+ crtc = single_enabled_crtc(display);
if (crtc) {
/* self-refresh has much higher latency */
static const int sr_latency_ns = 12000;
@@ -2157,7 +2151,7 @@ static void i965_update_wm(struct intel_display *display)
if (srwm < 0)
srwm = 1;
srwm &= 0x1ff;
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"self-refresh entries: %d, wm: %d\n",
entries, srwm);
@@ -2172,7 +2166,7 @@ static void i965_update_wm(struct intel_display *display)
if (cursor_sr > i965_cursor_wm_info.max_wm)
cursor_sr = i965_cursor_wm_info.max_wm;
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"self-refresh watermark: display plane %d "
"cursor %d\n", srwm, cursor_sr);
@@ -2183,7 +2177,7 @@ static void i965_update_wm(struct intel_display *display)
intel_set_memory_cxsr(display, false);
}
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
srwm);
@@ -2206,13 +2200,12 @@ static void i965_update_wm(struct intel_display *display)
#undef FW_WM
-static struct intel_crtc *intel_crtc_for_plane(struct drm_i915_private *i915,
+static struct intel_crtc *intel_crtc_for_plane(struct intel_display *display,
enum i9xx_plane_id i9xx_plane)
{
- struct intel_display *display = &i915->display;
struct intel_plane *plane;
- for_each_intel_plane(&i915->drm, plane) {
+ for_each_intel_plane(display->drm, plane) {
if (plane->id == PLANE_PRIMARY &&
plane->i9xx_plane == i9xx_plane)
return intel_crtc_for_pipe(display, plane->pipe);
@@ -2223,7 +2216,6 @@ static struct intel_crtc *intel_crtc_for_plane(struct drm_i915_private *i915,
static void i9xx_update_wm(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
const struct intel_watermark_params *wm_info;
u32 fwater_lo;
u32 fwater_hi;
@@ -2232,29 +2224,29 @@ static void i9xx_update_wm(struct intel_display *display)
int planea_wm, planeb_wm;
struct intel_crtc *crtc;
- if (IS_I945GM(dev_priv))
+ if (display->platform.i945gm)
wm_info = &i945_wm_info;
- else if (DISPLAY_VER(dev_priv) != 2)
+ else if (DISPLAY_VER(display) != 2)
wm_info = &i915_wm_info;
else
wm_info = &i830_a_wm_info;
- if (DISPLAY_VER(dev_priv) == 2)
- fifo_size = i830_get_fifo_size(dev_priv, PLANE_A);
+ if (DISPLAY_VER(display) == 2)
+ fifo_size = i830_get_fifo_size(display, PLANE_A);
else
- fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_A);
- crtc = intel_crtc_for_plane(dev_priv, PLANE_A);
+ fifo_size = i9xx_get_fifo_size(display, PLANE_A);
+ crtc = intel_crtc_for_plane(display, PLANE_A);
if (intel_crtc_active(crtc)) {
const struct drm_framebuffer *fb =
crtc->base.primary->state->fb;
int cpp;
- if (DISPLAY_VER(dev_priv) == 2)
+ if (DISPLAY_VER(display) == 2)
cpp = 4;
else
cpp = fb->format->cpp[0];
- planea_wm = intel_calculate_wm(dev_priv, crtc->config->pixel_rate,
+ planea_wm = intel_calculate_wm(display, crtc->config->pixel_rate,
wm_info, fifo_size, cpp,
pessimal_latency_ns);
} else {
@@ -2263,25 +2255,25 @@ static void i9xx_update_wm(struct intel_display *display)
planea_wm = wm_info->max_wm;
}
- if (DISPLAY_VER(dev_priv) == 2)
+ if (DISPLAY_VER(display) == 2)
wm_info = &i830_bc_wm_info;
- if (DISPLAY_VER(dev_priv) == 2)
- fifo_size = i830_get_fifo_size(dev_priv, PLANE_B);
+ if (DISPLAY_VER(display) == 2)
+ fifo_size = i830_get_fifo_size(display, PLANE_B);
else
- fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_B);
- crtc = intel_crtc_for_plane(dev_priv, PLANE_B);
+ fifo_size = i9xx_get_fifo_size(display, PLANE_B);
+ crtc = intel_crtc_for_plane(display, PLANE_B);
if (intel_crtc_active(crtc)) {
const struct drm_framebuffer *fb =
crtc->base.primary->state->fb;
int cpp;
- if (DISPLAY_VER(dev_priv) == 2)
+ if (DISPLAY_VER(display) == 2)
cpp = 4;
else
cpp = fb->format->cpp[0];
- planeb_wm = intel_calculate_wm(dev_priv, crtc->config->pixel_rate,
+ planeb_wm = intel_calculate_wm(display, crtc->config->pixel_rate,
wm_info, fifo_size, cpp,
pessimal_latency_ns);
} else {
@@ -2290,11 +2282,11 @@ static void i9xx_update_wm(struct intel_display *display)
planeb_wm = wm_info->max_wm;
}
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
- crtc = single_enabled_crtc(dev_priv);
- if (IS_I915GM(dev_priv) && crtc) {
+ crtc = single_enabled_crtc(display);
+ if (display->platform.i915gm && crtc) {
struct drm_gem_object *obj;
obj = intel_fb_bo(crtc->base.primary->state->fb);
@@ -2313,7 +2305,7 @@ static void i9xx_update_wm(struct intel_display *display)
intel_set_memory_cxsr(display, false);
/* Calc sr entries for one plane configs */
- if (HAS_FW_BLC(dev_priv) && crtc) {
+ if (HAS_FW_BLC(display) && crtc) {
/* self-refresh has much higher latency */
static const int sr_latency_ns = 6000;
const struct drm_display_mode *pipe_mode =
@@ -2326,7 +2318,7 @@ static void i9xx_update_wm(struct intel_display *display)
int cpp;
int entries;
- if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
+ if (display->platform.i915gm || display->platform.i945gm)
cpp = 4;
else
cpp = fb->format->cpp[0];
@@ -2334,20 +2326,20 @@ static void i9xx_update_wm(struct intel_display *display)
entries = intel_wm_method2(pixel_rate, htotal, width, cpp,
sr_latency_ns / 100);
entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"self-refresh entries: %d\n", entries);
srwm = wm_info->fifo_size - entries;
if (srwm < 0)
srwm = 1;
- if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
+ if (display->platform.i945g || display->platform.i945gm)
intel_de_write(display, FW_BLC_SELF,
FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
else
intel_de_write(display, FW_BLC_SELF, srwm & 0x3f);
}
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
planea_wm, planeb_wm, cwm, srwm);
@@ -2367,23 +2359,22 @@ static void i9xx_update_wm(struct intel_display *display)
static void i845_update_wm(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_crtc *crtc;
u32 fwater_lo;
int planea_wm;
- crtc = single_enabled_crtc(dev_priv);
+ crtc = single_enabled_crtc(display);
if (crtc == NULL)
return;
- planea_wm = intel_calculate_wm(dev_priv, crtc->config->pixel_rate,
+ planea_wm = intel_calculate_wm(display, crtc->config->pixel_rate,
&i845_wm_info,
- i845_get_fifo_size(dev_priv, PLANE_A),
+ i845_get_fifo_size(display, PLANE_A),
4, pessimal_latency_ns);
fwater_lo = intel_de_read(display, FW_BLC) & ~0xfff;
fwater_lo |= (3<<8) | planea_wm;
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Setting FIFO watermarks - A: %d\n", planea_wm);
intel_de_write(display, FW_BLC, fwater_lo);
@@ -2541,24 +2532,24 @@ static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
}
static unsigned int
-ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
+ilk_display_fifo_size(struct intel_display *display)
{
- if (DISPLAY_VER(dev_priv) >= 8)
+ if (DISPLAY_VER(display) >= 8)
return 3072;
- else if (DISPLAY_VER(dev_priv) >= 7)
+ else if (DISPLAY_VER(display) >= 7)
return 768;
else
return 512;
}
static unsigned int
-ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
+ilk_plane_wm_reg_max(struct intel_display *display,
int level, bool is_sprite)
{
- if (DISPLAY_VER(dev_priv) >= 8)
+ if (DISPLAY_VER(display) >= 8)
/* BDW primary/sprite plane watermarks */
return level == 0 ? 255 : 2047;
- else if (DISPLAY_VER(dev_priv) >= 7)
+ else if (DISPLAY_VER(display) >= 7)
/* IVB/HSW primary/sprite plane watermarks */
return level == 0 ? 127 : 1023;
else if (!is_sprite)
@@ -2570,30 +2561,30 @@ ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
}
static unsigned int
-ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
+ilk_cursor_wm_reg_max(struct intel_display *display, int level)
{
- if (DISPLAY_VER(dev_priv) >= 7)
+ if (DISPLAY_VER(display) >= 7)
return level == 0 ? 63 : 255;
else
return level == 0 ? 31 : 63;
}
-static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
+static unsigned int ilk_fbc_wm_reg_max(struct intel_display *display)
{
- if (DISPLAY_VER(dev_priv) >= 8)
+ if (DISPLAY_VER(display) >= 8)
return 31;
else
return 15;
}
/* Calculate the maximum primary/sprite plane watermark */
-static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
+static unsigned int ilk_plane_wm_max(struct intel_display *display,
int level,
const struct intel_wm_config *config,
enum intel_ddb_partitioning ddb_partitioning,
bool is_sprite)
{
- unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
+ unsigned int fifo_size = ilk_display_fifo_size(display);
/* if sprites aren't enabled, sprites get nothing */
if (is_sprite && !config->sprites_enabled)
@@ -2601,14 +2592,14 @@ static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
/* HSW allows LP1+ watermarks even with multiple pipes */
if (level == 0 || config->num_pipes_active > 1) {
- fifo_size /= INTEL_NUM_PIPES(dev_priv);
+ fifo_size /= INTEL_NUM_PIPES(display);
/*
* For some reason the non self refresh
* FIFO size is only half of the self
* refresh FIFO size on ILK/SNB.
*/
- if (DISPLAY_VER(dev_priv) < 7)
+ if (DISPLAY_VER(display) < 7)
fifo_size /= 2;
}
@@ -2624,11 +2615,11 @@ static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
}
/* clamp to max that the registers can hold */
- return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
+ return min(fifo_size, ilk_plane_wm_reg_max(display, level, is_sprite));
}
/* Calculate the maximum cursor plane watermark */
-static unsigned int ilk_cursor_wm_max(const struct drm_i915_private *dev_priv,
+static unsigned int ilk_cursor_wm_max(struct intel_display *display,
int level,
const struct intel_wm_config *config)
{
@@ -2637,32 +2628,32 @@ static unsigned int ilk_cursor_wm_max(const struct drm_i915_private *dev_priv,
return 64;
/* otherwise just report max that registers can hold */
- return ilk_cursor_wm_reg_max(dev_priv, level);
+ return ilk_cursor_wm_reg_max(display, level);
}
-static void ilk_compute_wm_maximums(const struct drm_i915_private *dev_priv,
+static void ilk_compute_wm_maximums(struct intel_display *display,
int level,
const struct intel_wm_config *config,
enum intel_ddb_partitioning ddb_partitioning,
struct ilk_wm_maximums *max)
{
- max->pri = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, false);
- max->spr = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, true);
- max->cur = ilk_cursor_wm_max(dev_priv, level, config);
- max->fbc = ilk_fbc_wm_reg_max(dev_priv);
+ max->pri = ilk_plane_wm_max(display, level, config, ddb_partitioning, false);
+ max->spr = ilk_plane_wm_max(display, level, config, ddb_partitioning, true);
+ max->cur = ilk_cursor_wm_max(display, level, config);
+ max->fbc = ilk_fbc_wm_reg_max(display);
}
-static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
+static void ilk_compute_wm_reg_maximums(struct intel_display *display,
int level,
struct ilk_wm_maximums *max)
{
- max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
- max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
- max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
- max->fbc = ilk_fbc_wm_reg_max(dev_priv);
+ max->pri = ilk_plane_wm_reg_max(display, level, false);
+ max->spr = ilk_plane_wm_reg_max(display, level, true);
+ max->cur = ilk_cursor_wm_reg_max(display, level);
+ max->fbc = ilk_fbc_wm_reg_max(display);
}
-static bool ilk_validate_wm_level(struct drm_i915_private *i915,
+static bool ilk_validate_wm_level(struct intel_display *display,
int level,
const struct ilk_wm_maximums *max,
struct intel_wm_level *result)
@@ -2686,15 +2677,15 @@ static bool ilk_validate_wm_level(struct drm_i915_private *i915,
*/
if (level == 0 && !result->enable) {
if (result->pri_val > max->pri)
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Primary WM%d too large %u (max %u)\n",
level, result->pri_val, max->pri);
if (result->spr_val > max->spr)
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Sprite WM%d too large %u (max %u)\n",
level, result->spr_val, max->spr);
if (result->cur_val > max->cur)
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Cursor WM%d too large %u (max %u)\n",
level, result->cur_val, max->cur);
@@ -2707,7 +2698,7 @@ static bool ilk_validate_wm_level(struct drm_i915_private *i915,
return ret;
}
-static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
+static void ilk_compute_wm_level(struct intel_display *display,
const struct intel_crtc *crtc,
int level,
struct intel_crtc_state *crtc_state,
@@ -2716,9 +2707,9 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
const struct intel_plane_state *curstate,
struct intel_wm_level *result)
{
- u16 pri_latency = dev_priv->display.wm.pri_latency[level];
- u16 spr_latency = dev_priv->display.wm.spr_latency[level];
- u16 cur_latency = dev_priv->display.wm.cur_latency[level];
+ u16 pri_latency = display->wm.pri_latency[level];
+ u16 spr_latency = display->wm.spr_latency[level];
+ u16 cur_latency = display->wm.cur_latency[level];
/* WM1+ latency values stored in 0.5us units */
if (level > 0) {
@@ -2742,11 +2733,12 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
result->enable = true;
}
-static void hsw_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
+static void hsw_read_wm_latency(struct intel_display *display, u16 wm[])
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
u64 sskpd;
- i915->display.wm.num_levels = 5;
+ display->wm.num_levels = 5;
sskpd = intel_uncore_read64(&i915->uncore, MCH_SSKPD);
@@ -2759,11 +2751,12 @@ static void hsw_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
wm[4] = REG_FIELD_GET64(SSKPD_WM4_MASK_HSW, sskpd);
}
-static void snb_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
+static void snb_read_wm_latency(struct intel_display *display, u16 wm[])
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
u32 sskpd;
- i915->display.wm.num_levels = 4;
+ display->wm.num_levels = 4;
sskpd = intel_uncore_read(&i915->uncore, MCH_SSKPD);
@@ -2773,11 +2766,12 @@ static void snb_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
wm[3] = REG_FIELD_GET(SSKPD_WM3_MASK_SNB, sskpd);
}
-static void ilk_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
+static void ilk_read_wm_latency(struct intel_display *display, u16 wm[])
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
u32 mltr;
- i915->display.wm.num_levels = 3;
+ display->wm.num_levels = 3;
mltr = intel_uncore_read(&i915->uncore, MLTR_ILK);
@@ -2787,24 +2781,21 @@ static void ilk_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
wm[2] = REG_FIELD_GET(MLTR_WM2_MASK, mltr);
}
-static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
- u16 wm[5])
+static void intel_fixup_spr_wm_latency(struct intel_display *display, u16 wm[5])
{
/* ILK sprite LP0 latency is 1300 ns */
- if (DISPLAY_VER(dev_priv) == 5)
+ if (DISPLAY_VER(display) == 5)
wm[0] = 13;
}
-static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
- u16 wm[5])
+static void intel_fixup_cur_wm_latency(struct intel_display *display, u16 wm[5])
{
/* ILK cursor LP0 latency is 1300 ns */
- if (DISPLAY_VER(dev_priv) == 5)
+ if (DISPLAY_VER(display) == 5)
wm[0] = 13;
}
-static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
- u16 wm[5], u16 min)
+static bool ilk_increase_wm_latency(struct intel_display *display, u16 wm[5], u16 min)
{
int level;
@@ -2812,38 +2803,36 @@ static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
return false;
wm[0] = max(wm[0], min);
- for (level = 1; level < dev_priv->display.wm.num_levels; level++)
+ for (level = 1; level < display->wm.num_levels; level++)
wm[level] = max_t(u16, wm[level], DIV_ROUND_UP(min, 5));
return true;
}
-static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
+static void snb_wm_latency_quirk(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
bool changed;
/*
* The BIOS provided WM memory latency values are often
* inadequate for high resolution displays. Adjust them.
*/
- changed = ilk_increase_wm_latency(dev_priv, dev_priv->display.wm.pri_latency, 12);
- changed |= ilk_increase_wm_latency(dev_priv, dev_priv->display.wm.spr_latency, 12);
- changed |= ilk_increase_wm_latency(dev_priv, dev_priv->display.wm.cur_latency, 12);
+ changed = ilk_increase_wm_latency(display, display->wm.pri_latency, 12);
+ changed |= ilk_increase_wm_latency(display, display->wm.spr_latency, 12);
+ changed |= ilk_increase_wm_latency(display, display->wm.cur_latency, 12);
if (!changed)
return;
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"WM latency values increased to avoid potential underruns\n");
- intel_print_wm_latency(display, "Primary", dev_priv->display.wm.pri_latency);
- intel_print_wm_latency(display, "Sprite", dev_priv->display.wm.spr_latency);
- intel_print_wm_latency(display, "Cursor", dev_priv->display.wm.cur_latency);
+ intel_print_wm_latency(display, "Primary", display->wm.pri_latency);
+ intel_print_wm_latency(display, "Sprite", display->wm.spr_latency);
+ intel_print_wm_latency(display, "Cursor", display->wm.cur_latency);
}
-static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
+static void snb_wm_lp3_irq_quirk(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
/*
* On some SNB machines (Thinkpad X220 Tablet at least)
* LP3 usage can cause vblank interrupts to be lost.
@@ -2855,52 +2844,50 @@ static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
* interrupts only. To play it safe we disable LP3
* watermarks entirely.
*/
- if (dev_priv->display.wm.pri_latency[3] == 0 &&
- dev_priv->display.wm.spr_latency[3] == 0 &&
- dev_priv->display.wm.cur_latency[3] == 0)
+ if (display->wm.pri_latency[3] == 0 &&
+ display->wm.spr_latency[3] == 0 &&
+ display->wm.cur_latency[3] == 0)
return;
- dev_priv->display.wm.pri_latency[3] = 0;
- dev_priv->display.wm.spr_latency[3] = 0;
- dev_priv->display.wm.cur_latency[3] = 0;
+ display->wm.pri_latency[3] = 0;
+ display->wm.spr_latency[3] = 0;
+ display->wm.cur_latency[3] = 0;
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"LP3 watermarks disabled due to potential for lost interrupts\n");
- intel_print_wm_latency(display, "Primary", dev_priv->display.wm.pri_latency);
- intel_print_wm_latency(display, "Sprite", dev_priv->display.wm.spr_latency);
- intel_print_wm_latency(display, "Cursor", dev_priv->display.wm.cur_latency);
+ intel_print_wm_latency(display, "Primary", display->wm.pri_latency);
+ intel_print_wm_latency(display, "Sprite", display->wm.spr_latency);
+ intel_print_wm_latency(display, "Cursor", display->wm.cur_latency);
}
-static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
+static void ilk_setup_wm_latency(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
-
- if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
- hsw_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency);
- else if (DISPLAY_VER(dev_priv) >= 6)
- snb_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency);
+ if (display->platform.broadwell || display->platform.haswell)
+ hsw_read_wm_latency(display, display->wm.pri_latency);
+ else if (DISPLAY_VER(display) >= 6)
+ snb_read_wm_latency(display, display->wm.pri_latency);
else
- ilk_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency);
+ ilk_read_wm_latency(display, display->wm.pri_latency);
- memcpy(dev_priv->display.wm.spr_latency, dev_priv->display.wm.pri_latency,
- sizeof(dev_priv->display.wm.pri_latency));
- memcpy(dev_priv->display.wm.cur_latency, dev_priv->display.wm.pri_latency,
- sizeof(dev_priv->display.wm.pri_latency));
+ memcpy(display->wm.spr_latency, display->wm.pri_latency,
+ sizeof(display->wm.pri_latency));
+ memcpy(display->wm.cur_latency, display->wm.pri_latency,
+ sizeof(display->wm.pri_latency));
- intel_fixup_spr_wm_latency(dev_priv, dev_priv->display.wm.spr_latency);
- intel_fixup_cur_wm_latency(dev_priv, dev_priv->display.wm.cur_latency);
+ intel_fixup_spr_wm_latency(display, display->wm.spr_latency);
+ intel_fixup_cur_wm_latency(display, display->wm.cur_latency);
- intel_print_wm_latency(display, "Primary", dev_priv->display.wm.pri_latency);
- intel_print_wm_latency(display, "Sprite", dev_priv->display.wm.spr_latency);
- intel_print_wm_latency(display, "Cursor", dev_priv->display.wm.cur_latency);
+ intel_print_wm_latency(display, "Primary", display->wm.pri_latency);
+ intel_print_wm_latency(display, "Sprite", display->wm.spr_latency);
+ intel_print_wm_latency(display, "Cursor", display->wm.cur_latency);
- if (DISPLAY_VER(dev_priv) == 6) {
- snb_wm_latency_quirk(dev_priv);
- snb_wm_lp3_irq_quirk(dev_priv);
+ if (DISPLAY_VER(display) == 6) {
+ snb_wm_latency_quirk(display);
+ snb_wm_lp3_irq_quirk(display);
}
}
-static bool ilk_validate_pipe_wm(struct drm_i915_private *dev_priv,
+static bool ilk_validate_pipe_wm(struct intel_display *display,
struct intel_pipe_wm *pipe_wm)
{
/* LP0 watermark maximums depend on this pipe alone */
@@ -2912,11 +2899,11 @@ static bool ilk_validate_pipe_wm(struct drm_i915_private *dev_priv,
struct ilk_wm_maximums max;
/* LP0 watermarks always use 1/2 DDB partitioning */
- ilk_compute_wm_maximums(dev_priv, 0, &config, INTEL_DDB_PART_1_2, &max);
+ ilk_compute_wm_maximums(display, 0, &config, INTEL_DDB_PART_1_2, &max);
/* At least LP0 must be valid */
- if (!ilk_validate_wm_level(dev_priv, 0, &max, &pipe_wm->wm[0])) {
- drm_dbg_kms(&dev_priv->drm, "LP0 watermark invalid\n");
+ if (!ilk_validate_wm_level(display, 0, &max, &pipe_wm->wm[0])) {
+ drm_dbg_kms(display->drm, "LP0 watermark invalid\n");
return false;
}
@@ -2927,7 +2914,7 @@ static bool ilk_validate_pipe_wm(struct drm_i915_private *dev_priv,
static int ilk_compute_pipe_wm(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_pipe_wm *pipe_wm;
@@ -2954,10 +2941,10 @@ static int ilk_compute_pipe_wm(struct intel_atomic_state *state,
pipe_wm->sprites_enabled = crtc_state->active_planes & BIT(PLANE_SPRITE0);
pipe_wm->sprites_scaled = crtc_state->scaled_planes & BIT(PLANE_SPRITE0);
- usable_level = dev_priv->display.wm.num_levels - 1;
+ usable_level = display->wm.num_levels - 1;
/* ILK/SNB: LP2+ watermarks only w/o sprites */
- if (DISPLAY_VER(dev_priv) < 7 && pipe_wm->sprites_enabled)
+ if (DISPLAY_VER(display) < 7 && pipe_wm->sprites_enabled)
usable_level = 1;
/* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
@@ -2965,18 +2952,18 @@ static int ilk_compute_pipe_wm(struct intel_atomic_state *state,
usable_level = 0;
memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
- ilk_compute_wm_level(dev_priv, crtc, 0, crtc_state,
+ ilk_compute_wm_level(display, crtc, 0, crtc_state,
pristate, sprstate, curstate, &pipe_wm->wm[0]);
- if (!ilk_validate_pipe_wm(dev_priv, pipe_wm))
+ if (!ilk_validate_pipe_wm(display, pipe_wm))
return -EINVAL;
- ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
+ ilk_compute_wm_reg_maximums(display, 1, &max);
for (level = 1; level <= usable_level; level++) {
struct intel_wm_level *wm = &pipe_wm->wm[level];
- ilk_compute_wm_level(dev_priv, crtc, level, crtc_state,
+ ilk_compute_wm_level(display, crtc, level, crtc_state,
pristate, sprstate, curstate, wm);
/*
@@ -2984,7 +2971,7 @@ static int ilk_compute_pipe_wm(struct intel_atomic_state *state,
* register maximums since such watermarks are
* always invalid.
*/
- if (!ilk_validate_wm_level(dev_priv, level, &max, wm)) {
+ if (!ilk_validate_wm_level(display, level, &max, wm)) {
memset(wm, 0, sizeof(*wm));
break;
}
@@ -3001,7 +2988,7 @@ static int ilk_compute_pipe_wm(struct intel_atomic_state *state,
static int ilk_compute_intermediate_wm(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_crtc_state *old_crtc_state =
@@ -3026,7 +3013,7 @@ static int ilk_compute_intermediate_wm(struct intel_atomic_state *state,
intermediate->sprites_enabled |= active->sprites_enabled;
intermediate->sprites_scaled |= active->sprites_scaled;
- for (level = 0; level < dev_priv->display.wm.num_levels; level++) {
+ for (level = 0; level < display->wm.num_levels; level++) {
struct intel_wm_level *intermediate_wm = &intermediate->wm[level];
const struct intel_wm_level *active_wm = &active->wm[level];
@@ -3047,7 +3034,7 @@ static int ilk_compute_intermediate_wm(struct intel_atomic_state *state,
* there's no safe way to transition from the old state to
* the new state, so we need to fail the atomic transaction.
*/
- if (!ilk_validate_pipe_wm(dev_priv, intermediate))
+ if (!ilk_validate_pipe_wm(display, intermediate))
return -EINVAL;
/*
@@ -3079,7 +3066,7 @@ static int ilk_compute_watermarks(struct intel_atomic_state *state,
/*
* Merge the watermarks from all active pipes for a specific level.
*/
-static void ilk_merge_wm_level(struct drm_i915_private *dev_priv,
+static void ilk_merge_wm_level(struct intel_display *display,
int level,
struct intel_wm_level *ret_wm)
{
@@ -3087,7 +3074,7 @@ static void ilk_merge_wm_level(struct drm_i915_private *dev_priv,
ret_wm->enable = true;
- for_each_intel_crtc(&dev_priv->drm, crtc) {
+ for_each_intel_crtc(display->drm, crtc) {
const struct intel_pipe_wm *active = &crtc->wm.active.ilk;
const struct intel_wm_level *wm = &active->wm[level];
@@ -3112,31 +3099,31 @@ static void ilk_merge_wm_level(struct drm_i915_private *dev_priv,
/*
* Merge all low power watermarks for all active pipes.
*/
-static void ilk_wm_merge(struct drm_i915_private *dev_priv,
+static void ilk_wm_merge(struct intel_display *display,
const struct intel_wm_config *config,
const struct ilk_wm_maximums *max,
struct intel_pipe_wm *merged)
{
- int level, num_levels = dev_priv->display.wm.num_levels;
+ int level, num_levels = display->wm.num_levels;
int last_enabled_level = num_levels - 1;
/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
- if ((DISPLAY_VER(dev_priv) < 7 || IS_IVYBRIDGE(dev_priv)) &&
+ if ((DISPLAY_VER(display) < 7 || display->platform.ivybridge) &&
config->num_pipes_active > 1)
last_enabled_level = 0;
/* ILK: FBC WM must be disabled always */
- merged->fbc_wm_enabled = DISPLAY_VER(dev_priv) >= 6;
+ merged->fbc_wm_enabled = DISPLAY_VER(display) >= 6;
/* merge each WM1+ level */
for (level = 1; level < num_levels; level++) {
struct intel_wm_level *wm = &merged->wm[level];
- ilk_merge_wm_level(dev_priv, level, wm);
+ ilk_merge_wm_level(display, level, wm);
if (level > last_enabled_level)
wm->enable = false;
- else if (!ilk_validate_wm_level(dev_priv, level, max, wm))
+ else if (!ilk_validate_wm_level(display, level, max, wm))
/* make sure all following levels get disabled */
last_enabled_level = level - 1;
@@ -3152,8 +3139,8 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv,
}
/* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
- if (DISPLAY_VER(dev_priv) == 5 && HAS_FBC(dev_priv) &&
- dev_priv->display.params.enable_fbc && !merged->fbc_wm_enabled) {
+ if (DISPLAY_VER(display) == 5 && HAS_FBC(display) &&
+ display->params.enable_fbc && !merged->fbc_wm_enabled) {
for (level = 2; level < num_levels; level++) {
struct intel_wm_level *wm = &merged->wm[level];
@@ -3169,16 +3156,16 @@ static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
}
/* The value we need to program into the WM_LPx latency field */
-static unsigned int ilk_wm_lp_latency(struct drm_i915_private *dev_priv,
+static unsigned int ilk_wm_lp_latency(struct intel_display *display,
int level)
{
- if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+ if (display->platform.haswell || display->platform.broadwell)
return 2 * level;
else
- return dev_priv->display.wm.pri_latency[level];
+ return display->wm.pri_latency[level];
}
-static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
+static void ilk_compute_wm_results(struct intel_display *display,
const struct intel_pipe_wm *merged,
enum intel_ddb_partitioning partitioning,
struct ilk_wm_values *results)
@@ -3202,14 +3189,14 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
* disabled. Doing otherwise could cause underruns.
*/
results->wm_lp[wm_lp - 1] =
- WM_LP_LATENCY(ilk_wm_lp_latency(dev_priv, level)) |
+ WM_LP_LATENCY(ilk_wm_lp_latency(display, level)) |
WM_LP_PRIMARY(r->pri_val) |
WM_LP_CURSOR(r->cur_val);
if (r->enable)
results->wm_lp[wm_lp - 1] |= WM_LP_ENABLE;
- if (DISPLAY_VER(dev_priv) >= 8)
+ if (DISPLAY_VER(display) >= 8)
results->wm_lp[wm_lp - 1] |= WM_LP_FBC_BDW(r->fbc_val);
else
results->wm_lp[wm_lp - 1] |= WM_LP_FBC_ILK(r->fbc_val);
@@ -3220,19 +3207,19 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
* Always set WM_LP_SPRITE_EN when spr_val != 0, even if the
* level is disabled. Doing otherwise could cause underruns.
*/
- if (DISPLAY_VER(dev_priv) < 7 && r->spr_val) {
- drm_WARN_ON(&dev_priv->drm, wm_lp != 1);
+ if (DISPLAY_VER(display) < 7 && r->spr_val) {
+ drm_WARN_ON(display->drm, wm_lp != 1);
results->wm_lp_spr[wm_lp - 1] |= WM_LP_SPRITE_ENABLE;
}
}
/* LP0 register values */
- for_each_intel_crtc(&dev_priv->drm, crtc) {
+ for_each_intel_crtc(display->drm, crtc) {
enum pipe pipe = crtc->pipe;
const struct intel_pipe_wm *pipe_wm = &crtc->wm.active.ilk;
const struct intel_wm_level *r = &pipe_wm->wm[0];
- if (drm_WARN_ON(&dev_priv->drm, !r->enable))
+ if (drm_WARN_ON(display->drm, !r->enable))
continue;
results->wm_pipe[pipe] =
@@ -3247,13 +3234,13 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
* case both are at the same level. Prefer r1 in case they're the same.
*/
static struct intel_pipe_wm *
-ilk_find_best_result(struct drm_i915_private *dev_priv,
+ilk_find_best_result(struct intel_display *display,
struct intel_pipe_wm *r1,
struct intel_pipe_wm *r2)
{
int level, level1 = 0, level2 = 0;
- for (level = 1; level < dev_priv->display.wm.num_levels; level++) {
+ for (level = 1; level < display->wm.num_levels; level++) {
if (r1->wm[level].enable)
level1 = level;
if (r2->wm[level].enable)
@@ -3279,7 +3266,7 @@ ilk_find_best_result(struct drm_i915_private *dev_priv,
#define WM_DIRTY_FBC (1 << 24)
#define WM_DIRTY_DDB (1 << 25)
-static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
+static unsigned int ilk_compute_wm_dirty(struct intel_display *display,
const struct ilk_wm_values *old,
const struct ilk_wm_values *new)
{
@@ -3287,7 +3274,7 @@ static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
enum pipe pipe;
int wm_lp;
- for_each_pipe(dev_priv, pipe) {
+ for_each_pipe(display, pipe) {
if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
dirty |= WM_DIRTY_PIPE(pipe);
/* Must disable LP1+ watermarks too */
@@ -3325,11 +3312,10 @@ static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
return dirty;
}
-static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
+static bool _ilk_disable_lp_wm(struct intel_display *display,
unsigned int dirty)
{
- struct intel_display *display = &dev_priv->display;
- struct ilk_wm_values *previous = &dev_priv->display.wm.hw;
+ struct ilk_wm_values *previous = &display->wm.hw;
bool changed = false;
if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM_LP_ENABLE) {
@@ -3360,18 +3346,17 @@ static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
* The spec says we shouldn't write when we don't need, because every write
* causes WMs to be re-evaluated, expending some power.
*/
-static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
+static void ilk_write_wm_values(struct intel_display *display,
struct ilk_wm_values *results)
{
- struct intel_display *display = &dev_priv->display;
- struct ilk_wm_values *previous = &dev_priv->display.wm.hw;
+ struct ilk_wm_values *previous = &display->wm.hw;
unsigned int dirty;
- dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
+ dirty = ilk_compute_wm_dirty(display, previous, results);
if (!dirty)
return;
- _ilk_disable_lp_wm(dev_priv, dirty);
+ _ilk_disable_lp_wm(display, dirty);
if (dirty & WM_DIRTY_PIPE(PIPE_A))
intel_de_write(display, WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
@@ -3381,7 +3366,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
intel_de_write(display, WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);
if (dirty & WM_DIRTY_DDB) {
- if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+ if (display->platform.haswell || display->platform.broadwell)
intel_de_rmw(display, WM_MISC, WM_MISC_DATA_PARTITION_5_6,
results->partitioning == INTEL_DDB_PART_1_2 ? 0 :
WM_MISC_DATA_PARTITION_5_6);
@@ -3399,7 +3384,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
previous->wm_lp_spr[0] != results->wm_lp_spr[0])
intel_de_write(display, WM1S_LP_ILK, results->wm_lp_spr[0]);
- if (DISPLAY_VER(dev_priv) >= 7) {
+ if (DISPLAY_VER(display) >= 7) {
if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
intel_de_write(display, WM2S_LP_IVB, results->wm_lp_spr[1]);
if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
@@ -3413,23 +3398,21 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
intel_de_write(display, WM3_LP_ILK, results->wm_lp[2]);
- dev_priv->display.wm.hw = *results;
+ display->wm.hw = *results;
}
bool ilk_disable_cxsr(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
-
- return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
+ return _ilk_disable_lp_wm(display, WM_DIRTY_LP_ALL);
}
-static void ilk_compute_wm_config(struct drm_i915_private *dev_priv,
+static void ilk_compute_wm_config(struct intel_display *display,
struct intel_wm_config *config)
{
struct intel_crtc *crtc;
/* Compute the currently _active_ config */
- for_each_intel_crtc(&dev_priv->drm, crtc) {
+ for_each_intel_crtc(display->drm, crtc) {
const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
if (!wm->pipe_enabled)
@@ -3441,7 +3424,7 @@ static void ilk_compute_wm_config(struct drm_i915_private *dev_priv,
}
}
-static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
+static void ilk_program_watermarks(struct intel_display *display)
{
struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
struct ilk_wm_maximums max;
@@ -3449,18 +3432,18 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
struct ilk_wm_values results = {};
enum intel_ddb_partitioning partitioning;
- ilk_compute_wm_config(dev_priv, &config);
+ ilk_compute_wm_config(display, &config);
- ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_1_2, &max);
- ilk_wm_merge(dev_priv, &config, &max, &lp_wm_1_2);
+ ilk_compute_wm_maximums(display, 1, &config, INTEL_DDB_PART_1_2, &max);
+ ilk_wm_merge(display, &config, &max, &lp_wm_1_2);
/* 5/6 split only in single pipe config on IVB+ */
- if (DISPLAY_VER(dev_priv) >= 7 &&
+ if (DISPLAY_VER(display) >= 7 &&
config.num_pipes_active == 1 && config.sprites_enabled) {
- ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_5_6, &max);
- ilk_wm_merge(dev_priv, &config, &max, &lp_wm_5_6);
+ ilk_compute_wm_maximums(display, 1, &config, INTEL_DDB_PART_5_6, &max);
+ ilk_wm_merge(display, &config, &max, &lp_wm_5_6);
- best_lp_wm = ilk_find_best_result(dev_priv, &lp_wm_1_2, &lp_wm_5_6);
+ best_lp_wm = ilk_find_best_result(display, &lp_wm_1_2, &lp_wm_5_6);
} else {
best_lp_wm = &lp_wm_1_2;
}
@@ -3468,46 +3451,44 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
partitioning = (best_lp_wm == &lp_wm_1_2) ?
INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
- ilk_compute_wm_results(dev_priv, best_lp_wm, partitioning, &results);
+ ilk_compute_wm_results(display, best_lp_wm, partitioning, &results);
- ilk_write_wm_values(dev_priv, &results);
+ ilk_write_wm_values(display, &results);
}
static void ilk_initial_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
const struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- mutex_lock(&dev_priv->display.wm.wm_mutex);
+ mutex_lock(&display->wm.wm_mutex);
crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
- ilk_program_watermarks(dev_priv);
- mutex_unlock(&dev_priv->display.wm.wm_mutex);
+ ilk_program_watermarks(display);
+ mutex_unlock(&display->wm.wm_mutex);
}
static void ilk_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
const struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
if (!crtc_state->wm.need_postvbl_update)
return;
- mutex_lock(&dev_priv->display.wm.wm_mutex);
+ mutex_lock(&display->wm.wm_mutex);
crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;
- ilk_program_watermarks(dev_priv);
- mutex_unlock(&dev_priv->display.wm.wm_mutex);
+ ilk_program_watermarks(display);
+ mutex_unlock(&display->wm.wm_mutex);
}
static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(crtc);
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct ilk_wm_values *hw = &dev_priv->display.wm.hw;
+ struct ilk_wm_values *hw = &display->wm.hw;
struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
enum pipe pipe = crtc->pipe;
@@ -3539,7 +3520,7 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
* should be marked as enabled but zeroed,
* which is what we'd compute them to.
*/
- for (level = 0; level < dev_priv->display.wm.num_levels; level++)
+ for (level = 0; level < display->wm.num_levels; level++)
active->wm[level].enable = true;
}
@@ -3590,7 +3571,6 @@ static int ilk_sanitize_watermarks_add_affected(struct drm_atomic_state *state)
*/
void ilk_wm_sanitize(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
struct drm_atomic_state *state;
struct intel_atomic_state *intel_state;
struct intel_crtc *crtc;
@@ -3600,14 +3580,14 @@ void ilk_wm_sanitize(struct intel_display *display)
int i;
/* Only supported on platforms that use atomic watermark design */
- if (!dev_priv->display.funcs.wm->optimize_watermarks)
+ if (!display->funcs.wm->optimize_watermarks)
return;
- if (drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) >= 9))
+ if (drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 9))
return;
- state = drm_atomic_state_alloc(&dev_priv->drm);
- if (drm_WARN_ON(&dev_priv->drm, !state))
+ state = drm_atomic_state_alloc(display->drm);
+ if (drm_WARN_ON(display->drm, !state))
return;
intel_state = to_intel_atomic_state(state);
@@ -3623,14 +3603,14 @@ void ilk_wm_sanitize(struct intel_display *display)
* intermediate watermarks (since we don't trust the current
* watermarks).
*/
- if (!HAS_GMCH(dev_priv))
+ if (!HAS_GMCH(display))
intel_state->skip_intermediate_wm = true;
ret = ilk_sanitize_watermarks_add_affected(state);
if (ret)
goto fail;
- ret = intel_atomic_check(&dev_priv->drm, state);
+ ret = intel_atomic_check(display->drm, state);
if (ret)
goto fail;
@@ -3660,7 +3640,7 @@ void ilk_wm_sanitize(struct intel_display *display)
* If this actually happens, we'll have to just leave the
* BIOS-programmed watermarks untouched and hope for the best.
*/
- drm_WARN(&dev_priv->drm, ret,
+ drm_WARN(display->drm, ret,
"Could not determine valid watermarks for inherited state\n");
drm_atomic_state_put(state);
@@ -3674,10 +3654,9 @@ void ilk_wm_sanitize(struct intel_display *display)
#define _FW_WM_VLV(value, plane) \
(((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
-static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
+static void g4x_read_wm_values(struct intel_display *display,
struct g4x_wm_values *wm)
{
- struct intel_display *display = &dev_priv->display;
u32 tmp;
tmp = intel_de_read(display, DSPFW1(display));
@@ -3701,14 +3680,13 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
wm->hpll.plane = _FW_WM(tmp, HPLL_SR);
}
-static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
+static void vlv_read_wm_values(struct intel_display *display,
struct vlv_wm_values *wm)
{
- struct intel_display *display = &dev_priv->display;
enum pipe pipe;
u32 tmp;
- for_each_pipe(dev_priv, pipe) {
+ for_each_pipe(display, pipe) {
tmp = intel_de_read(display, VLV_DDL(pipe));
wm->ddl[pipe].plane[PLANE_PRIMARY] =
@@ -3735,7 +3713,7 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
tmp = intel_de_read(display, DSPFW3(display));
wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
- if (IS_CHERRYVIEW(dev_priv)) {
+ if (display->platform.cherryview) {
tmp = intel_de_read(display, DSPFW7_CHV);
wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
@@ -3780,15 +3758,14 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
static void g4x_wm_get_hw_state(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
- struct g4x_wm_values *wm = &dev_priv->display.wm.g4x;
+ struct g4x_wm_values *wm = &display->wm.g4x;
struct intel_crtc *crtc;
- g4x_read_wm_values(dev_priv, wm);
+ g4x_read_wm_values(display, wm);
wm->cxsr = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
- for_each_intel_crtc(&dev_priv->drm, crtc) {
+ for_each_intel_crtc(display->drm, crtc) {
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
struct g4x_wm_state *active = &crtc->wm.active.g4x;
@@ -3853,7 +3830,7 @@ static void g4x_wm_get_hw_state(struct intel_display *display)
crtc_state->wm.g4x.optimal = *active;
crtc_state->wm.g4x.intermediate = *active;
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n",
pipe_name(pipe),
wm->pipe[pipe].plane[PLANE_PRIMARY],
@@ -3861,26 +3838,25 @@ static void g4x_wm_get_hw_state(struct intel_display *display)
wm->pipe[pipe].plane[PLANE_SPRITE0]);
}
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n",
wm->sr.plane, wm->sr.cursor, wm->sr.fbc);
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n",
wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc);
- drm_dbg_kms(&dev_priv->drm, "Initial SR=%s HPLL=%s FBC=%s\n",
+ drm_dbg_kms(display->drm, "Initial SR=%s HPLL=%s FBC=%s\n",
str_yes_no(wm->cxsr), str_yes_no(wm->hpll_en),
str_yes_no(wm->fbc_en));
}
static void g4x_wm_sanitize(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_plane *plane;
struct intel_crtc *crtc;
- mutex_lock(&dev_priv->display.wm.wm_mutex);
+ mutex_lock(&display->wm.wm_mutex);
- for_each_intel_plane(&dev_priv->drm, plane) {
+ for_each_intel_plane(display->drm, plane) {
struct intel_crtc *crtc =
intel_crtc_for_pipe(display, plane->pipe);
struct intel_crtc_state *crtc_state =
@@ -3893,7 +3869,7 @@ static void g4x_wm_sanitize(struct intel_display *display)
if (plane_state->uapi.visible)
continue;
- for (level = 0; level < dev_priv->display.wm.num_levels; level++) {
+ for (level = 0; level < display->wm.num_levels; level++) {
struct g4x_pipe_wm *raw =
&crtc_state->wm.g4x.raw[level];
@@ -3904,37 +3880,37 @@ static void g4x_wm_sanitize(struct intel_display *display)
}
}
- for_each_intel_crtc(&dev_priv->drm, crtc) {
+ for_each_intel_crtc(display->drm, crtc) {
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
int ret;
ret = _g4x_compute_pipe_wm(crtc_state);
- drm_WARN_ON(&dev_priv->drm, ret);
+ drm_WARN_ON(display->drm, ret);
crtc_state->wm.g4x.intermediate =
crtc_state->wm.g4x.optimal;
crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
}
- g4x_program_watermarks(dev_priv);
+ g4x_program_watermarks(display);
- mutex_unlock(&dev_priv->display.wm.wm_mutex);
+ mutex_unlock(&display->wm.wm_mutex);
}
static void vlv_wm_get_hw_state(struct intel_display *display)
{
struct drm_i915_private *dev_priv = to_i915(display->drm);
- struct vlv_wm_values *wm = &dev_priv->display.wm.vlv;
+ struct vlv_wm_values *wm = &display->wm.vlv;
struct intel_crtc *crtc;
u32 val;
- vlv_read_wm_values(dev_priv, wm);
+ vlv_read_wm_values(display, wm);
wm->cxsr = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
wm->level = VLV_WM_LEVEL_PM2;
- if (IS_CHERRYVIEW(dev_priv)) {
+ if (display->platform.cherryview) {
vlv_punit_get(dev_priv);
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
@@ -3956,10 +3932,10 @@ static void vlv_wm_get_hw_state(struct intel_display *display)
if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Punit not acking DDR DVFS request, "
"assuming DDR DVFS is disabled\n");
- dev_priv->display.wm.num_levels = VLV_WM_LEVEL_PM5 + 1;
+ display->wm.num_levels = VLV_WM_LEVEL_PM5 + 1;
} else {
val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
if ((val & FORCE_DDR_HIGH_FREQ) == 0)
@@ -3969,7 +3945,7 @@ static void vlv_wm_get_hw_state(struct intel_display *display)
vlv_punit_put(dev_priv);
}
- for_each_intel_crtc(&dev_priv->drm, crtc) {
+ for_each_intel_crtc(display->drm, crtc) {
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
struct vlv_wm_state *active = &crtc->wm.active.vlv;
@@ -4009,7 +3985,7 @@ static void vlv_wm_get_hw_state(struct intel_display *display)
crtc_state->wm.vlv.optimal = *active;
crtc_state->wm.vlv.intermediate = *active;
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
pipe_name(pipe),
wm->pipe[pipe].plane[PLANE_PRIMARY],
@@ -4018,20 +3994,19 @@ static void vlv_wm_get_hw_state(struct intel_display *display)
wm->pipe[pipe].plane[PLANE_SPRITE1]);
}
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
}
static void vlv_wm_sanitize(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_plane *plane;
struct intel_crtc *crtc;
- mutex_lock(&dev_priv->display.wm.wm_mutex);
+ mutex_lock(&display->wm.wm_mutex);
- for_each_intel_plane(&dev_priv->drm, plane) {
+ for_each_intel_plane(display->drm, plane) {
struct intel_crtc *crtc =
intel_crtc_for_pipe(display, plane->pipe);
struct intel_crtc_state *crtc_state =
@@ -4044,7 +4019,7 @@ static void vlv_wm_sanitize(struct intel_display *display)
if (plane_state->uapi.visible)
continue;
- for (level = 0; level < dev_priv->display.wm.num_levels; level++) {
+ for (level = 0; level < display->wm.num_levels; level++) {
struct g4x_pipe_wm *raw =
&crtc_state->wm.vlv.raw[level];
@@ -4052,32 +4027,30 @@ static void vlv_wm_sanitize(struct intel_display *display)
}
}
- for_each_intel_crtc(&dev_priv->drm, crtc) {
+ for_each_intel_crtc(display->drm, crtc) {
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
int ret;
ret = _vlv_compute_pipe_wm(crtc_state);
- drm_WARN_ON(&dev_priv->drm, ret);
+ drm_WARN_ON(display->drm, ret);
crtc_state->wm.vlv.intermediate =
crtc_state->wm.vlv.optimal;
crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
}
- vlv_program_watermarks(dev_priv);
+ vlv_program_watermarks(display);
- mutex_unlock(&dev_priv->display.wm.wm_mutex);
+ mutex_unlock(&display->wm.wm_mutex);
}
/*
* FIXME should probably kill this and improve
* the real watermark readout/sanitation instead
*/
-static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
+static void ilk_init_lp_watermarks(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
-
intel_de_rmw(display, WM3_LP_ILK, WM_LP_ENABLE, 0);
intel_de_rmw(display, WM2_LP_ILK, WM_LP_ENABLE, 0);
intel_de_rmw(display, WM1_LP_ILK, WM_LP_ENABLE, 0);
@@ -4090,13 +4063,12 @@ static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
static void ilk_wm_get_hw_state(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
- struct ilk_wm_values *hw = &dev_priv->display.wm.hw;
+ struct ilk_wm_values *hw = &display->wm.hw;
struct intel_crtc *crtc;
- ilk_init_lp_watermarks(dev_priv);
+ ilk_init_lp_watermarks(display);
- for_each_intel_crtc(&dev_priv->drm, crtc)
+ for_each_intel_crtc(display->drm, crtc)
ilk_pipe_wm_get_hw_state(crtc);
hw->wm_lp[0] = intel_de_read(display, WM1_LP_ILK);
@@ -4104,16 +4076,16 @@ static void ilk_wm_get_hw_state(struct intel_display *display)
hw->wm_lp[2] = intel_de_read(display, WM3_LP_ILK);
hw->wm_lp_spr[0] = intel_de_read(display, WM1S_LP_ILK);
- if (DISPLAY_VER(dev_priv) >= 7) {
+ if (DISPLAY_VER(display) >= 7) {
hw->wm_lp_spr[1] = intel_de_read(display, WM2S_LP_IVB);
hw->wm_lp_spr[2] = intel_de_read(display, WM3S_LP_IVB);
}
- if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+ if (display->platform.haswell || display->platform.broadwell)
hw->partitioning = (intel_de_read(display, WM_MISC) &
WM_MISC_DATA_PARTITION_5_6) ?
INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
- else if (IS_IVYBRIDGE(dev_priv))
+ else if (display->platform.ivybridge)
hw->partitioning = (intel_de_read(display, DISP_ARB_CTL2) &
DISP_DATA_PARTITION_5_6) ?
INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
@@ -4175,35 +4147,35 @@ void i9xx_wm_init(struct intel_display *display)
/* For FIFO watermark updates */
if (HAS_PCH_SPLIT(dev_priv)) {
- ilk_setup_wm_latency(dev_priv);
- dev_priv->display.funcs.wm = &ilk_wm_funcs;
- } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- vlv_setup_wm_latency(dev_priv);
- dev_priv->display.funcs.wm = &vlv_wm_funcs;
- } else if (IS_G4X(dev_priv)) {
- g4x_setup_wm_latency(dev_priv);
- dev_priv->display.funcs.wm = &g4x_wm_funcs;
- } else if (IS_PINEVIEW(dev_priv)) {
- if (!pnv_get_cxsr_latency(dev_priv)) {
- drm_info(&dev_priv->drm, "Unknown FSB/MEM, disabling CxSR\n");
+ ilk_setup_wm_latency(display);
+ display->funcs.wm = &ilk_wm_funcs;
+ } else if (display->platform.valleyview || display->platform.cherryview) {
+ vlv_setup_wm_latency(display);
+ display->funcs.wm = &vlv_wm_funcs;
+ } else if (display->platform.g4x) {
+ g4x_setup_wm_latency(display);
+ display->funcs.wm = &g4x_wm_funcs;
+ } else if (display->platform.pineview) {
+ if (!pnv_get_cxsr_latency(display)) {
+ drm_info(display->drm, "Unknown FSB/MEM, disabling CxSR\n");
/* Disable CxSR and never update its watermark again */
intel_set_memory_cxsr(display, false);
- dev_priv->display.funcs.wm = &nop_funcs;
+ display->funcs.wm = &nop_funcs;
} else {
- dev_priv->display.funcs.wm = &pnv_wm_funcs;
+ display->funcs.wm = &pnv_wm_funcs;
}
- } else if (DISPLAY_VER(dev_priv) == 4) {
- dev_priv->display.funcs.wm = &i965_wm_funcs;
- } else if (DISPLAY_VER(dev_priv) == 3) {
- dev_priv->display.funcs.wm = &i9xx_wm_funcs;
- } else if (DISPLAY_VER(dev_priv) == 2) {
- if (INTEL_NUM_PIPES(dev_priv) == 1)
- dev_priv->display.funcs.wm = &i845_wm_funcs;
+ } else if (DISPLAY_VER(display) == 4) {
+ display->funcs.wm = &i965_wm_funcs;
+ } else if (DISPLAY_VER(display) == 3) {
+ display->funcs.wm = &i9xx_wm_funcs;
+ } else if (DISPLAY_VER(display) == 2) {
+ if (INTEL_NUM_PIPES(display) == 1)
+ display->funcs.wm = &i845_wm_funcs;
else
- dev_priv->display.funcs.wm = &i9xx_wm_funcs;
+ display->funcs.wm = &i9xx_wm_funcs;
} else {
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"unexpected fall-through in %s\n", __func__);
- dev_priv->display.funcs.wm = &nop_funcs;
+ display->funcs.wm = &nop_funcs;
}
}
--
2.39.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/wm: convert to struct intel_display (rev2)
2025-04-08 13:38 [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display Jani Nikula
` (6 preceding siblings ...)
2025-04-08 13:38 ` [PATCH v2 7/7] drm/i915/wm: convert i9xx_wm.c internally to struct intel_display Jani Nikula
@ 2025-04-08 14:03 ` Patchwork
2025-04-08 14:03 ` ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-04-08 14:03 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/wm: convert to struct intel_display (rev2)
URL : https://patchwork.freedesktop.org/series/147193/
State : warning
== Summary ==
Error: dim checkpatch failed
ae4e585eb936 drm/i915/wm: convert intel_wm.h external interfaces to struct intel_display
b79a9b9bdbce drm/i915/wm: convert intel_wm.c internally to struct intel_display
6a10837011af drm/i915/wm: convert skl_watermark.h external interfaces to struct intel_display
67fa5a776904 drm/i915/wm: convert skl_watermarks.c internally to struct intel_display
bbcb07cca6e7 drm/i915/wm: convert i9xx_wm.h external interfaces to struct intel_display
-:170: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#170: FILE: drivers/gpu/drm/i915/display/i9xx_wm.h:25:
}
+static inline void ilk_wm_sanitize(struct intel_display *display)
-:174: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#174: FILE: drivers/gpu/drm/i915/display/i9xx_wm.h:28:
}
+static inline bool intel_set_memory_cxsr(struct intel_display *display, bool enable)
-:179: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#179: FILE: drivers/gpu/drm/i915/display/i9xx_wm.h:32:
}
+static inline void i9xx_wm_init(struct intel_display *display)
total: 0 errors, 0 warnings, 3 checks, 217 lines checked
bfef21460fb2 drm/i915/wm: convert i9xx_wm.c to intel_de_*() register interface
8f8cc1bb47bb drm/i915/wm: convert i9xx_wm.c internally to struct intel_display
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915/wm: convert to struct intel_display (rev2)
2025-04-08 13:38 [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display Jani Nikula
` (7 preceding siblings ...)
2025-04-08 14:03 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/wm: convert to struct intel_display (rev2) Patchwork
@ 2025-04-08 14:03 ` Patchwork
2025-04-08 14:22 ` ✓ i915.CI.BAT: success " Patchwork
` (2 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-04-08 14:03 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/wm: convert to struct intel_display (rev2)
URL : https://patchwork.freedesktop.org/series/147193/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ i915.CI.BAT: success for drm/i915/wm: convert to struct intel_display (rev2)
2025-04-08 13:38 [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display Jani Nikula
` (8 preceding siblings ...)
2025-04-08 14:03 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2025-04-08 14:22 ` Patchwork
2025-04-08 16:44 ` ✗ i915.CI.Full: failure " Patchwork
2025-04-09 9:17 ` [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display Kandpal, Suraj
11 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-04-08 14:22 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5397 bytes --]
== Series Details ==
Series: drm/i915/wm: convert to struct intel_display (rev2)
URL : https://patchwork.freedesktop.org/series/147193/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16377 -> Patchwork_147193v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/index.html
Participating hosts (44 -> 43)
------------------------------
Additional (1): fi-hsw-4770
Missing (2): bat-arlh-2 fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_147193v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@dmabuf@all-tests@dma_fence_chain:
- fi-bsw-n3050: [PASS][1] -> [INCOMPLETE][2] ([i915#12904]) +1 other test incomplete
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/fi-bsw-n3050/igt@dmabuf@all-tests@dma_fence_chain.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/fi-bsw-n3050/igt@dmabuf@all-tests@dma_fence_chain.html
* igt@gem_softpin@allocator-basic-reserve:
- fi-hsw-4770: NOTRUN -> [SKIP][3] +14 other tests skip
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/fi-hsw-4770/igt@gem_softpin@allocator-basic-reserve.html
* igt@i915_selftest@live@late_gt_pm:
- fi-cfl-8109u: [PASS][4] -> [DMESG-WARN][5] ([i915#13735]) +82 other tests dmesg-warn
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
* igt@i915_selftest@live@workarounds:
- bat-arls-5: [PASS][6] -> [DMESG-FAIL][7] ([i915#12061]) +1 other test dmesg-fail
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/bat-arls-5/igt@i915_selftest@live@workarounds.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/bat-arls-5/igt@i915_selftest@live@workarounds.html
- bat-dg2-11: [PASS][8] -> [DMESG-FAIL][9] ([i915#12061]) +1 other test dmesg-fail
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/bat-dg2-11/igt@i915_selftest@live@workarounds.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/bat-dg2-11/igt@i915_selftest@live@workarounds.html
- bat-arls-6: [PASS][10] -> [DMESG-FAIL][11] ([i915#12061]) +1 other test dmesg-fail
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/bat-arls-6/igt@i915_selftest@live@workarounds.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/bat-arls-6/igt@i915_selftest@live@workarounds.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770: NOTRUN -> [SKIP][12] ([i915#5190])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/fi-hsw-4770/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_pipe_crc_basic@read-crc:
- fi-cfl-8109u: [PASS][13] -> [DMESG-WARN][14] ([i915#13735] / [i915#13890]) +49 other tests dmesg-warn
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc.html
* igt@kms_psr@psr-sprite-plane-onoff:
- fi-hsw-4770: NOTRUN -> [SKIP][15] ([i915#1072]) +3 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/fi-hsw-4770/igt@kms_psr@psr-sprite-plane-onoff.html
#### Possible fixes ####
* igt@i915_module_load@load:
- bat-mtlp-9: [DMESG-WARN][16] ([i915#13494]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/bat-mtlp-9/igt@i915_module_load@load.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/bat-mtlp-9/igt@i915_module_load@load.html
* igt@i915_selftest@live@workarounds:
- bat-mtlp-9: [DMESG-FAIL][18] ([i915#12061]) -> [PASS][19] +1 other test pass
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
[i915#13494]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13494
[i915#13735]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13735
[i915#13890]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13890
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
Build changes
-------------
* Linux: CI_DRM_16377 -> Patchwork_147193v2
CI-20190529: 20190529
CI_DRM_16377: a33da369e8cde6c7208381a592866cd61f1ce188 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8309: fb77fb2d8d58a2539c9d67d00e1747351eec0bea @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_147193v2: a33da369e8cde6c7208381a592866cd61f1ce188 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/index.html
[-- Attachment #2: Type: text/html, Size: 6526 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✗ i915.CI.Full: failure for drm/i915/wm: convert to struct intel_display (rev2)
2025-04-08 13:38 [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display Jani Nikula
` (9 preceding siblings ...)
2025-04-08 14:22 ` ✓ i915.CI.BAT: success " Patchwork
@ 2025-04-08 16:44 ` Patchwork
2025-04-09 9:17 ` [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display Kandpal, Suraj
11 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-04-08 16:44 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 122471 bytes --]
== Series Details ==
Series: drm/i915/wm: convert to struct intel_display (rev2)
URL : https://patchwork.freedesktop.org/series/147193/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16377_full -> Patchwork_147193v2_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_147193v2_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_147193v2_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_147193v2_full:
### IGT changes ###
#### Possible regressions ####
* igt@api_intel_allocator@gem-pool:
- shard-dg2: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg2-6/igt@api_intel_allocator@gem-pool.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-5/igt@api_intel_allocator@gem-pool.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [INCOMPLETE][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1.html
New tests
---------
New tests have been introduced between CI_DRM_16377_full and Patchwork_147193v2_full:
### New IGT tests (12) ###
* igt@api_intel_allocator@cursor-onscreen-32x10:
- Statuses :
- Exec time: [None] s
* igt@api_intel_allocator@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt:
- Statuses :
- Exec time: [None] s
* igt@api_intel_allocator@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- Statuses :
- Exec time: [None] s
* igt@api_intel_allocator@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- Statuses :
- Exec time: [None] s
* igt@api_intel_allocator@fbc-2p-scndscrn-spr-indfb-draw-render:
- Statuses :
- Exec time: [None] s
* igt@api_intel_allocator@invalid-metadata-sizes:
- Statuses :
- Exec time: [None] s
* igt@api_intel_allocator@plane-position-hole:
- Statuses :
- Exec time: [None] s
* igt@api_intel_allocator@psr-2p-primscrn-shrfb-msflip-blt:
- Statuses :
- Exec time: [None] s
* igt@api_intel_allocator@rc6-idle:
- Statuses :
- Exec time: [None] s
* igt@api_intel_allocator@system-suspend:
- Statuses :
- Exec time: [None] s
* igt@api_intel_allocator@y-tiled-64bpp-rotate-270:
- Statuses :
- Exec time: [None] s
* igt@api_intel_allocator@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- Statuses :
- Exec time: [None] s
Known issues
------------
Here are the changes found in Patchwork_147193v2_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@object-reloc-keep-cache:
- shard-dg2: NOTRUN -> [SKIP][4] ([i915#8411])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@api_intel_bb@object-reloc-keep-cache.html
* igt@debugfs_test@basic-hwmon:
- shard-rkl: NOTRUN -> [SKIP][5] ([i915#9318])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@debugfs_test@basic-hwmon.html
* igt@device_reset@cold-reset-bound:
- shard-dg2-9: NOTRUN -> [SKIP][6] ([i915#11078]) +1 other test skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@device_reset@cold-reset-bound.html
* igt@device_reset@unbind-cold-reset-rebind:
- shard-rkl: NOTRUN -> [SKIP][7] ([i915#11078]) +1 other test skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-4/igt@device_reset@unbind-cold-reset-rebind.html
* igt@drm_fdinfo@most-busy-check-all@vecs0:
- shard-dg2-9: NOTRUN -> [SKIP][8] ([i915#8414]) +7 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@drm_fdinfo@most-busy-check-all@vecs0.html
* igt@drm_fdinfo@virtual-busy-hang-all:
- shard-dg2: NOTRUN -> [SKIP][9] ([i915#8414])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@drm_fdinfo@virtual-busy-hang-all.html
* igt@drm_fdinfo@virtual-busy-idle-all:
- shard-mtlp: NOTRUN -> [SKIP][10] ([i915#8414])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@drm_fdinfo@virtual-busy-idle-all.html
* igt@gem_bad_reloc@negative-reloc-lut:
- shard-rkl: NOTRUN -> [SKIP][11] ([i915#3281]) +16 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@gem_bad_reloc@negative-reloc-lut.html
* igt@gem_ccs@block-copy-compressed:
- shard-tglu-1: NOTRUN -> [SKIP][12] ([i915#3555] / [i915#9323])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@gem_ccs@block-copy-compressed.html
* igt@gem_ccs@block-multicopy-compressed:
- shard-mtlp: NOTRUN -> [SKIP][13] ([i915#9323])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@gem_ccs@block-multicopy-compressed.html
* igt@gem_ccs@block-multicopy-inplace:
- shard-rkl: NOTRUN -> [SKIP][14] ([i915#3555] / [i915#9323])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-4/igt@gem_ccs@block-multicopy-inplace.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-tglu-1: NOTRUN -> [SKIP][15] ([i915#9323])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_ccs@large-ctrl-surf-copy:
- shard-rkl: NOTRUN -> [SKIP][16] ([i915#13008])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-4/igt@gem_ccs@large-ctrl-surf-copy.html
* igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-lmem0-lmem0:
- shard-dg2: NOTRUN -> [INCOMPLETE][17] ([i915#12392])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-2/igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-lmem0-lmem0.html
* igt@gem_close_race@multigpu-basic-process:
- shard-rkl: NOTRUN -> [SKIP][18] ([i915#7697])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-dg2: NOTRUN -> [ABORT][19] ([i915#13427])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@gem_create@create-ext-cpu-access-big.html
- shard-rkl: NOTRUN -> [SKIP][20] ([i915#6335])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-8/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_ctx_persistence@engines-cleanup:
- shard-snb: NOTRUN -> [SKIP][21] ([i915#1099])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-snb4/igt@gem_ctx_persistence@engines-cleanup.html
* igt@gem_ctx_persistence@saturated-hostile-nopreempt@rcs0:
- shard-dg2-9: NOTRUN -> [SKIP][22] ([i915#5882]) +7 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@gem_ctx_persistence@saturated-hostile-nopreempt@rcs0.html
* igt@gem_ctx_sseu@invalid-args:
- shard-dg2: NOTRUN -> [SKIP][23] ([i915#280])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@gem_ctx_sseu@invalid-args.html
* igt@gem_ctx_sseu@mmap-args:
- shard-rkl: NOTRUN -> [SKIP][24] ([i915#280])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-5/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_eio@hibernate:
- shard-dg2: [PASS][25] -> [ABORT][26] ([i915#10030] / [i915#7975] / [i915#8213])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg2-6/igt@gem_eio@hibernate.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-7/igt@gem_eio@hibernate.html
- shard-rkl: NOTRUN -> [ABORT][27] ([i915#7975] / [i915#8213])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-6/igt@gem_eio@hibernate.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-rkl: NOTRUN -> [SKIP][28] ([i915#4525])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-8/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-tglu: NOTRUN -> [SKIP][29] ([i915#4525]) +1 other test skip
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-7/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-tglu-1: NOTRUN -> [SKIP][30] ([i915#4525]) +1 other test skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_capture@capture-invisible:
- shard-dg2-9: NOTRUN -> [SKIP][31] ([i915#6334]) +2 other tests skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@gem_exec_capture@capture-invisible.html
* igt@gem_exec_capture@capture-invisible@smem0:
- shard-tglu: NOTRUN -> [SKIP][32] ([i915#6334]) +1 other test skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@gem_exec_capture@capture-invisible@smem0.html
* igt@gem_exec_endless@dispatch@rcs0:
- shard-tglu: NOTRUN -> [TIMEOUT][33] ([i915#3778]) +1 other test timeout
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-7/igt@gem_exec_endless@dispatch@rcs0.html
* igt@gem_exec_flush@basic-wb-ro-before-default:
- shard-dg2-9: NOTRUN -> [SKIP][34] ([i915#3539] / [i915#4852]) +2 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@gem_exec_flush@basic-wb-ro-before-default.html
* igt@gem_exec_reloc@basic-cpu-gtt-noreloc:
- shard-dg2: NOTRUN -> [SKIP][35] ([i915#3281]) +5 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html
* igt@gem_exec_reloc@basic-cpu-read-noreloc:
- shard-dg2-9: NOTRUN -> [SKIP][36] ([i915#3281]) +3 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@gem_exec_reloc@basic-cpu-read-noreloc.html
* igt@gem_exec_reloc@basic-gtt-wc-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][37] ([i915#3281]) +2 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html
* igt@gem_exec_schedule@deep@rcs0:
- shard-mtlp: NOTRUN -> [SKIP][38] ([i915#4537])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@gem_exec_schedule@deep@rcs0.html
* igt@gem_exec_schedule@preempt-queue-contexts:
- shard-mtlp: NOTRUN -> [SKIP][39] ([i915#4537] / [i915#4812]) +1 other test skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@gem_exec_schedule@preempt-queue-contexts.html
* igt@gem_exec_schedule@reorder-wide:
- shard-dg2-9: NOTRUN -> [SKIP][40] ([i915#4537] / [i915#4812])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@gem_exec_schedule@reorder-wide.html
* igt@gem_huc_copy@huc-copy:
- shard-rkl: NOTRUN -> [SKIP][41] ([i915#2190])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-tglu: NOTRUN -> [SKIP][42] ([i915#4613]) +2 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@gem_lmem_swapping@parallel-multi.html
- shard-mtlp: NOTRUN -> [SKIP][43] ([i915#4613])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-4/igt@gem_lmem_swapping@parallel-multi.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-rkl: NOTRUN -> [SKIP][44] ([i915#4613]) +6 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-6/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@random-engines:
- shard-tglu-1: NOTRUN -> [SKIP][45] ([i915#4613]) +1 other test skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify-random:
- shard-glk: NOTRUN -> [SKIP][46] ([i915#4613]) +2 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-glk5/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap_gtt@bad-object:
- shard-mtlp: NOTRUN -> [SKIP][47] ([i915#4077]) +2 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@gem_mmap_gtt@bad-object.html
* igt@gem_mmap_gtt@pf-nonblock:
- shard-dg2-9: NOTRUN -> [SKIP][48] ([i915#4077]) +3 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@gem_mmap_gtt@pf-nonblock.html
* igt@gem_mmap_gtt@zero-extend:
- shard-dg2: NOTRUN -> [SKIP][49] ([i915#4077]) +8 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@gem_mmap_gtt@zero-extend.html
* igt@gem_mmap_wc@fault-concurrent:
- shard-dg2-9: NOTRUN -> [SKIP][50] ([i915#4083]) +1 other test skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@gem_mmap_wc@fault-concurrent.html
* igt@gem_mmap_wc@write-read-distinct:
- shard-dg2: NOTRUN -> [SKIP][51] ([i915#4083])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@gem_mmap_wc@write-read-distinct.html
* igt@gem_partial_pwrite_pread@reads-display:
- shard-mtlp: NOTRUN -> [SKIP][52] ([i915#3282])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@gem_partial_pwrite_pread@reads-display.html
* igt@gem_partial_pwrite_pread@reads-uncached:
- shard-dg2-9: NOTRUN -> [SKIP][53] ([i915#3282]) +1 other test skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@gem_partial_pwrite_pread@reads-uncached.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- shard-rkl: NOTRUN -> [SKIP][54] ([i915#3282]) +7 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-1/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gem_pread@exhaustion:
- shard-tglu-1: NOTRUN -> [WARN][55] ([i915#2658])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@gem_pread@exhaustion.html
* igt@gem_pwrite@basic-exhaustion:
- shard-dg2: NOTRUN -> [SKIP][56] ([i915#3282]) +1 other test skip
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@create-protected-buffer:
- shard-rkl: [PASS][57] -> [TIMEOUT][58] ([i915#12964])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-rkl-8/igt@gem_pxp@create-protected-buffer.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@gem_pxp@create-protected-buffer.html
* igt@gem_pxp@create-valid-protected-context:
- shard-dg2: NOTRUN -> [SKIP][59] ([i915#4270])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@gem_pxp@create-valid-protected-context.html
* igt@gem_pxp@display-protected-crc:
- shard-rkl: NOTRUN -> [TIMEOUT][60] ([i915#12917] / [i915#12964]) +3 other tests timeout
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-4/igt@gem_pxp@display-protected-crc.html
- shard-dg2-9: NOTRUN -> [SKIP][61] ([i915#4270]) +1 other test skip
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@gem_pxp@display-protected-crc.html
* igt@gem_pxp@protected-encrypted-src-copy-not-readible:
- shard-rkl: [PASS][62] -> [TIMEOUT][63] ([i915#12917] / [i915#12964])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-rkl-8/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-6/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-rkl: NOTRUN -> [TIMEOUT][64] ([i915#12964]) +1 other test timeout
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs:
- shard-mtlp: NOTRUN -> [SKIP][65] ([i915#8428]) +1 other test skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs.html
* igt@gem_render_copy@y-tiled-ccs-to-y-tiled:
- shard-dg2: NOTRUN -> [SKIP][66] ([i915#5190] / [i915#8428]) +4 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@gem_render_copy@y-tiled-ccs-to-y-tiled.html
* igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled:
- shard-dg2-9: NOTRUN -> [SKIP][67] ([i915#5190] / [i915#8428]) +1 other test skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled.html
* igt@gem_set_tiling_vs_blt@untiled-to-tiled:
- shard-rkl: NOTRUN -> [SKIP][68] ([i915#8411]) +1 other test skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-6/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
* igt@gem_set_tiling_vs_gtt:
- shard-mtlp: NOTRUN -> [SKIP][69] ([i915#4079]) +1 other test skip
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@gem_set_tiling_vs_gtt.html
* igt@gem_softpin@evict-snoop:
- shard-dg2-9: NOTRUN -> [SKIP][70] ([i915#4885])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@gem_softpin@evict-snoop.html
* igt@gem_tiled_swapping@non-threaded:
- shard-rkl: [PASS][71] -> [FAIL][72] ([i915#12941])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-rkl-8/igt@gem_tiled_swapping@non-threaded.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-8/igt@gem_tiled_swapping@non-threaded.html
* igt@gem_userptr_blits@access-control:
- shard-mtlp: NOTRUN -> [SKIP][73] ([i915#3297]) +1 other test skip
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-4/igt@gem_userptr_blits@access-control.html
* igt@gem_userptr_blits@coherency-sync:
- shard-dg2-9: NOTRUN -> [SKIP][74] ([i915#3297])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@gem_userptr_blits@coherency-sync.html
* igt@gem_userptr_blits@coherency-unsync:
- shard-tglu: NOTRUN -> [SKIP][75] ([i915#3297]) +1 other test skip
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@gem_userptr_blits@coherency-unsync.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-dg2: NOTRUN -> [SKIP][76] ([i915#3297])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@gem_userptr_blits@create-destroy-unsync.html
- shard-rkl: NOTRUN -> [SKIP][77] ([i915#3297]) +4 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-8/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-rkl: NOTRUN -> [SKIP][78] ([i915#3297] / [i915#3323])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-4/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@forbidden-operations:
- shard-rkl: NOTRUN -> [SKIP][79] ([i915#3282] / [i915#3297])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-1/igt@gem_userptr_blits@forbidden-operations.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-dg2: NOTRUN -> [SKIP][80] ([i915#3297] / [i915#4880])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_workarounds@reset:
- shard-mtlp: [PASS][81] -> [ABORT][82] ([i915#13193]) +2 other tests abort
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-mtlp-8/igt@gem_workarounds@reset.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-7/igt@gem_workarounds@reset.html
* igt@gen9_exec_parse@allowed-single:
- shard-dg2-9: NOTRUN -> [SKIP][83] ([i915#2856])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@gen9_exec_parse@allowed-single.html
- shard-glk: NOTRUN -> [ABORT][84] ([i915#5566])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-glk3/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@basic-rejected:
- shard-tglu: NOTRUN -> [SKIP][85] ([i915#2527] / [i915#2856]) +1 other test skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@gen9_exec_parse@basic-rejected.html
- shard-mtlp: NOTRUN -> [SKIP][86] ([i915#2856]) +1 other test skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-4/igt@gen9_exec_parse@basic-rejected.html
* igt@gen9_exec_parse@bb-start-far:
- shard-tglu-1: NOTRUN -> [SKIP][87] ([i915#2527] / [i915#2856]) +1 other test skip
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@gen9_exec_parse@bb-start-far.html
* igt@gen9_exec_parse@valid-registers:
- shard-dg2: NOTRUN -> [SKIP][88] ([i915#2856]) +1 other test skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@gen9_exec_parse@valid-registers.html
- shard-rkl: NOTRUN -> [SKIP][89] ([i915#2527]) +4 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-8/igt@gen9_exec_parse@valid-registers.html
* igt@i915_pm_freq_api@freq-basic-api:
- shard-rkl: NOTRUN -> [SKIP][90] ([i915#8399])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-4/igt@i915_pm_freq_api@freq-basic-api.html
* igt@i915_pm_freq_api@freq-suspend:
- shard-tglu: NOTRUN -> [SKIP][91] ([i915#8399]) +2 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-7/igt@i915_pm_freq_api@freq-suspend.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-dg1: [PASS][92] -> [FAIL][93] ([i915#3591]) +1 other test fail
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_pm_rpm@system-suspend:
- shard-glk: NOTRUN -> [INCOMPLETE][94] ([i915#12797])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-glk8/igt@i915_pm_rpm@system-suspend.html
* igt@i915_pm_rps@min-max-config-idle:
- shard-dg2: NOTRUN -> [SKIP][95] ([i915#11681] / [i915#6621])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@i915_pm_rps@min-max-config-idle.html
* igt@i915_power@sanity:
- shard-mtlp: [PASS][96] -> [SKIP][97] ([i915#7984])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-mtlp-4/igt@i915_power@sanity.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-5/igt@i915_power@sanity.html
* igt@i915_query@hwconfig_table:
- shard-tglu: NOTRUN -> [SKIP][98] ([i915#6245])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@i915_query@hwconfig_table.html
* igt@i915_query@test-query-geometry-subslices:
- shard-rkl: NOTRUN -> [SKIP][99] ([i915#5723])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@i915_query@test-query-geometry-subslices.html
* igt@i915_selftest@mock@memory_region:
- shard-rkl: NOTRUN -> [DMESG-WARN][100] ([i915#9311]) +1 other test dmesg-warn
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-5/igt@i915_selftest@mock@memory_region.html
* igt@i915_suspend@fence-restore-untiled:
- shard-rkl: NOTRUN -> [INCOMPLETE][101] ([i915#4817])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-3/igt@i915_suspend@fence-restore-untiled.html
* igt@intel_hwmon@hwmon-read:
- shard-tglu: NOTRUN -> [SKIP][102] ([i915#7707])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-7/igt@intel_hwmon@hwmon-read.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- shard-dg2: NOTRUN -> [SKIP][103] ([i915#4212]) +1 other test skip
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@kms_addfb_basic@basic-x-tiled-legacy.html
* igt@kms_addfb_basic@clobberred-modifier:
- shard-mtlp: NOTRUN -> [SKIP][104] ([i915#4212])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@kms_addfb_basic@clobberred-modifier.html
* igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
- shard-rkl: NOTRUN -> [SKIP][105] ([i915#12454] / [i915#12712])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-1/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
* igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-c-hdmi-a-2-y-rc-ccs-cc:
- shard-rkl: NOTRUN -> [SKIP][106] ([i915#8709])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-8/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-c-hdmi-a-2-y-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-4-y-rc-ccs-cc:
- shard-dg1: NOTRUN -> [SKIP][107] ([i915#8709]) +3 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-16/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-4-y-rc-ccs-cc.html
* igt@kms_async_flips@crc:
- shard-rkl: NOTRUN -> [DMESG-WARN][108] ([i915#12964]) +24 other tests dmesg-warn
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-5/igt@kms_async_flips@crc.html
* igt@kms_async_flips@invalid-async-flip-atomic:
- shard-mtlp: NOTRUN -> [SKIP][109] ([i915#12967])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@kms_async_flips@invalid-async-flip-atomic.html
* igt@kms_async_flips@test-cursor:
- shard-mtlp: NOTRUN -> [SKIP][110] ([i915#10333])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-4/igt@kms_async_flips@test-cursor.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-mtlp: NOTRUN -> [SKIP][111] ([i915#3555])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-mtlp: NOTRUN -> [SKIP][112] ([i915#1769] / [i915#3555])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@kms_atomic_transition@plane-all-modeset-transition.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-tglu: NOTRUN -> [SKIP][113] ([i915#1769] / [i915#3555])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-7/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-0:
- shard-tglu-1: NOTRUN -> [SKIP][114] ([i915#5286]) +5 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
- shard-tglu: NOTRUN -> [SKIP][115] ([i915#5286]) +3 other tests skip
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-7/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-rkl: NOTRUN -> [SKIP][116] ([i915#5286]) +7 other tests skip
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-4/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-mtlp: [PASS][117] -> [FAIL][118] ([i915#5138])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@linear-16bpp-rotate-270:
- shard-dg2-9: NOTRUN -> [SKIP][119] +3 other tests skip
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_big_fb@linear-16bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][120] ([i915#3638]) +5 other tests skip
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-180:
- shard-dg1: [PASS][121] -> [DMESG-WARN][122] ([i915#4423]) +9 other tests dmesg-warn
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg1-15/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-13/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-dg2: NOTRUN -> [SKIP][123] ([i915#4538] / [i915#5190]) +5 other tests skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
- shard-dg2-9: NOTRUN -> [SKIP][124] ([i915#4538] / [i915#5190]) +4 other tests skip
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-addfb:
- shard-mtlp: NOTRUN -> [SKIP][125] ([i915#6187])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@kms_big_fb@yf-tiled-addfb.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0:
- shard-tglu-1: NOTRUN -> [SKIP][126] +64 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2:
- shard-glk: NOTRUN -> [SKIP][127] +209 other tests skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-glk5/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2.html
* igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][128] ([i915#10307] / [i915#10434] / [i915#6095])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1.html
* igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc:
- shard-dg2-9: NOTRUN -> [SKIP][129] ([i915#10307] / [i915#6095]) +14 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs:
- shard-rkl: NOTRUN -> [SKIP][130] ([i915#12313]) +1 other test skip
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][131] ([i915#6095]) +34 other tests skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-d-edp-1.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
- shard-dg2-9: NOTRUN -> [SKIP][132] ([i915#12313])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs@pipe-d-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][133] ([i915#6095]) +141 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-13/igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs@pipe-d-hdmi-a-3.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-tglu: NOTRUN -> [SKIP][134] ([i915#12805])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-2:
- shard-dg2-9: NOTRUN -> [SKIP][135] ([i915#6095]) +4 other tests skip
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][136] ([i915#6095]) +7 other tests skip
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-4:
- shard-dg1: NOTRUN -> [DMESG-WARN][137] ([i915#4423])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-17/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-4.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
- shard-tglu: NOTRUN -> [SKIP][138] ([i915#12313]) +1 other test skip
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-7/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][139] ([i915#10307] / [i915#6095]) +118 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3.html
* igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1:
- shard-tglu-1: NOTRUN -> [SKIP][140] ([i915#6095]) +54 other tests skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][141] ([i915#12313])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc:
- shard-tglu: NOTRUN -> [SKIP][142] ([i915#6095]) +39 other tests skip
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][143] ([i915#6095]) +102 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-5/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-a-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][144] ([i915#4423] / [i915#6095]) +1 other test skip
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-13/igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-a-hdmi-a-3.html
* igt@kms_cdclk@mode-transition:
- shard-rkl: NOTRUN -> [SKIP][145] ([i915#3742]) +1 other test skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-8/igt@kms_cdclk@mode-transition.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][146] ([i915#13781]) +4 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html
* igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][147] ([i915#13783]) +3 other tests skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-5/igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3.html
* igt@kms_chamelium_audio@hdmi-audio-edid:
- shard-tglu-1: NOTRUN -> [SKIP][148] ([i915#11151] / [i915#7828]) +6 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_chamelium_audio@hdmi-audio-edid.html
* igt@kms_chamelium_color@degamma:
- shard-dg2: NOTRUN -> [SKIP][149] +4 other tests skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@kms_chamelium_color@degamma.html
* igt@kms_chamelium_edid@hdmi-edid-read:
- shard-rkl: NOTRUN -> [SKIP][150] ([i915#11151] / [i915#7828]) +14 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-8/igt@kms_chamelium_edid@hdmi-edid-read.html
* igt@kms_chamelium_frames@hdmi-cmp-planar-formats:
- shard-dg2: NOTRUN -> [SKIP][151] ([i915#11151] / [i915#7828]) +3 other tests skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html
* igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode:
- shard-tglu: NOTRUN -> [SKIP][152] ([i915#11151] / [i915#7828]) +5 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-7/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html
* igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode:
- shard-dg2-9: NOTRUN -> [SKIP][153] ([i915#11151] / [i915#7828]) +2 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode.html
* igt@kms_chamelium_hpd@vga-hpd-without-ddc:
- shard-mtlp: NOTRUN -> [SKIP][154] ([i915#11151] / [i915#7828]) +2 other tests skip
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@kms_chamelium_hpd@vga-hpd-without-ddc.html
* igt@kms_color@deep-color:
- shard-dg2: NOTRUN -> [SKIP][155] ([i915#3555]) +3 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@kms_color@deep-color.html
* igt@kms_content_protection@atomic-dpms:
- shard-rkl: NOTRUN -> [SKIP][156] ([i915#7118] / [i915#9424]) +1 other test skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-tglu: NOTRUN -> [SKIP][157] ([i915#3116] / [i915#3299]) +1 other test skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-mtlp: NOTRUN -> [SKIP][158] ([i915#3299])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-4/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@lic-type-0:
- shard-rkl: NOTRUN -> [SKIP][159] ([i915#9424]) +1 other test skip
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-1/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@lic-type-1:
- shard-dg2: NOTRUN -> [SKIP][160] ([i915#9424])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@kms_content_protection@lic-type-1.html
* igt@kms_content_protection@mei-interface:
- shard-tglu-1: NOTRUN -> [SKIP][161] ([i915#6944] / [i915#9424]) +1 other test skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@srm:
- shard-tglu-1: NOTRUN -> [SKIP][162] ([i915#6944] / [i915#7116] / [i915#7118])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_content_protection@srm.html
* igt@kms_content_protection@srm@pipe-a-dp-3:
- shard-dg2: NOTRUN -> [FAIL][163] ([i915#7173])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-11/igt@kms_content_protection@srm@pipe-a-dp-3.html
* igt@kms_content_protection@type1:
- shard-tglu: NOTRUN -> [SKIP][164] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-7/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@cursor-offscreen-512x512:
- shard-tglu: NOTRUN -> [SKIP][165] ([i915#13049])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@kms_cursor_crc@cursor-offscreen-512x512.html
* igt@kms_cursor_crc@cursor-onscreen-32x32:
- shard-tglu-1: NOTRUN -> [SKIP][166] ([i915#3555]) +4 other tests skip
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_cursor_crc@cursor-onscreen-32x32.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-dg2-9: NOTRUN -> [SKIP][167] ([i915#13049]) +1 other test skip
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-onscreen-64x21@pipe-a-hdmi-a-1:
- shard-tglu: NOTRUN -> [FAIL][168] ([i915#13566]) +1 other test fail
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@kms_cursor_crc@cursor-onscreen-64x21@pipe-a-hdmi-a-1.html
* igt@kms_cursor_crc@cursor-onscreen-max-size:
- shard-tglu: NOTRUN -> [SKIP][169] ([i915#3555])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-7/igt@kms_cursor_crc@cursor-onscreen-max-size.html
* igt@kms_cursor_crc@cursor-random-128x42:
- shard-rkl: NOTRUN -> [FAIL][170] ([i915#13566]) +1 other test fail
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-5/igt@kms_cursor_crc@cursor-random-128x42.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-rkl: NOTRUN -> [SKIP][171] ([i915#13049]) +2 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-dg2: NOTRUN -> [SKIP][172] ([i915#13049])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_cursor_crc@cursor-random-64x21:
- shard-tglu: [PASS][173] -> [FAIL][174] ([i915#13566]) +1 other test fail
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-tglu-5/igt@kms_cursor_crc@cursor-random-64x21.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-9/igt@kms_cursor_crc@cursor-random-64x21.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-mtlp: NOTRUN -> [SKIP][175] ([i915#13049])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_cursor_crc@cursor-sliding-256x85:
- shard-mtlp: NOTRUN -> [SKIP][176] ([i915#8814]) +1 other test skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-4/igt@kms_cursor_crc@cursor-sliding-256x85.html
* igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-1:
- shard-tglu-1: NOTRUN -> [FAIL][177] ([i915#13566]) +1 other test fail
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-1.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-dg2-9: NOTRUN -> [SKIP][178] ([i915#13046] / [i915#5354]) +1 other test skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- shard-rkl: NOTRUN -> [SKIP][179] ([i915#4103]) +1 other test skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
- shard-rkl: NOTRUN -> [SKIP][180] +35 other tests skip
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-5/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
- shard-dg2: NOTRUN -> [SKIP][181] ([i915#13046] / [i915#5354]) +1 other test skip
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-mtlp: NOTRUN -> [SKIP][182] ([i915#9809])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-3/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
- shard-dg2: NOTRUN -> [SKIP][183] ([i915#9067])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
- shard-rkl: NOTRUN -> [SKIP][184] ([i915#9067])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-8/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-tglu: NOTRUN -> [SKIP][185] ([i915#4103])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
- shard-mtlp: NOTRUN -> [SKIP][186] ([i915#4213])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-4/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_dirtyfb@psr-dirtyfb-ioctl:
- shard-rkl: NOTRUN -> [SKIP][187] ([i915#9723])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
* igt@kms_display_modes@extended-mode-basic:
- shard-rkl: NOTRUN -> [SKIP][188] ([i915#13691])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc:
- shard-dg2: [PASS][189] -> [SKIP][190] ([i915#3555])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg2-11/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-2/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
- shard-rkl: NOTRUN -> [SKIP][191] ([i915#3555] / [i915#3804])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-5/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][192] ([i915#3804])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-5/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc:
- shard-dg2-9: NOTRUN -> [SKIP][193] ([i915#3555])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
* igt@kms_dp_aux_dev:
- shard-tglu-1: NOTRUN -> [SKIP][194] ([i915#1257])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_dp_aux_dev.html
* igt@kms_dp_link_training@uhbr-mst:
- shard-tglu-1: NOTRUN -> [SKIP][195] ([i915#13748])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_dp_link_training@uhbr-mst.html
* igt@kms_dp_linktrain_fallback@dp-fallback:
- shard-tglu: NOTRUN -> [SKIP][196] ([i915#13707])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-7/igt@kms_dp_linktrain_fallback@dp-fallback.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-tglu: NOTRUN -> [SKIP][197] ([i915#3840])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@kms_dsc@dsc-fractional-bpp.html
- shard-mtlp: NOTRUN -> [SKIP][198] ([i915#3840] / [i915#9688])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-4/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-dg2: NOTRUN -> [SKIP][199] ([i915#3840])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
- shard-rkl: NOTRUN -> [SKIP][200] ([i915#3840])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-8/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
* igt@kms_dsc@dsc-with-bpc:
- shard-dg2: NOTRUN -> [SKIP][201] ([i915#3555] / [i915#3840])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-rkl: NOTRUN -> [SKIP][202] ([i915#3555] / [i915#3840])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-tglu-1: NOTRUN -> [SKIP][203] ([i915#3840] / [i915#9053])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
- shard-mtlp: NOTRUN -> [SKIP][204] ([i915#13798])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-glk: NOTRUN -> [INCOMPLETE][205] ([i915#9878])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-glk9/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_fbcon_fbt@psr:
- shard-tglu: NOTRUN -> [SKIP][206] ([i915#3469])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@kms_fbcon_fbt@psr.html
- shard-dg2-9: NOTRUN -> [SKIP][207] ([i915#3469])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_fbcon_fbt@psr.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-rkl: NOTRUN -> [SKIP][208] ([i915#3955])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_feature_discovery@chamelium:
- shard-rkl: NOTRUN -> [SKIP][209] ([i915#4854])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-4/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@psr1:
- shard-dg2-9: NOTRUN -> [SKIP][210] ([i915#658])
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_feature_discovery@psr1.html
- shard-rkl: NOTRUN -> [SKIP][211] ([i915#658])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-4/igt@kms_feature_discovery@psr1.html
* igt@kms_feature_discovery@psr2:
- shard-tglu: NOTRUN -> [SKIP][212] ([i915#658])
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@kms_feature_discovery@psr2.html
* igt@kms_fence_pin_leak:
- shard-dg2: NOTRUN -> [SKIP][213] ([i915#4881])
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@kms_fence_pin_leak.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
- shard-tglu: NOTRUN -> [SKIP][214] ([i915#3637]) +6 other tests skip
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html
* igt@kms_flip@2x-flip-vs-dpms:
- shard-tglu-1: NOTRUN -> [SKIP][215] ([i915#3637]) +4 other tests skip
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_flip@2x-flip-vs-dpms.html
* igt@kms_flip@2x-flip-vs-panning:
- shard-dg2: NOTRUN -> [SKIP][216] ([i915#9934]) +1 other test skip
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@kms_flip@2x-flip-vs-panning.html
* igt@kms_flip@2x-flip-vs-panning-vs-hang:
- shard-rkl: NOTRUN -> [SKIP][217] ([i915#9934]) +8 other tests skip
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-1/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
* igt@kms_flip@2x-flip-vs-rmfb-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][218] ([i915#3637]) +2 other tests skip
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-dg2-9: NOTRUN -> [SKIP][219] ([i915#9934])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_flip@blocking-wf_vblank@c-hdmi-a1:
- shard-tglu: [PASS][220] -> [FAIL][221] ([i915#13734]) +3 other tests fail
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-tglu-9/igt@kms_flip@blocking-wf_vblank@c-hdmi-a1.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-4/igt@kms_flip@blocking-wf_vblank@c-hdmi-a1.html
* igt@kms_flip@flip-vs-fences:
- shard-dg2-9: NOTRUN -> [SKIP][222] ([i915#8381]) +1 other test skip
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_flip@flip-vs-fences.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-hdmi-a2:
- shard-rkl: NOTRUN -> [FAIL][223] ([i915#13734]) +2 other tests fail
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-5/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-hdmi-a2.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
- shard-rkl: NOTRUN -> [SKIP][224] ([i915#2672] / [i915#3555]) +5 other tests skip
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][225] ([i915#2672]) +5 other tests skip
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][226] ([i915#2587] / [i915#2672]) +2 other tests skip
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling:
- shard-dg2: NOTRUN -> [SKIP][227] ([i915#2672] / [i915#3555])
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][228] ([i915#2672]) +2 other tests skip
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling:
- shard-tglu: NOTRUN -> [SKIP][229] ([i915#2672] / [i915#3555]) +1 other test skip
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
- shard-tglu: NOTRUN -> [SKIP][230] ([i915#2587] / [i915#2672] / [i915#3555])
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
- shard-mtlp: NOTRUN -> [SKIP][231] ([i915#2672] / [i915#3555] / [i915#8813])
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][232] ([i915#2672] / [i915#8813])
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
- shard-tglu-1: NOTRUN -> [SKIP][233] ([i915#2587] / [i915#2672] / [i915#3555]) +1 other test skip
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
- shard-tglu-1: NOTRUN -> [SKIP][234] ([i915#2672] / [i915#3555]) +2 other tests skip
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-tglu-1: NOTRUN -> [SKIP][235] ([i915#2587] / [i915#2672]) +4 other tests skip
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
- shard-dg2-9: NOTRUN -> [SKIP][236] ([i915#2672] / [i915#3555] / [i915#5190])
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-dg2-9: NOTRUN -> [SKIP][237] ([i915#2672])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling:
- shard-dg2: NOTRUN -> [SKIP][238] ([i915#2672] / [i915#3555] / [i915#5190]) +1 other test skip
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
- shard-mtlp: NOTRUN -> [SKIP][239] ([i915#1825]) +10 other tests skip
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt:
- shard-dg2: NOTRUN -> [SKIP][240] ([i915#5354]) +18 other tests skip
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen:
- shard-dg2-9: NOTRUN -> [SKIP][241] ([i915#5354]) +14 other tests skip
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][242] ([i915#8708]) +2 other tests skip
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][243] ([i915#8708]) +4 other tests skip
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][244] ([i915#1825]) +66 other tests skip
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
- shard-rkl: NOTRUN -> [SKIP][245] ([i915#3023]) +35 other tests skip
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-rkl: NOTRUN -> [SKIP][246] ([i915#5439])
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt:
- shard-dg2-9: NOTRUN -> [SKIP][247] ([i915#3458]) +5 other tests skip
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][248] ([i915#3458]) +6 other tests skip
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
- shard-tglu: NOTRUN -> [SKIP][249] +59 other tests skip
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-dg2-9: NOTRUN -> [SKIP][250] ([i915#8708]) +6 other tests skip
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_hdr@brightness-with-hdr:
- shard-rkl: NOTRUN -> [SKIP][251] ([i915#12713])
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_hdr@invalid-hdr:
- shard-tglu-1: NOTRUN -> [SKIP][252] ([i915#3555] / [i915#8228])
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_hdr@invalid-hdr.html
* igt@kms_hdr@static-toggle-suspend:
- shard-dg2: NOTRUN -> [SKIP][253] ([i915#3555] / [i915#8228]) +1 other test skip
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@kms_hdr@static-toggle-suspend.html
- shard-rkl: NOTRUN -> [SKIP][254] ([i915#3555] / [i915#8228]) +1 other test skip
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-8/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_joiner@basic-force-ultra-joiner:
- shard-mtlp: NOTRUN -> [SKIP][255] ([i915#10656])
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@kms_joiner@basic-force-ultra-joiner.html
* igt@kms_joiner@basic-ultra-joiner:
- shard-rkl: NOTRUN -> [SKIP][256] ([i915#12339])
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@kms_joiner@basic-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-big-joiner:
- shard-tglu: NOTRUN -> [SKIP][257] ([i915#10656])
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@kms_joiner@invalid-modeset-big-joiner.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- shard-tglu: NOTRUN -> [SKIP][258] ([i915#12388])
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@kms_joiner@invalid-modeset-force-big-joiner.html
- shard-dg2-9: NOTRUN -> [SKIP][259] ([i915#12388])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@kms_joiner@invalid-modeset-force-ultra-joiner:
- shard-rkl: NOTRUN -> [SKIP][260] ([i915#12394])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-1/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-mtlp: NOTRUN -> [SKIP][261] ([i915#4816])
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_panel_fitting@legacy:
- shard-dg2: NOTRUN -> [SKIP][262] ([i915#6301])
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@kms_panel_fitting@legacy.html
- shard-rkl: NOTRUN -> [SKIP][263] ([i915#6301])
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-8/igt@kms_panel_fitting@legacy.html
* igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes:
- shard-mtlp: NOTRUN -> [SKIP][264] +6 other tests skip
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-4/igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- shard-rkl: [PASS][265] -> [INCOMPLETE][266] ([i915#13476])
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-rkl-8/igt@kms_pipe_crc_basic@suspend-read-crc.html
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@kms_pipe_crc_basic@suspend-read-crc.html
* igt@kms_plane_alpha_blend@alpha-opaque-fb:
- shard-glk: NOTRUN -> [FAIL][267] ([i915#10647] / [i915#12169])
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-glk1/igt@kms_plane_alpha_blend@alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [FAIL][268] ([i915#10647]) +1 other test fail
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-glk1/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1.html
* igt@kms_plane_multiple@2x-tiling-4:
- shard-tglu: NOTRUN -> [SKIP][269] ([i915#13958]) +1 other test skip
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-7/igt@kms_plane_multiple@2x-tiling-4.html
* igt@kms_plane_multiple@2x-tiling-none:
- shard-mtlp: NOTRUN -> [SKIP][270] ([i915#13958])
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-4/igt@kms_plane_multiple@2x-tiling-none.html
* igt@kms_plane_multiple@2x-tiling-yf:
- shard-tglu-1: NOTRUN -> [SKIP][271] ([i915#13958])
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_plane_multiple@2x-tiling-yf.html
* igt@kms_plane_multiple@tiling-yf:
- shard-rkl: NOTRUN -> [SKIP][272] ([i915#3555]) +10 other tests skip
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-dg2: [PASS][273] -> [SKIP][274] ([i915#6953] / [i915#9423])
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg2-11/igt@kms_plane_scaling@intel-max-src-size.html
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-2/igt@kms_plane_scaling@intel-max-src-size.html
- shard-rkl: NOTRUN -> [SKIP][275] ([i915#6953])
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-5/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a:
- shard-mtlp: NOTRUN -> [SKIP][276] ([i915#12247]) +4 other tests skip
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-4/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-c:
- shard-tglu: NOTRUN -> [SKIP][277] ([i915#12247]) +4 other tests skip
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-c.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a:
- shard-rkl: NOTRUN -> [SKIP][278] ([i915#12247]) +13 other tests skip
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25:
- shard-dg2: NOTRUN -> [SKIP][279] ([i915#12247] / [i915#6953] / [i915#9423])
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@kms_plane_scaling@planes-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b:
- shard-tglu-1: NOTRUN -> [SKIP][280] ([i915#12247]) +8 other tests skip
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25:
- shard-rkl: NOTRUN -> [SKIP][281] ([i915#12247] / [i915#6953]) +1 other test skip
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-1/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d:
- shard-dg2: NOTRUN -> [SKIP][282] ([i915#12247]) +3 other tests skip
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25:
- shard-tglu-1: NOTRUN -> [SKIP][283] ([i915#12247] / [i915#6953])
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html
* igt@kms_pm_backlight@brightness-with-dpms:
- shard-rkl: NOTRUN -> [SKIP][284] ([i915#12343])
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-1/igt@kms_pm_backlight@brightness-with-dpms.html
* igt@kms_pm_backlight@fade:
- shard-tglu-1: NOTRUN -> [SKIP][285] ([i915#9812])
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_pm_backlight@fade.html
* igt@kms_pm_backlight@fade-with-dpms:
- shard-rkl: NOTRUN -> [SKIP][286] ([i915#5354]) +1 other test skip
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-4/igt@kms_pm_backlight@fade-with-dpms.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-tglu-1: NOTRUN -> [SKIP][287] ([i915#9685])
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_pm_dc@dc5-retention-flops:
- shard-rkl: NOTRUN -> [SKIP][288] ([i915#3828])
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-5/igt@kms_pm_dc@dc5-retention-flops.html
* igt@kms_pm_dc@dc6-psr:
- shard-tglu: NOTRUN -> [SKIP][289] ([i915#9685])
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@kms_pm_dc@dc6-psr.html
- shard-mtlp: [PASS][290] -> [FAIL][291] ([i915#12912])
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-mtlp-7/igt@kms_pm_dc@dc6-psr.html
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-4/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_dc@dc9-dpms:
- shard-rkl: [PASS][292] -> [SKIP][293] ([i915#3361])
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-rkl-6/igt@kms_pm_dc@dc9-dpms.html
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-8/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_pm_lpsp@screens-disabled:
- shard-dg2: NOTRUN -> [SKIP][294] ([i915#8430])
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@kms_pm_lpsp@screens-disabled.html
- shard-rkl: NOTRUN -> [SKIP][295] ([i915#8430])
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-8/igt@kms_pm_lpsp@screens-disabled.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-dg2: [PASS][296] -> [SKIP][297] ([i915#9519])
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg2-8/igt@kms_pm_rpm@modeset-lpsp.html
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-7/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-rkl: NOTRUN -> [SKIP][298] ([i915#9519])
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-rkl: [PASS][299] -> [SKIP][300] ([i915#9519])
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-rkl-3/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_pm_rpm@pm-caching:
- shard-rkl: [PASS][301] -> [DMESG-WARN][302] ([i915#12964]) +1 other test dmesg-warn
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-rkl-8/igt@kms_pm_rpm@pm-caching.html
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-6/igt@kms_pm_rpm@pm-caching.html
* igt@kms_prime@basic-crc-hybrid:
- shard-rkl: NOTRUN -> [SKIP][303] ([i915#6524]) +1 other test skip
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf:
- shard-mtlp: NOTRUN -> [SKIP][304] ([i915#12316])
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-4/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf:
- shard-glk: NOTRUN -> [SKIP][305] ([i915#11520]) +5 other tests skip
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-glk9/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
- shard-snb: NOTRUN -> [SKIP][306] ([i915#11520]) +1 other test skip
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-snb4/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@pr-cursor-plane-update-sf:
- shard-tglu: NOTRUN -> [SKIP][307] ([i915#11520]) +6 other tests skip
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-7/igt@kms_psr2_sf@pr-cursor-plane-update-sf.html
* igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
- shard-rkl: NOTRUN -> [SKIP][308] ([i915#11520]) +15 other tests skip
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area:
- shard-dg2-9: NOTRUN -> [SKIP][309] ([i915#11520]) +3 other tests skip
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf:
- shard-tglu-1: NOTRUN -> [SKIP][310] ([i915#11520]) +5 other tests skip
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area:
- shard-dg2: NOTRUN -> [SKIP][311] ([i915#11520]) +3 other tests skip
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-dg2: NOTRUN -> [SKIP][312] ([i915#9683])
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-p010:
- shard-tglu: NOTRUN -> [SKIP][313] ([i915#9683])
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@kms_psr2_su@page_flip-p010.html
- shard-mtlp: NOTRUN -> [SKIP][314] ([i915#4348])
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-4/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-rkl: NOTRUN -> [SKIP][315] ([i915#9683]) +2 other tests skip
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-1/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-psr-sprite-render:
- shard-mtlp: NOTRUN -> [SKIP][316] ([i915#9688]) +7 other tests skip
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-4/igt@kms_psr@fbc-psr-sprite-render.html
* igt@kms_psr@fbc-psr2-primary-mmap-gtt:
- shard-tglu: NOTRUN -> [SKIP][317] ([i915#9732]) +12 other tests skip
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@kms_psr@fbc-psr2-primary-mmap-gtt.html
* igt@kms_psr@psr-cursor-blt:
- shard-dg2-9: NOTRUN -> [SKIP][318] ([i915#1072] / [i915#9732]) +8 other tests skip
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_psr@psr-cursor-blt.html
* igt@kms_psr@psr-cursor-render:
- shard-dg2: NOTRUN -> [SKIP][319] ([i915#1072] / [i915#9732]) +8 other tests skip
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@kms_psr@psr-cursor-render.html
* igt@kms_psr@psr2-cursor-mmap-gtt:
- shard-tglu-1: NOTRUN -> [SKIP][320] ([i915#9732]) +17 other tests skip
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_psr@psr2-cursor-mmap-gtt.html
* igt@kms_psr@psr2-sprite-mmap-cpu:
- shard-rkl: NOTRUN -> [SKIP][321] ([i915#1072] / [i915#9732]) +34 other tests skip
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@kms_psr@psr2-sprite-mmap-cpu.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-rkl: NOTRUN -> [SKIP][322] ([i915#9685]) +1 other test skip
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
- shard-tglu: NOTRUN -> [SKIP][323] ([i915#5289])
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-rkl: NOTRUN -> [SKIP][324] ([i915#5289])
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
- shard-dg2-9: NOTRUN -> [SKIP][325] ([i915#5190])
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-mtlp: NOTRUN -> [SKIP][326] ([i915#12755])
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-dg2: NOTRUN -> [SKIP][327] ([i915#12755]) +1 other test skip
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@kms_vrr@flip-suspend:
- shard-mtlp: NOTRUN -> [SKIP][328] ([i915#3555] / [i915#8808])
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@kms_vrr@flip-suspend.html
* igt@kms_vrr@negative-basic:
- shard-rkl: NOTRUN -> [SKIP][329] ([i915#3555] / [i915#9906])
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@kms_vrr@negative-basic.html
* igt@kms_vrr@seamless-rr-switch-drrs:
- shard-tglu-1: NOTRUN -> [SKIP][330] ([i915#9906])
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_vrr@seamless-rr-switch-drrs.html
* igt@kms_vrr@seamless-rr-switch-virtual:
- shard-dg2-9: NOTRUN -> [SKIP][331] ([i915#9906])
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@kms_vrr@seamless-rr-switch-virtual.html
* igt@kms_vrr@seamless-rr-switch-vrr:
- shard-rkl: NOTRUN -> [SKIP][332] ([i915#9906]) +1 other test skip
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-8/igt@kms_vrr@seamless-rr-switch-vrr.html
* igt@kms_writeback@writeback-check-output:
- shard-dg2: NOTRUN -> [SKIP][333] ([i915#2437])
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-check-output-xrgb2101010:
- shard-tglu-1: NOTRUN -> [SKIP][334] ([i915#2437] / [i915#9412])
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@kms_writeback@writeback-check-output-xrgb2101010.html
* igt@kms_writeback@writeback-fb-id:
- shard-rkl: NOTRUN -> [SKIP][335] ([i915#2437])
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-6/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-rkl: NOTRUN -> [SKIP][336] ([i915#2437] / [i915#9412]) +1 other test skip
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-4/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf_pmu@enable-race@bcs0:
- shard-snb: NOTRUN -> [SKIP][337] +51 other tests skip
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-snb4/igt@perf_pmu@enable-race@bcs0.html
* igt@perf_pmu@module-unload:
- shard-dg1: [PASS][338] -> [INCOMPLETE][339] ([i915#13520])
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg1-14/igt@perf_pmu@module-unload.html
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-12/igt@perf_pmu@module-unload.html
* igt@perf_pmu@rc6-all-gts:
- shard-rkl: NOTRUN -> [SKIP][340] ([i915#8516])
[340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@perf_pmu@rc6-all-gts.html
* igt@perf_pmu@rc6-suspend:
- shard-glk: [PASS][341] -> [INCOMPLETE][342] ([i915#13356])
[341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-glk9/igt@perf_pmu@rc6-suspend.html
[342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-glk4/igt@perf_pmu@rc6-suspend.html
* igt@prime_vgem@basic-fence-mmap:
- shard-dg2: NOTRUN -> [SKIP][343] ([i915#3708] / [i915#4077])
[343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- shard-dg2-9: NOTRUN -> [SKIP][344] ([i915#3291] / [i915#3708])
[344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-gtt:
- shard-dg2-9: NOTRUN -> [SKIP][345] ([i915#3708] / [i915#4077])
[345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@coherency-gtt:
- shard-mtlp: NOTRUN -> [SKIP][346] ([i915#3708] / [i915#4077])
[346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@prime_vgem@coherency-gtt.html
* igt@prime_vgem@fence-flip-hang:
- shard-rkl: NOTRUN -> [SKIP][347] ([i915#3708])
[347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-4/igt@prime_vgem@fence-flip-hang.html
* igt@sriov_basic@bind-unbind-vf:
- shard-dg2: NOTRUN -> [SKIP][348] ([i915#9917])
[348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@sriov_basic@bind-unbind-vf.html
* igt@sriov_basic@enable-vfs-autoprobe-off:
- shard-rkl: NOTRUN -> [SKIP][349] ([i915#9917])
[349]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-1/igt@sriov_basic@enable-vfs-autoprobe-off.html
* igt@sriov_basic@enable-vfs-autoprobe-on@numvfs-7:
- shard-tglu-1: NOTRUN -> [FAIL][350] ([i915#12910]) +9 other tests fail
[350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-1/igt@sriov_basic@enable-vfs-autoprobe-on@numvfs-7.html
* igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
- shard-tglu: NOTRUN -> [FAIL][351] ([i915#12910])
[351]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-8/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
- shard-dg2-9: NOTRUN -> [SKIP][352] ([i915#9917])
[352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-9/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
* igt@sriov_basic@enable-vfs-bind-unbind-each@numvfs-random:
- shard-mtlp: NOTRUN -> [FAIL][353] ([i915#12910]) +8 other tests fail
[353]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-1/igt@sriov_basic@enable-vfs-bind-unbind-each@numvfs-random.html
* igt@tools_test@sysfs_l3_parity:
- shard-mtlp: NOTRUN -> [SKIP][354] ([i915#4818])
[354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-4/igt@tools_test@sysfs_l3_parity.html
#### Possible fixes ####
* igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0:
- shard-dg2: [INCOMPLETE][355] ([i915#13356]) -> [PASS][356]
[355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg2-7/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
[356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-2/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
* igt@gem_eio@in-flight-immediate:
- shard-mtlp: [ABORT][357] ([i915#13193]) -> [PASS][358] +3 other tests pass
[357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-mtlp-4/igt@gem_eio@in-flight-immediate.html
[358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-6/igt@gem_eio@in-flight-immediate.html
* igt@gem_pxp@verify-pxp-stale-ctx-execution:
- shard-rkl: [TIMEOUT][359] ([i915#12917] / [i915#12964]) -> [PASS][360]
[359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-rkl-1/igt@gem_pxp@verify-pxp-stale-ctx-execution.html
[360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-8/igt@gem_pxp@verify-pxp-stale-ctx-execution.html
* igt@i915_pm_rpm@debugfs-forcewake-user:
- shard-rkl: [SKIP][361] ([i915#13328]) -> [PASS][362]
[361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-rkl-1/igt@i915_pm_rpm@debugfs-forcewake-user.html
[362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-8/igt@i915_pm_rpm@debugfs-forcewake-user.html
* igt@i915_pm_rps@reset:
- shard-snb: [INCOMPLETE][363] ([i915#13729] / [i915#13821]) -> [PASS][364]
[363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-snb2/igt@i915_pm_rps@reset.html
[364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-snb4/igt@i915_pm_rps@reset.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-dg2: [FAIL][365] ([i915#5956]) -> [PASS][366]
[365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg2-8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
[366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_cursor_crc@cursor-onscreen-128x42:
- shard-rkl: [FAIL][367] ([i915#13566]) -> [PASS][368] +2 other tests pass
[367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-rkl-1/igt@kms_cursor_crc@cursor-onscreen-128x42.html
[368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-8/igt@kms_cursor_crc@cursor-onscreen-128x42.html
* igt@kms_dp_aux_dev:
- shard-dg2: [SKIP][369] ([i915#1257]) -> [PASS][370]
[369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg2-5/igt@kms_dp_aux_dev.html
[370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-11/igt@kms_dp_aux_dev.html
* igt@kms_flip@2x-flip-vs-suspend@ab-vga1-hdmi-a1:
- shard-snb: [TIMEOUT][371] ([i915#14033]) -> [PASS][372] +1 other test pass
[371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-snb6/igt@kms_flip@2x-flip-vs-suspend@ab-vga1-hdmi-a1.html
[372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-snb7/igt@kms_flip@2x-flip-vs-suspend@ab-vga1-hdmi-a1.html
* igt@kms_flip@blocking-wf_vblank@b-hdmi-a1:
- shard-tglu: [FAIL][373] ([i915#13734]) -> [PASS][374] +3 other tests pass
[373]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-tglu-9/igt@kms_flip@blocking-wf_vblank@b-hdmi-a1.html
[374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-tglu-4/igt@kms_flip@blocking-wf_vblank@b-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-rkl: [INCOMPLETE][375] ([i915#6113]) -> [PASS][376]
[375]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-rkl-3/igt@kms_flip@flip-vs-suspend-interruptible.html
[376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-7/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@plain-flip-fb-recreate:
- shard-rkl: [FAIL][377] ([i915#13734]) -> [PASS][378] +1 other test pass
[377]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-rkl-1/igt@kms_flip@plain-flip-fb-recreate.html
[378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-1/igt@kms_flip@plain-flip-fb-recreate.html
* igt@kms_flip@wf_vblank-ts-check@a-vga1:
- shard-snb: [FAIL][379] ([i915#13734]) -> [PASS][380] +1 other test pass
[379]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-snb4/igt@kms_flip@wf_vblank-ts-check@a-vga1.html
[380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-snb7/igt@kms_flip@wf_vblank-ts-check@a-vga1.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-dg2: [FAIL][381] ([i915#6880]) -> [PASS][382]
[381]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-mtlp: [INCOMPLETE][383] -> [PASS][384] +1 other test pass
[383]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-mtlp-8/igt@kms_hdr@bpc-switch-suspend.html
[384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-mtlp-3/igt@kms_hdr@bpc-switch-suspend.html
- shard-dg2: [SKIP][385] ([i915#3555] / [i915#8228]) -> [PASS][386]
[385]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg2-3/igt@kms_hdr@bpc-switch-suspend.html
[386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-11/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-dg2: [SKIP][387] ([i915#9340]) -> [PASS][388]
[387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg2-3/igt@kms_pm_lpsp@kms-lpsp.html
[388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-8/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@i2c:
- shard-dg1: [DMESG-WARN][389] ([i915#4423]) -> [PASS][390]
[389]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg1-15/igt@kms_pm_rpm@i2c.html
[390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-13/igt@kms_pm_rpm@i2c.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-dg2: [SKIP][391] ([i915#9519]) -> [PASS][392]
[391]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg2-8/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
[392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-5/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
- shard-rkl: [SKIP][393] ([i915#9519]) -> [PASS][394]
[393]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-rkl-7/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
[394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-3/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
* igt@perf@polling@0-rcs0:
- shard-rkl: [DMESG-WARN][395] ([i915#12964]) -> [PASS][396] +7 other tests pass
[395]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-rkl-7/igt@perf@polling@0-rcs0.html
[396]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-3/igt@perf@polling@0-rcs0.html
* igt@perf_pmu@busy-double-start@vecs1:
- shard-dg2: [FAIL][397] ([i915#4349]) -> [PASS][398] +4 other tests pass
[397]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg2-2/igt@perf_pmu@busy-double-start@vecs1.html
[398]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-6/igt@perf_pmu@busy-double-start@vecs1.html
#### Warnings ####
* igt@gem_eio@in-flight-suspend:
- shard-glk: [INCOMPLETE][399] ([i915#13390]) -> [INCOMPLETE][400] ([i915#13197] / [i915#13390])
[399]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-glk2/igt@gem_eio@in-flight-suspend.html
[400]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-glk6/igt@gem_eio@in-flight-suspend.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg1: [TIMEOUT][401] ([i915#5493]) -> [TIMEOUT][402] ([i915#14044] / [i915#5493]) +1 other test timeout
[401]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html
[402]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_pxp@hw-rejects-pxp-buffer:
- shard-rkl: [SKIP][403] ([i915#13717]) -> [TIMEOUT][404] ([i915#12917] / [i915#12964])
[403]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-rkl-8/igt@gem_pxp@hw-rejects-pxp-buffer.html
[404]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-6/igt@gem_pxp@hw-rejects-pxp-buffer.html
* igt@i915_suspend@forcewake:
- shard-rkl: [INCOMPLETE][405] ([i915#4817]) -> [INCOMPLETE][406] ([i915#12964] / [i915#4817])
[405]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-rkl-4/igt@i915_suspend@forcewake.html
[406]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-4/igt@i915_suspend@forcewake.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-4:
- shard-dg1: [SKIP][407] ([i915#4423] / [i915#6095]) -> [SKIP][408] ([i915#6095]) +1 other test skip
[407]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg1-17/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-4.html
[408]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-19/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-4.html
* igt@kms_ccs@random-ccs-data-y-tiled-ccs:
- shard-dg1: [SKIP][409] ([i915#6095]) -> [SKIP][410] ([i915#4423] / [i915#6095]) +1 other test skip
[409]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg1-15/igt@kms_ccs@random-ccs-data-y-tiled-ccs.html
[410]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-13/igt@kms_ccs@random-ccs-data-y-tiled-ccs.html
* igt@kms_chamelium_frames@dp-frame-dump:
- shard-dg1: [SKIP][411] ([i915#11151] / [i915#7828]) -> [SKIP][412] ([i915#11151] / [i915#4423] / [i915#7828])
[411]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg1-18/igt@kms_chamelium_frames@dp-frame-dump.html
[412]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-18/igt@kms_chamelium_frames@dp-frame-dump.html
* igt@kms_content_protection@atomic-dpms:
- shard-dg2: [FAIL][413] ([i915#7173]) -> [SKIP][414] ([i915#7118] / [i915#9424])
[413]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg2-11/igt@kms_content_protection@atomic-dpms.html
[414]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-3/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@mei-interface:
- shard-dg1: [SKIP][415] ([i915#9424]) -> [SKIP][416] ([i915#9433])
[415]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg1-18/igt@kms_content_protection@mei-interface.html
[416]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-13/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@srm:
- shard-dg2: [SKIP][417] ([i915#7118]) -> [FAIL][418] ([i915#7173])
[417]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg2-5/igt@kms_content_protection@srm.html
[418]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-11/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent:
- shard-dg2: [FAIL][419] ([i915#1339] / [i915#7173]) -> [SKIP][420] ([i915#7118] / [i915#9424])
[419]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg2-11/igt@kms_content_protection@uevent.html
[420]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg2-2/igt@kms_content_protection@uevent.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-dg1: [SKIP][421] ([i915#4103] / [i915#4213]) -> [SKIP][422] ([i915#4103] / [i915#4213] / [i915#4423])
[421]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg1-15/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
[422]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-13/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-glk: [INCOMPLETE][423] ([i915#12745] / [i915#4839]) -> [INCOMPLETE][424] ([i915#12314] / [i915#12745] / [i915#4839])
[423]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-glk4/igt@kms_flip@flip-vs-suspend-interruptible.html
[424]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-glk8/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a1:
- shard-glk: [INCOMPLETE][425] ([i915#12745]) -> [INCOMPLETE][426] ([i915#12314] / [i915#12745])
[425]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-glk4/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a1.html
[426]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-glk8/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
- shard-dg1: [SKIP][427] ([i915#2672] / [i915#3555] / [i915#4423]) -> [SKIP][428] ([i915#2672] / [i915#3555])
[427]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg1-12/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
[428]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-17/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode:
- shard-dg1: [SKIP][429] ([i915#2587] / [i915#2672] / [i915#4423]) -> [SKIP][430] ([i915#2587] / [i915#2672])
[429]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg1-12/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html
[430]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-17/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt:
- shard-dg1: [SKIP][431] ([i915#8708]) -> [SKIP][432] ([i915#4423] / [i915#8708]) +1 other test skip
[431]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt.html
[432]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-15/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite:
- shard-dg1: [SKIP][433] ([i915#3458]) -> [SKIP][434] ([i915#3458] / [i915#4423])
[433]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg1-14/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html
[434]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-12/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt:
- shard-dg1: [SKIP][435] -> [SKIP][436] ([i915#4423]) +2 other tests skip
[435]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg1-15/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt.html
[436]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-13/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt.html
* igt@kms_pm_dc@dc6-dpms:
- shard-rkl: [SKIP][437] ([i915#3361]) -> [FAIL][438] ([i915#9295])
[437]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-rkl-8/igt@kms_pm_dc@dc6-dpms.html
[438]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-6/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-rkl: [SKIP][439] ([i915#3828]) -> [SKIP][440] ([i915#9340])
[439]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-rkl-4/igt@kms_pm_lpsp@kms-lpsp.html
[440]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-rkl-5/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf:
- shard-dg1: [SKIP][441] ([i915#11520]) -> [SKIP][442] ([i915#11520] / [i915#4423])
[441]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg1-15/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf.html
[442]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-13/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr@psr-sprite-render:
- shard-dg1: [SKIP][443] ([i915#1072] / [i915#9732]) -> [SKIP][444] ([i915#1072] / [i915#4423] / [i915#9732])
[443]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg1-15/igt@kms_psr@psr-sprite-render.html
[444]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-13/igt@kms_psr@psr-sprite-render.html
* igt@kms_vrr@flip-suspend:
- shard-dg1: [SKIP][445] ([i915#3555] / [i915#4423]) -> [SKIP][446] ([i915#3555])
[445]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16377/shard-dg1-19/igt@kms_vrr@flip-suspend.html
[446]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/shard-dg1-14/igt@kms_vrr@flip-suspend.html
[i915#10030]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10030
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10333]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10333
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10647]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10647
[i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
[i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
[i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#12169]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12169
[i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
[i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
[i915#12314]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12314
[i915#12316]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12316
[i915#12339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12339
[i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
[i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
[i915#12392]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12392
[i915#12394]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12394
[i915#12454]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12454
[i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
[i915#12712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12712
[i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
[i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
[i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
[i915#12797]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12797
[i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
[i915#12910]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12910
[i915#12912]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12912
[i915#12917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12917
[i915#12941]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12941
[i915#12964]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12964
[i915#12967]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12967
[i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
[i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
[i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
[i915#13193]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13193
[i915#13197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13197
[i915#13328]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13328
[i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
[i915#1339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1339
[i915#13390]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13390
[i915#13427]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13427
[i915#13476]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13476
[i915#13520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13520
[i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
[i915#13691]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13691
[i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
[i915#13717]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13717
[i915#13729]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13729
[i915#13734]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13734
[i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
[i915#13781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13781
[i915#13783]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13783
[i915#13798]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13798
[i915#13821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13821
[i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
[i915#14033]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14033
[i915#14044]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14044
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
[i915#3778]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3778
[i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
[i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#3955]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3955
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4348]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4348
[i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
[i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
[i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
[i915#4818]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4818
[i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4854
[i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4881
[i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
[i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
[i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
[i915#5566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5566
[i915#5723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5723
[i915#5882]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5882
[i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6113]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6113
[i915#6187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6187
[i915#6245]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6245
[i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
[i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
[i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
[i915#8213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
[i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
[i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
[i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
[i915#8808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8808
[i915#8813]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8813
[i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
[i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
[i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
[i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
[i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
[i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
[i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
[i915#9878]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9878
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_16377 -> Patchwork_147193v2
CI-20190529: 20190529
CI_DRM_16377: a33da369e8cde6c7208381a592866cd61f1ce188 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8309: fb77fb2d8d58a2539c9d67d00e1747351eec0bea @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_147193v2: a33da369e8cde6c7208381a592866cd61f1ce188 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147193v2/index.html
[-- Attachment #2: Type: text/html, Size: 156052 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display
2025-04-08 13:38 [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display Jani Nikula
` (10 preceding siblings ...)
2025-04-08 16:44 ` ✗ i915.CI.Full: failure " Patchwork
@ 2025-04-09 9:17 ` Kandpal, Suraj
2025-04-09 14:55 ` Jani Nikula
11 siblings, 1 reply; 14+ messages in thread
From: Kandpal, Suraj @ 2025-04-09 9:17 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Nikula, Jani
> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Tuesday, April 8, 2025 7:09 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display
>
> v2 of [1], basically just a rebase.
>
> BR,
> Jani.
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
For the whole series
>
>
> [1] https://lore.kernel.org/r/cover.1743671373.git.jani.nikula@intel.com
>
> Jani Nikula (7):
> drm/i915/wm: convert intel_wm.h external interfaces to struct
> intel_display
> drm/i915/wm: convert intel_wm.c internally to struct intel_display
> drm/i915/wm: convert skl_watermark.h external interfaces to struct
> intel_display
> drm/i915/wm: convert skl_watermarks.c internally to struct
> intel_display
> drm/i915/wm: convert i9xx_wm.h external interfaces to struct
> intel_display
> drm/i915/wm: convert i9xx_wm.c to intel_de_*() register interface
> drm/i915/wm: convert i9xx_wm.c internally to struct intel_display
>
> drivers/gpu/drm/i915/display/i9xx_wm.c | 1222 ++++++++---------
> drivers/gpu/drm/i915/display/i9xx_wm.h | 18 +-
> drivers/gpu/drm/i915/display/intel_bw.c | 24 +-
> drivers/gpu/drm/i915/display/intel_cdclk.c | 4 +-
> drivers/gpu/drm/i915/display/intel_display.c | 22 +-
> .../gpu/drm/i915/display/intel_display_core.h | 6 +-
> .../drm/i915/display/intel_display_debugfs.c | 3 +-
> .../drm/i915/display/intel_display_driver.c | 12 +-
> drivers/gpu/drm/i915/display/intel_dsb.c | 4 +-
> .../drm/i915/display/intel_modeset_setup.c | 11 +-
> drivers/gpu/drm/i915/display/intel_wm.c | 171 +--
> drivers/gpu/drm/i915/display/intel_wm.h | 14 +-
> drivers/gpu/drm/i915/display/skl_watermark.c | 616 ++++-----
> drivers/gpu/drm/i915/display/skl_watermark.h | 23 +-
> drivers/gpu/drm/i915/i915_driver.c | 2 +-
> drivers/gpu/drm/xe/display/xe_display.c | 2 +-
> 16 files changed, 1057 insertions(+), 1097 deletions(-)
>
> --
> 2.39.5
^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display
2025-04-09 9:17 ` [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display Kandpal, Suraj
@ 2025-04-09 14:55 ` Jani Nikula
0 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2025-04-09 14:55 UTC (permalink / raw)
To: Kandpal, Suraj, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
On Wed, 09 Apr 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> -----Original Message-----
>> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Jani
>> Nikula
>> Sent: Tuesday, April 8, 2025 7:09 PM
>> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>
>> Subject: [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display
>>
>> v2 of [1], basically just a rebase.
>>
>> BR,
>> Jani.
>
> LGTM,
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> For the whole series
Thanks, pushed to din.
BR,
Jani.
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2025-04-09 14:55 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-04-08 13:38 [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display Jani Nikula
2025-04-08 13:38 ` [PATCH v2 1/7] drm/i915/wm: convert intel_wm.h external interfaces " Jani Nikula
2025-04-08 13:38 ` [PATCH v2 2/7] drm/i915/wm: convert intel_wm.c internally " Jani Nikula
2025-04-08 13:38 ` [PATCH v2 3/7] drm/i915/wm: convert skl_watermark.h external interfaces " Jani Nikula
2025-04-08 13:38 ` [PATCH v2 4/7] drm/i915/wm: convert skl_watermarks.c internally " Jani Nikula
2025-04-08 13:38 ` [PATCH v2 5/7] drm/i915/wm: convert i9xx_wm.h external interfaces " Jani Nikula
2025-04-08 13:38 ` [PATCH v2 6/7] drm/i915/wm: convert i9xx_wm.c to intel_de_*() register interface Jani Nikula
2025-04-08 13:38 ` [PATCH v2 7/7] drm/i915/wm: convert i9xx_wm.c internally to struct intel_display Jani Nikula
2025-04-08 14:03 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/wm: convert to struct intel_display (rev2) Patchwork
2025-04-08 14:03 ` ✗ Fi.CI.SPARSE: " Patchwork
2025-04-08 14:22 ` ✓ i915.CI.BAT: success " Patchwork
2025-04-08 16:44 ` ✗ i915.CI.Full: failure " Patchwork
2025-04-09 9:17 ` [PATCH v2 0/7] drm/i915/wm: convert to struct intel_display Kandpal, Suraj
2025-04-09 14:55 ` Jani Nikula
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