* [PATCH v2 1/6] drm/i915/irq: deduplicate dg1_de_irq_postinstall() and gen11_de_irq_postinstall()
2026-05-04 22:26 [PATCH v2 0/6] drm/i915: add display irq hooks Jani Nikula
@ 2026-05-04 22:26 ` Jani Nikula
2026-05-04 22:26 ` [PATCH v2 2/6] drm/i915/irq: constify pipe stats parameters Jani Nikula
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2026-05-04 22:26 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
dg1_de_irq_postinstall() and gen11_de_irq_postinstall() are exactly the
same. Remove dg1_de_irq_postinstall() and call
gen11_de_irq_postinstall() instead.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 9 ---------
drivers/gpu/drm/i915/display/intel_display_irq.h | 1 -
drivers/gpu/drm/i915/i915_irq.c | 2 +-
3 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index b5bfdebc66ca..bf4b5e7b6011 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -2449,15 +2449,6 @@ void gen11_de_irq_postinstall(struct intel_display *display)
intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
}
-void dg1_de_irq_postinstall(struct intel_display *display)
-{
- if (!HAS_DISPLAY(display))
- return;
-
- gen8_de_irq_postinstall(display);
- intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
-}
-
struct intel_display_irq_funcs {
void (*reset)(struct intel_display *display);
};
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index b25d180254d7..e2b1674fae06 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -71,7 +71,6 @@ void vlv_display_irq_postinstall(struct intel_display *display);
void ilk_de_irq_postinstall(struct intel_display *display);
void gen8_de_irq_postinstall(struct intel_display *display);
void gen11_de_irq_postinstall(struct intel_display *display);
-void dg1_de_irq_postinstall(struct intel_display *display);
u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d4d8dd0a4174..ef9eadf38a53 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -778,7 +778,7 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
- dg1_de_irq_postinstall(display);
+ gen11_de_irq_postinstall(display);
dg1_master_intr_enable(intel_uncore_regs(uncore));
intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
--
2.47.3
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 2/6] drm/i915/irq: constify pipe stats parameters
2026-05-04 22:26 [PATCH v2 0/6] drm/i915: add display irq hooks Jani Nikula
2026-05-04 22:26 ` [PATCH v2 1/6] drm/i915/irq: deduplicate dg1_de_irq_postinstall() and gen11_de_irq_postinstall() Jani Nikula
@ 2026-05-04 22:26 ` Jani Nikula
2026-05-04 22:26 ` [PATCH v2 3/6] drm/i915/irq: add display irq funcs, start with intel_display_irq_reset() Jani Nikula
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2026-05-04 22:26 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
The pipe stat irq handling doesn't need to modify the pipe stats
arrays. Make them const.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 6 +++---
drivers/gpu/drm/i915/display/intel_display_irq.h | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index bf4b5e7b6011..d30b063714b0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -597,7 +597,7 @@ void i9xx_pipestat_irq_ack(struct intel_display *display,
}
void i915_pipestat_irq_handler(struct intel_display *display,
- u32 iir, u32 pipe_stats[I915_MAX_PIPES])
+ u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
{
bool blc_event = false;
enum pipe pipe;
@@ -621,7 +621,7 @@ void i915_pipestat_irq_handler(struct intel_display *display,
}
void i965_pipestat_irq_handler(struct intel_display *display,
- u32 iir, u32 pipe_stats[I915_MAX_PIPES])
+ u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
{
bool blc_event = false;
enum pipe pipe;
@@ -648,7 +648,7 @@ void i965_pipestat_irq_handler(struct intel_display *display,
}
void valleyview_pipestat_irq_handler(struct intel_display *display,
- u32 pipe_stats[I915_MAX_PIPES])
+ const u32 pipe_stats[I915_MAX_PIPES])
{
enum pipe pipe;
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index e2b1674fae06..d25b9ea4272b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -78,9 +78,9 @@ void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 st
void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
-void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
-void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
-void valleyview_pipestat_irq_handler(struct intel_display *display, u32 pipe_stats[I915_MAX_PIPES]);
+void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
+void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
+void valleyview_pipestat_irq_handler(struct intel_display *display, const u32 pipe_stats[I915_MAX_PIPES]);
void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt);
void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);
--
2.47.3
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 3/6] drm/i915/irq: add display irq funcs, start with intel_display_irq_reset()
2026-05-04 22:26 [PATCH v2 0/6] drm/i915: add display irq hooks Jani Nikula
2026-05-04 22:26 ` [PATCH v2 1/6] drm/i915/irq: deduplicate dg1_de_irq_postinstall() and gen11_de_irq_postinstall() Jani Nikula
2026-05-04 22:26 ` [PATCH v2 2/6] drm/i915/irq: constify pipe stats parameters Jani Nikula
@ 2026-05-04 22:26 ` Jani Nikula
2026-05-04 22:26 ` [PATCH v2 4/6] drm/i915/irq: add intel_display_irq_postinstall() to irq funcs Jani Nikula
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2026-05-04 22:26 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Introduce display irq hooks with struct intel_display_irq_funcs, and add
the ->reset hook as the first thing. Call the reset hooks from i915 and
xe core via intel_display_irq_reset().
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_display_core.h | 3 ++
.../gpu/drm/i915/display/intel_display_irq.c | 52 +++++++++++++++++--
.../gpu/drm/i915/display/intel_display_irq.h | 6 +--
drivers/gpu/drm/i915/i915_irq.c | 16 +++---
drivers/gpu/drm/xe/display/xe_display.c | 2 +-
5 files changed, 60 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 796517e7bc6c..7bc2ff11b658 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -475,6 +475,9 @@ struct intel_display {
} ips;
struct {
+ /* internal display irq functions */
+ const struct intel_display_irq_funcs *funcs;
+
/* protects the irq masks */
spinlock_t lock;
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index d30b063714b0..7505652257d8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1947,7 +1947,7 @@ static void _vlv_display_irq_reset(struct intel_display *display)
display->irq.vlv_imr_mask = ~0u;
}
-void vlv_display_irq_reset(struct intel_display *display)
+static void vlv_display_irq_reset(struct intel_display *display)
{
spin_lock_irq(&display->irq.lock);
if (display->irq.vlv_display_irqs_enabled)
@@ -1955,7 +1955,7 @@ void vlv_display_irq_reset(struct intel_display *display)
spin_unlock_irq(&display->irq.lock);
}
-void i9xx_display_irq_reset(struct intel_display *display)
+static void i9xx_display_irq_reset(struct intel_display *display)
{
if (HAS_HOTPLUG(display)) {
i915_hotplug_interrupt_update(display, 0xffffffff, 0);
@@ -2076,7 +2076,7 @@ static void ibx_display_irq_reset(struct intel_display *display)
intel_de_write(display, SERR_INT, 0xffffffff);
}
-void ilk_display_irq_reset(struct intel_display *display)
+static void ilk_display_irq_reset(struct intel_display *display)
{
irq_reset(display, DE_IRQ_REGS);
display->irq.ilk_de_imr_mask = ~0u;
@@ -2092,7 +2092,7 @@ void ilk_display_irq_reset(struct intel_display *display)
ibx_display_irq_reset(display);
}
-void gen8_display_irq_reset(struct intel_display *display)
+static void gen8_display_irq_reset(struct intel_display *display)
{
enum pipe pipe;
@@ -2114,7 +2114,7 @@ void gen8_display_irq_reset(struct intel_display *display)
ibx_display_irq_reset(display);
}
-void gen11_display_irq_reset(struct intel_display *display)
+static void gen11_display_irq_reset(struct intel_display *display)
{
enum pipe pipe;
u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
@@ -2453,6 +2453,35 @@ struct intel_display_irq_funcs {
void (*reset)(struct intel_display *display);
};
+struct intel_display_irq_funcs gen11_display_irq_funcs = {
+ .reset = gen11_display_irq_reset,
+};
+
+struct intel_display_irq_funcs gen8_display_irq_funcs = {
+ .reset = gen8_display_irq_reset,
+};
+
+struct intel_display_irq_funcs vlv_display_irq_funcs = {
+ .reset = vlv_display_irq_reset,
+};
+
+struct intel_display_irq_funcs ilk_display_irq_funcs = {
+ .reset = ilk_display_irq_reset,
+};
+
+struct intel_display_irq_funcs i965_display_irq_funcs = {
+ .reset = i9xx_display_irq_reset,
+};
+
+struct intel_display_irq_funcs i915_display_irq_funcs = {
+ .reset = i9xx_display_irq_reset,
+};
+
+void intel_display_irq_reset(struct intel_display *display)
+{
+ display->irq.funcs->reset(display);
+}
+
void intel_display_irq_init(struct intel_display *display)
{
spin_lock_init(&display->irq.lock);
@@ -2463,6 +2492,19 @@ void intel_display_irq_init(struct intel_display *display)
INIT_WORK(&display->irq.vblank_notify_work,
intel_display_vblank_notify_work);
+
+ if (DISPLAY_VER(display) >= 11)
+ display->irq.funcs = &gen11_display_irq_funcs;
+ else if (display->platform.cherryview || display->platform.valleyview)
+ display->irq.funcs = &vlv_display_irq_funcs;
+ else if (DISPLAY_VER(display) >= 8)
+ display->irq.funcs = &gen8_display_irq_funcs;
+ else if (DISPLAY_VER(display) >= 5)
+ display->irq.funcs = &ilk_display_irq_funcs;
+ else if (DISPLAY_VER(display) == 4)
+ display->irq.funcs = &i965_display_irq_funcs;
+ else
+ display->irq.funcs = &i915_display_irq_funcs;
}
struct intel_display_irq_snapshot {
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index d25b9ea4272b..21b2145656cd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -58,11 +58,7 @@ void gen11_display_irq_handler(struct intel_display *display);
u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
-void i9xx_display_irq_reset(struct intel_display *display);
-void ilk_display_irq_reset(struct intel_display *display);
-void vlv_display_irq_reset(struct intel_display *display);
-void gen8_display_irq_reset(struct intel_display *display);
-void gen11_display_irq_reset(struct intel_display *display);
+void intel_display_irq_reset(struct intel_display *display);
u32 i9xx_display_irq_enable_mask(struct intel_display *display);
void i915_display_irq_postinstall(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ef9eadf38a53..c4f56a869910 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -640,7 +640,7 @@ static void ilk_irq_reset(struct drm_i915_private *dev_priv)
struct intel_display *display = dev_priv->display;
/* The master interrupt enable is in DEIER, reset display irq first */
- ilk_display_irq_reset(display);
+ intel_display_irq_reset(display);
gen5_gt_irq_reset(to_gt(dev_priv));
}
@@ -653,7 +653,7 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
gen5_gt_irq_reset(to_gt(dev_priv));
- vlv_display_irq_reset(display);
+ intel_display_irq_reset(display);
}
static void gen8_irq_reset(struct drm_i915_private *dev_priv)
@@ -664,7 +664,7 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
gen8_master_intr_disable(intel_uncore_regs(uncore));
gen8_gt_irq_reset(to_gt(dev_priv));
- gen8_display_irq_reset(display);
+ intel_display_irq_reset(display);
gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
}
@@ -677,7 +677,7 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
gen11_master_intr_disable(intel_uncore_regs(&dev_priv->uncore));
gen11_gt_irq_reset(gt);
- gen11_display_irq_reset(display);
+ intel_display_irq_reset(display);
gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
@@ -695,7 +695,7 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv)
for_each_gt(gt, dev_priv, i)
gen11_gt_irq_reset(gt);
- gen11_display_irq_reset(display);
+ intel_display_irq_reset(display);
gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
@@ -715,7 +715,7 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
- vlv_display_irq_reset(display);
+ intel_display_irq_reset(display);
}
static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -864,7 +864,7 @@ static void i915_irq_reset(struct drm_i915_private *dev_priv)
struct intel_display *display = dev_priv->display;
struct intel_uncore *uncore = &dev_priv->uncore;
- i9xx_display_irq_reset(display);
+ intel_display_irq_reset(display);
gen2_error_reset(uncore, GEN2_ERROR_REGS);
gen2_irq_reset(uncore, GEN2_IRQ_REGS);
@@ -951,7 +951,7 @@ static void i965_irq_reset(struct drm_i915_private *dev_priv)
struct intel_display *display = dev_priv->display;
struct intel_uncore *uncore = &dev_priv->uncore;
- i9xx_display_irq_reset(display);
+ intel_display_irq_reset(display);
gen2_error_reset(uncore, GEN2_ERROR_REGS);
gen2_irq_reset(uncore, GEN2_IRQ_REGS);
diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index 0747044f7c2a..d6a4546fbe94 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -235,7 +235,7 @@ void xe_display_irq_reset(struct xe_device *xe)
if (!xe->info.probe_display)
return;
- gen11_display_irq_reset(display);
+ intel_display_irq_reset(display);
}
void xe_display_irq_postinstall(struct xe_device *xe)
--
2.47.3
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 4/6] drm/i915/irq: add intel_display_irq_postinstall() to irq funcs
2026-05-04 22:26 [PATCH v2 0/6] drm/i915: add display irq hooks Jani Nikula
` (2 preceding siblings ...)
2026-05-04 22:26 ` [PATCH v2 3/6] drm/i915/irq: add display irq funcs, start with intel_display_irq_reset() Jani Nikula
@ 2026-05-04 22:26 ` Jani Nikula
2026-05-04 22:26 ` [PATCH v2 5/6] drm/i915/irq: add intel_display_irq_ack() " Jani Nikula
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2026-05-04 22:26 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Call the platform specific display irq postinstall hooks via
intel_display_irq_postinstall().
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_display_irq.c | 24 ++++++++++++++-----
.../gpu/drm/i915/display/intel_display_irq.h | 7 +-----
drivers/gpu/drm/i915/i915_irq.c | 16 ++++++-------
drivers/gpu/drm/xe/display/xe_display.c | 2 +-
4 files changed, 28 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 7505652257d8..6ba094a0df66 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1981,7 +1981,7 @@ u32 i9xx_display_irq_enable_mask(struct intel_display *display)
return enable_mask;
}
-void i915_display_irq_postinstall(struct intel_display *display)
+static void i915_display_irq_postinstall(struct intel_display *display)
{
/*
* Interrupt setup is already guaranteed to be single-threaded, this is
@@ -1995,7 +1995,7 @@ void i915_display_irq_postinstall(struct intel_display *display)
i915_enable_asle_pipestat(display);
}
-void i965_display_irq_postinstall(struct intel_display *display)
+static void i965_display_irq_postinstall(struct intel_display *display)
{
/*
* Interrupt setup is already guaranteed to be single-threaded, this is
@@ -2057,7 +2057,7 @@ static void _vlv_display_irq_postinstall(struct intel_display *display)
irq_init(display, VLV_IRQ_REGS, display->irq.vlv_imr_mask, enable_mask);
}
-void vlv_display_irq_postinstall(struct intel_display *display)
+static void vlv_display_irq_postinstall(struct intel_display *display)
{
spin_lock_irq(&display->irq.lock);
if (display->irq.vlv_display_irqs_enabled)
@@ -2268,7 +2268,7 @@ void valleyview_disable_display_irqs(struct intel_display *display)
spin_unlock_irq(&display->irq.lock);
}
-void ilk_de_irq_postinstall(struct intel_display *display)
+static void ilk_de_irq_postinstall(struct intel_display *display)
{
u32 display_mask, extra_mask;
@@ -2312,7 +2312,7 @@ void ilk_de_irq_postinstall(struct intel_display *display)
static void mtp_irq_postinstall(struct intel_display *display);
static void icp_irq_postinstall(struct intel_display *display);
-void gen8_de_irq_postinstall(struct intel_display *display)
+static void gen8_de_irq_postinstall(struct intel_display *display)
{
u32 de_pipe_masked = gen8_de_pipe_fault_mask(display) |
GEN8_PIPE_CDCLK_CRC_DONE;
@@ -2439,7 +2439,7 @@ static void icp_irq_postinstall(struct intel_display *display)
irq_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);
}
-void gen11_de_irq_postinstall(struct intel_display *display)
+static void gen11_de_irq_postinstall(struct intel_display *display)
{
if (!HAS_DISPLAY(display))
return;
@@ -2451,30 +2451,37 @@ void gen11_de_irq_postinstall(struct intel_display *display)
struct intel_display_irq_funcs {
void (*reset)(struct intel_display *display);
+ void (*postinstall)(struct intel_display *display);
};
struct intel_display_irq_funcs gen11_display_irq_funcs = {
.reset = gen11_display_irq_reset,
+ .postinstall = gen11_de_irq_postinstall,
};
struct intel_display_irq_funcs gen8_display_irq_funcs = {
.reset = gen8_display_irq_reset,
+ .postinstall = gen8_de_irq_postinstall,
};
struct intel_display_irq_funcs vlv_display_irq_funcs = {
.reset = vlv_display_irq_reset,
+ .postinstall = vlv_display_irq_postinstall,
};
struct intel_display_irq_funcs ilk_display_irq_funcs = {
.reset = ilk_display_irq_reset,
+ .postinstall = ilk_de_irq_postinstall,
};
struct intel_display_irq_funcs i965_display_irq_funcs = {
.reset = i9xx_display_irq_reset,
+ .postinstall = i965_display_irq_postinstall,
};
struct intel_display_irq_funcs i915_display_irq_funcs = {
.reset = i9xx_display_irq_reset,
+ .postinstall = i915_display_irq_postinstall,
};
void intel_display_irq_reset(struct intel_display *display)
@@ -2482,6 +2489,11 @@ void intel_display_irq_reset(struct intel_display *display)
display->irq.funcs->reset(display);
}
+void intel_display_irq_postinstall(struct intel_display *display)
+{
+ display->irq.funcs->postinstall(display);
+}
+
void intel_display_irq_init(struct intel_display *display)
{
spin_lock_init(&display->irq.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index 21b2145656cd..fd9873ce9755 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -59,14 +59,9 @@ u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
void intel_display_irq_reset(struct intel_display *display);
+void intel_display_irq_postinstall(struct intel_display *display);
u32 i9xx_display_irq_enable_mask(struct intel_display *display);
-void i915_display_irq_postinstall(struct intel_display *display);
-void i965_display_irq_postinstall(struct intel_display *display);
-void vlv_display_irq_postinstall(struct intel_display *display);
-void ilk_de_irq_postinstall(struct intel_display *display);
-void gen8_de_irq_postinstall(struct intel_display *display);
-void gen11_de_irq_postinstall(struct intel_display *display);
u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c4f56a869910..c21b289b8007 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -724,7 +724,7 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
gen5_gt_irq_postinstall(to_gt(dev_priv));
- ilk_de_irq_postinstall(display);
+ intel_display_irq_postinstall(display);
}
static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -733,7 +733,7 @@ static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
gen5_gt_irq_postinstall(to_gt(dev_priv));
- vlv_display_irq_postinstall(display);
+ intel_display_irq_postinstall(display);
intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
@@ -744,7 +744,7 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
struct intel_display *display = dev_priv->display;
gen8_gt_irq_postinstall(to_gt(dev_priv));
- gen8_de_irq_postinstall(display);
+ intel_display_irq_postinstall(display);
gen8_master_intr_enable(intel_uncore_regs(&dev_priv->uncore));
}
@@ -757,7 +757,7 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
u32 gu_misc_masked = GEN11_GU_MISC_GSE;
gen11_gt_irq_postinstall(gt);
- gen11_de_irq_postinstall(display);
+ intel_display_irq_postinstall(display);
gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
@@ -778,7 +778,7 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
- gen11_de_irq_postinstall(display);
+ intel_display_irq_postinstall(display);
dg1_master_intr_enable(intel_uncore_regs(uncore));
intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
@@ -790,7 +790,7 @@ static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
gen8_gt_irq_postinstall(to_gt(dev_priv));
- vlv_display_irq_postinstall(display);
+ intel_display_irq_postinstall(display);
intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
@@ -888,7 +888,7 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask);
- i915_display_irq_postinstall(display);
+ intel_display_irq_postinstall(display);
}
static irqreturn_t i915_irq_handler(int irq, void *arg)
@@ -997,7 +997,7 @@ static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask);
- i965_display_irq_postinstall(display);
+ intel_display_irq_postinstall(display);
}
static irqreturn_t i965_irq_handler(int irq, void *arg)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index d6a4546fbe94..736a5e6938d6 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -245,7 +245,7 @@ void xe_display_irq_postinstall(struct xe_device *xe)
if (!xe->info.probe_display)
return;
- gen11_de_irq_postinstall(display);
+ intel_display_irq_postinstall(display);
}
static bool suspend_to_idle(void)
--
2.47.3
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 5/6] drm/i915/irq: add intel_display_irq_ack() to irq funcs
2026-05-04 22:26 [PATCH v2 0/6] drm/i915: add display irq hooks Jani Nikula
` (3 preceding siblings ...)
2026-05-04 22:26 ` [PATCH v2 4/6] drm/i915/irq: add intel_display_irq_postinstall() to irq funcs Jani Nikula
@ 2026-05-04 22:26 ` Jani Nikula
2026-05-04 22:26 ` [PATCH v2 6/6] drm/i915/irq: add intel_display_irq_handler() " Jani Nikula
2026-05-04 23:26 ` ✗ i915.CI.BAT: failure for drm/i915: add display irq hooks Patchwork
6 siblings, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2026-05-04 22:26 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Some platforms have a separate step for acking display irqs. Call the
platform specific display irq ack hooks, if any, via
intel_display_irq_ack().
Introduce struct intel_display_irq_state to group together all the data
the ack hooks need. In the follow-up, this state will be passed on to a
shared handler function.
v2: Include LPE audio in the ack part
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_display_irq.c | 56 ++++++-
.../gpu/drm/i915/display/intel_display_irq.h | 12 +-
drivers/gpu/drm/i915/i915_irq.c | 144 ++++++------------
3 files changed, 111 insertions(+), 101 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 6ba094a0df66..a2e05945416d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -23,6 +23,7 @@
#include "intel_fifo_underrun.h"
#include "intel_gmbus.h"
#include "intel_hotplug_irq.h"
+#include "intel_lpe_audio.h"
#include "intel_parent.h"
#include "intel_pipe_crc_regs.h"
#include "intel_plane.h"
@@ -529,8 +530,8 @@ static void i9xx_pipestat_irq_reset(struct intel_display *display)
}
}
-void i9xx_pipestat_irq_ack(struct intel_display *display,
- u32 iir, u32 pipe_stats[I915_MAX_PIPES])
+static void i9xx_pipestat_irq_ack(struct intel_display *display,
+ u32 iir, u32 pipe_stats[I915_MAX_PIPES])
{
enum pipe pipe;
@@ -1898,8 +1899,8 @@ static void vlv_page_table_error_irq_handler(struct intel_display *display, u32
}
}
-void vlv_display_error_irq_ack(struct intel_display *display,
- u32 *eir, u32 *dpinvgtt)
+static void vlv_display_error_irq_ack(struct intel_display *display,
+ u32 *eir, u32 *dpinvgtt)
{
u32 emr;
@@ -2010,6 +2011,16 @@ static void i965_display_irq_postinstall(struct intel_display *display)
i915_enable_asle_pipestat(display);
}
+static void i9xx_display_irq_ack(struct intel_display *display,
+ struct intel_display_irq_state *state)
+{
+ if (state->iir & I915_DISPLAY_PORT_INTERRUPT)
+ state->hotplug_status = i9xx_hpd_irq_ack(display);
+
+ /* Call regardless, as some status bits might not be signalled in IIR */
+ i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
+}
+
static u32 vlv_error_mask(void)
{
/* TODO enable other errors too? */
@@ -2065,6 +2076,32 @@ static void vlv_display_irq_postinstall(struct intel_display *display)
spin_unlock_irq(&display->irq.lock);
}
+static u32 vlv_lpe_irq_mask(struct intel_display *display)
+{
+ if (display->platform.cherryview)
+ return I915_LPE_PIPE_A_INTERRUPT | I915_LPE_PIPE_B_INTERRUPT |
+ I915_LPE_PIPE_C_INTERRUPT;
+ else
+ return I915_LPE_PIPE_A_INTERRUPT | I915_LPE_PIPE_B_INTERRUPT;
+}
+
+static void vlv_display_irq_ack(struct intel_display *display,
+ struct intel_display_irq_state *state)
+{
+ if (state->iir & I915_DISPLAY_PORT_INTERRUPT)
+ state->hotplug_status = i9xx_hpd_irq_ack(display);
+
+ if (state->iir & I915_MASTER_ERROR_INTERRUPT)
+ vlv_display_error_irq_ack(display, &state->eir, &state->dpinvgtt);
+
+ /* Call regardless, as some status bits might not be signalled in IIR */
+ i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
+
+ /* The handler acks the irq, so need to call the handler here */
+ if (state->iir & vlv_lpe_irq_mask(display))
+ intel_lpe_audio_irq_handler(display);
+}
+
static void ibx_display_irq_reset(struct intel_display *display)
{
if (HAS_PCH_NOP(display))
@@ -2452,6 +2489,7 @@ static void gen11_de_irq_postinstall(struct intel_display *display)
struct intel_display_irq_funcs {
void (*reset)(struct intel_display *display);
void (*postinstall)(struct intel_display *display);
+ void (*ack)(struct intel_display *display, struct intel_display_irq_state *state);
};
struct intel_display_irq_funcs gen11_display_irq_funcs = {
@@ -2467,6 +2505,7 @@ struct intel_display_irq_funcs gen8_display_irq_funcs = {
struct intel_display_irq_funcs vlv_display_irq_funcs = {
.reset = vlv_display_irq_reset,
.postinstall = vlv_display_irq_postinstall,
+ .ack = vlv_display_irq_ack,
};
struct intel_display_irq_funcs ilk_display_irq_funcs = {
@@ -2477,11 +2516,13 @@ struct intel_display_irq_funcs ilk_display_irq_funcs = {
struct intel_display_irq_funcs i965_display_irq_funcs = {
.reset = i9xx_display_irq_reset,
.postinstall = i965_display_irq_postinstall,
+ .ack = i9xx_display_irq_ack,
};
struct intel_display_irq_funcs i915_display_irq_funcs = {
.reset = i9xx_display_irq_reset,
.postinstall = i915_display_irq_postinstall,
+ .ack = i9xx_display_irq_ack,
};
void intel_display_irq_reset(struct intel_display *display)
@@ -2494,6 +2535,13 @@ void intel_display_irq_postinstall(struct intel_display *display)
display->irq.funcs->postinstall(display);
}
+void intel_display_irq_ack(struct intel_display *display,
+ struct intel_display_irq_state *state)
+{
+ if (display->irq.funcs->ack)
+ display->irq.funcs->ack(display, state);
+}
+
void intel_display_irq_init(struct intel_display *display)
{
spin_lock_init(&display->irq.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index fd9873ce9755..3773a31e48f2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -58,8 +58,17 @@ void gen11_display_irq_handler(struct intel_display *display);
u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
+struct intel_display_irq_state {
+ u32 iir;
+ u32 eir;
+ u32 hotplug_status;
+ u32 dpinvgtt;
+ u32 pipe_stats[I915_MAX_PIPES];
+};
+
void intel_display_irq_reset(struct intel_display *display);
void intel_display_irq_postinstall(struct intel_display *display);
+void intel_display_irq_ack(struct intel_display *display, struct intel_display_irq_state *state);
u32 i9xx_display_irq_enable_mask(struct intel_display *display);
@@ -67,13 +76,10 @@ u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
-void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
-
void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
void valleyview_pipestat_irq_handler(struct intel_display *display, const u32 pipe_stats[I915_MAX_PIPES]);
-void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt);
void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);
void intel_display_irq_init(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c21b289b8007..b28e89fdb6fd 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -39,7 +39,6 @@
#include "display/intel_display_irq.h"
#include "display/intel_hotplug.h"
#include "display/intel_hotplug_irq.h"
-#include "display/intel_lpe_audio.h"
#include "gt/intel_breadcrumbs.h"
#include "gt/intel_gt.h"
@@ -236,17 +235,15 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
do {
- u32 iir, gt_iir, pm_iir;
- u32 eir = 0, dpinvgtt = 0;
- u32 pipe_stats[I915_MAX_PIPES] = {};
- u32 hotplug_status = 0;
+ struct intel_display_irq_state state = {};
+ u32 gt_iir, pm_iir;
u32 ier = 0;
gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR);
pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR);
- iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
+ state.iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
- if (gt_iir == 0 && pm_iir == 0 && iir == 0)
+ if (gt_iir == 0 && pm_iir == 0 && state.iir == 0)
break;
ret = IRQ_HANDLED;
@@ -272,26 +269,14 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
if (pm_iir)
intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir);
- if (iir & I915_DISPLAY_PORT_INTERRUPT)
- hotplug_status = i9xx_hpd_irq_ack(display);
-
- if (iir & I915_MASTER_ERROR_INTERRUPT)
- vlv_display_error_irq_ack(display, &eir, &dpinvgtt);
-
- /* Call regardless, as some status bits might not be
- * signalled in IIR */
- i9xx_pipestat_irq_ack(display, iir, pipe_stats);
-
- if (iir & (I915_LPE_PIPE_A_INTERRUPT |
- I915_LPE_PIPE_B_INTERRUPT))
- intel_lpe_audio_irq_handler(display);
+ intel_display_irq_ack(display, &state);
/*
* VLV_IIR is single buffered, and reflects the level
* from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
*/
- if (iir)
- intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
+ if (state.iir)
+ intel_uncore_write(&dev_priv->uncore, VLV_IIR, state.iir);
intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
@@ -301,13 +286,13 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
if (pm_iir)
gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);
- if (hotplug_status)
- i9xx_hpd_irq_handler(display, hotplug_status);
+ if (state.hotplug_status)
+ i9xx_hpd_irq_handler(display, state.hotplug_status);
- if (iir & I915_MASTER_ERROR_INTERRUPT)
- vlv_display_error_irq_handler(display, eir, dpinvgtt);
+ if (state.iir & I915_MASTER_ERROR_INTERRUPT)
+ vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
- valleyview_pipestat_irq_handler(display, pipe_stats);
+ valleyview_pipestat_irq_handler(display, state.pipe_stats);
} while (0);
pmu_irq_stats(dev_priv, ret);
@@ -330,16 +315,14 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
do {
- u32 master_ctl, iir;
- u32 eir = 0, dpinvgtt = 0;
- u32 pipe_stats[I915_MAX_PIPES] = {};
- u32 hotplug_status = 0;
+ struct intel_display_irq_state state = {};
+ u32 master_ctl;
u32 ier = 0;
master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
- iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
+ state.iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
- if (master_ctl == 0 && iir == 0)
+ if (master_ctl == 0 && state.iir == 0)
break;
ret = IRQ_HANDLED;
@@ -362,38 +345,25 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
gen8_gt_irq_handler(to_gt(dev_priv), master_ctl);
- if (iir & I915_DISPLAY_PORT_INTERRUPT)
- hotplug_status = i9xx_hpd_irq_ack(display);
-
- if (iir & I915_MASTER_ERROR_INTERRUPT)
- vlv_display_error_irq_ack(display, &eir, &dpinvgtt);
-
- /* Call regardless, as some status bits might not be
- * signalled in IIR */
- i9xx_pipestat_irq_ack(display, iir, pipe_stats);
-
- if (iir & (I915_LPE_PIPE_A_INTERRUPT |
- I915_LPE_PIPE_B_INTERRUPT |
- I915_LPE_PIPE_C_INTERRUPT))
- intel_lpe_audio_irq_handler(display);
+ intel_display_irq_ack(display, &state);
/*
* VLV_IIR is single buffered, and reflects the level
* from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
*/
- if (iir)
- intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
+ if (state.iir)
+ intel_uncore_write(&dev_priv->uncore, VLV_IIR, state.iir);
intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
- if (hotplug_status)
- i9xx_hpd_irq_handler(display, hotplug_status);
+ if (state.hotplug_status)
+ i9xx_hpd_irq_handler(display, state.hotplug_status);
- if (iir & I915_MASTER_ERROR_INTERRUPT)
- vlv_display_error_irq_handler(display, eir, dpinvgtt);
+ if (state.iir & I915_MASTER_ERROR_INTERRUPT)
+ vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
- valleyview_pipestat_irq_handler(display, pipe_stats);
+ valleyview_pipestat_irq_handler(display, state.pipe_stats);
} while (0);
pmu_irq_stats(dev_priv, ret);
@@ -904,39 +874,32 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
do {
- u32 pipe_stats[I915_MAX_PIPES] = {};
+ struct intel_display_irq_state state = {};
u32 eir = 0, eir_stuck = 0;
- u32 hotplug_status = 0;
- u32 iir;
- iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
- if (iir == 0)
+ state.iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
+ if (state.iir == 0)
break;
ret = IRQ_HANDLED;
- if (iir & I915_DISPLAY_PORT_INTERRUPT)
- hotplug_status = i9xx_hpd_irq_ack(display);
+ intel_display_irq_ack(display, &state);
- /* Call regardless, as some status bits might not be
- * signalled in IIR */
- i9xx_pipestat_irq_ack(display, iir, pipe_stats);
-
- if (iir & I915_MASTER_ERROR_INTERRUPT)
+ if (state.iir & I915_MASTER_ERROR_INTERRUPT)
i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
- intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
+ intel_uncore_write(&dev_priv->uncore, GEN2_IIR, state.iir);
- if (iir & I915_USER_INTERRUPT)
- intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir);
+ if (state.iir & I915_USER_INTERRUPT)
+ intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], state.iir);
- if (iir & I915_MASTER_ERROR_INTERRUPT)
+ if (state.iir & I915_MASTER_ERROR_INTERRUPT)
i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
- if (hotplug_status)
- i9xx_hpd_irq_handler(display, hotplug_status);
+ if (state.hotplug_status)
+ i9xx_hpd_irq_handler(display, state.hotplug_status);
- i915_pipestat_irq_handler(display, iir, pipe_stats);
+ i915_pipestat_irq_handler(display, state.iir, state.pipe_stats);
} while (0);
pmu_irq_stats(dev_priv, ret);
@@ -1013,44 +976,37 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
do {
- u32 pipe_stats[I915_MAX_PIPES] = {};
+ struct intel_display_irq_state state = {};
u32 eir = 0, eir_stuck = 0;
- u32 hotplug_status = 0;
- u32 iir;
- iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
- if (iir == 0)
+ state.iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
+ if (state.iir == 0)
break;
ret = IRQ_HANDLED;
- if (iir & I915_DISPLAY_PORT_INTERRUPT)
- hotplug_status = i9xx_hpd_irq_ack(display);
-
- /* Call regardless, as some status bits might not be
- * signalled in IIR */
- i9xx_pipestat_irq_ack(display, iir, pipe_stats);
+ intel_display_irq_ack(display, &state);
- if (iir & I915_MASTER_ERROR_INTERRUPT)
+ if (state.iir & I915_MASTER_ERROR_INTERRUPT)
i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
- intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
+ intel_uncore_write(&dev_priv->uncore, GEN2_IIR, state.iir);
- if (iir & I915_USER_INTERRUPT)
+ if (state.iir & I915_USER_INTERRUPT)
intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0],
- iir);
+ state.iir);
- if (iir & I915_BSD_USER_INTERRUPT)
+ if (state.iir & I915_BSD_USER_INTERRUPT)
intel_engine_cs_irq(to_gt(dev_priv)->engine[VCS0],
- iir >> 25);
+ state.iir >> 25);
- if (iir & I915_MASTER_ERROR_INTERRUPT)
+ if (state.iir & I915_MASTER_ERROR_INTERRUPT)
i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
- if (hotplug_status)
- i9xx_hpd_irq_handler(display, hotplug_status);
+ if (state.hotplug_status)
+ i9xx_hpd_irq_handler(display, state.hotplug_status);
- i965_pipestat_irq_handler(display, iir, pipe_stats);
+ i965_pipestat_irq_handler(display, state.iir, state.pipe_stats);
} while (0);
pmu_irq_stats(dev_priv, IRQ_HANDLED);
--
2.47.3
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 6/6] drm/i915/irq: add intel_display_irq_handler() to irq funcs
2026-05-04 22:26 [PATCH v2 0/6] drm/i915: add display irq hooks Jani Nikula
` (4 preceding siblings ...)
2026-05-04 22:26 ` [PATCH v2 5/6] drm/i915/irq: add intel_display_irq_ack() " Jani Nikula
@ 2026-05-04 22:26 ` Jani Nikula
2026-05-04 23:26 ` ✗ i915.CI.BAT: failure for drm/i915: add display irq hooks Patchwork
6 siblings, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2026-05-04 22:26 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Call the platform specific display irq handler hooks via
intel_display_irq_handler(). Add master_ctl to struct
intel_display_irq_state, and pass the state pointer to the handler where
necessary.
v2: Rebase, handle LPE audio in ack (Ville)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_display_irq.c | 86 ++++++++++++++++---
.../gpu/drm/i915/display/intel_display_irq.h | 11 +--
drivers/gpu/drm/i915/i915_irq.c | 38 +++-----
drivers/gpu/drm/xe/display/xe_display.c | 2 +-
4 files changed, 89 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index a2e05945416d..afa22acfcdde 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -597,8 +597,8 @@ static void i9xx_pipestat_irq_ack(struct intel_display *display,
spin_unlock(&display->irq.lock);
}
-void i915_pipestat_irq_handler(struct intel_display *display,
- u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
+static void i915_pipestat_irq_handler(struct intel_display *display,
+ u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
{
bool blc_event = false;
enum pipe pipe;
@@ -621,8 +621,8 @@ void i915_pipestat_irq_handler(struct intel_display *display,
intel_opregion_asle_intr(display);
}
-void i965_pipestat_irq_handler(struct intel_display *display,
- u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
+static void i965_pipestat_irq_handler(struct intel_display *display,
+ u32 iir, const u32 pipe_stats[I915_MAX_PIPES])
{
bool blc_event = false;
enum pipe pipe;
@@ -648,8 +648,8 @@ void i965_pipestat_irq_handler(struct intel_display *display,
intel_gmbus_irq_handler(display);
}
-void valleyview_pipestat_irq_handler(struct intel_display *display,
- const u32 pipe_stats[I915_MAX_PIPES])
+static void valleyview_pipestat_irq_handler(struct intel_display *display,
+ const u32 pipe_stats[I915_MAX_PIPES])
{
enum pipe pipe;
@@ -1021,7 +1021,8 @@ void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u3
intel_de_write_fw(display, SDEIER, sde_ier);
}
-bool ilk_display_irq_handler(struct intel_display *display)
+static bool ilk_display_irq_handler(struct intel_display *display,
+ const struct intel_display_irq_state *state)
{
u32 de_iir;
bool handled = false;
@@ -1405,7 +1406,7 @@ static void gen8_read_and_ack_pch_irqs(struct intel_display *display, u32 *pch_i
intel_de_write(display, PICAINTERRUPT_IER, pica_ier);
}
-void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
+static void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
{
u32 iir;
enum pipe pipe;
@@ -1566,6 +1567,14 @@ void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
}
}
+static bool gen8_display_irq_handler(struct intel_display *display,
+ const struct intel_display_irq_state *state)
+{
+ gen8_de_irq_handler(display, state->master_ctl);
+
+ return true;
+}
+
u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl)
{
u32 iir;
@@ -1590,7 +1599,8 @@ void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir)
intel_opregion_asle_intr(display);
}
-void gen11_display_irq_handler(struct intel_display *display)
+static bool gen11_display_irq_handler(struct intel_display *display,
+ const struct intel_display_irq_state *state)
{
u32 disp_ctl;
@@ -1606,6 +1616,8 @@ void gen11_display_irq_handler(struct intel_display *display)
intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
intel_display_rpm_assert_unblock(display);
+
+ return true;
}
static void i915gm_irq_cstate_wa_enable(struct intel_display *display)
@@ -1921,8 +1933,8 @@ static void vlv_display_error_irq_ack(struct intel_display *display,
intel_de_write(display, VLV_EMR, emr);
}
-void vlv_display_error_irq_handler(struct intel_display *display,
- u32 eir, u32 dpinvgtt)
+static void vlv_display_error_irq_handler(struct intel_display *display,
+ u32 eir, u32 dpinvgtt)
{
drm_dbg(display->drm, "Master Error, EIR 0x%08x\n", eir);
@@ -2021,6 +2033,28 @@ static void i9xx_display_irq_ack(struct intel_display *display,
i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
}
+static bool i965_display_irq_handler(struct intel_display *display,
+ const struct intel_display_irq_state *state)
+{
+ if (state->hotplug_status)
+ i9xx_hpd_irq_handler(display, state->hotplug_status);
+
+ i965_pipestat_irq_handler(display, state->iir, state->pipe_stats);
+
+ return true;
+}
+
+static bool i915_display_irq_handler(struct intel_display *display,
+ const struct intel_display_irq_state *state)
+{
+ if (state->hotplug_status)
+ i9xx_hpd_irq_handler(display, state->hotplug_status);
+
+ i915_pipestat_irq_handler(display, state->iir, state->pipe_stats);
+
+ return true;
+}
+
static u32 vlv_error_mask(void)
{
/* TODO enable other errors too? */
@@ -2102,6 +2136,20 @@ static void vlv_display_irq_ack(struct intel_display *display,
intel_lpe_audio_irq_handler(display);
}
+static bool vlv_display_irq_handler(struct intel_display *display,
+ const struct intel_display_irq_state *state)
+{
+ if (state->hotplug_status)
+ i9xx_hpd_irq_handler(display, state->hotplug_status);
+
+ if (state->iir & I915_MASTER_ERROR_INTERRUPT)
+ vlv_display_error_irq_handler(display, state->eir, state->dpinvgtt);
+
+ valleyview_pipestat_irq_handler(display, state->pipe_stats);
+
+ return true;
+}
+
static void ibx_display_irq_reset(struct intel_display *display)
{
if (HAS_PCH_NOP(display))
@@ -2490,39 +2538,46 @@ struct intel_display_irq_funcs {
void (*reset)(struct intel_display *display);
void (*postinstall)(struct intel_display *display);
void (*ack)(struct intel_display *display, struct intel_display_irq_state *state);
+ bool (*handler)(struct intel_display *display, const struct intel_display_irq_state *state);
};
struct intel_display_irq_funcs gen11_display_irq_funcs = {
.reset = gen11_display_irq_reset,
.postinstall = gen11_de_irq_postinstall,
+ .handler = gen11_display_irq_handler,
};
struct intel_display_irq_funcs gen8_display_irq_funcs = {
.reset = gen8_display_irq_reset,
.postinstall = gen8_de_irq_postinstall,
+ .handler = gen8_display_irq_handler,
};
struct intel_display_irq_funcs vlv_display_irq_funcs = {
.reset = vlv_display_irq_reset,
.postinstall = vlv_display_irq_postinstall,
.ack = vlv_display_irq_ack,
+ .handler = vlv_display_irq_handler,
};
struct intel_display_irq_funcs ilk_display_irq_funcs = {
.reset = ilk_display_irq_reset,
.postinstall = ilk_de_irq_postinstall,
+ .handler = ilk_display_irq_handler,
};
struct intel_display_irq_funcs i965_display_irq_funcs = {
.reset = i9xx_display_irq_reset,
.postinstall = i965_display_irq_postinstall,
.ack = i9xx_display_irq_ack,
+ .handler = i965_display_irq_handler,
};
struct intel_display_irq_funcs i915_display_irq_funcs = {
.reset = i9xx_display_irq_reset,
.postinstall = i915_display_irq_postinstall,
.ack = i9xx_display_irq_ack,
+ .handler = i915_display_irq_handler,
};
void intel_display_irq_reset(struct intel_display *display)
@@ -2542,6 +2597,15 @@ void intel_display_irq_ack(struct intel_display *display,
display->irq.funcs->ack(display, state);
}
+bool intel_display_irq_handler(struct intel_display *display,
+ const struct intel_display_irq_state *state)
+{
+ if (!display->irq.funcs->handler)
+ return true;
+
+ return display->irq.funcs->handler(display, state);
+}
+
void intel_display_irq_init(struct intel_display *display)
{
spin_lock_init(&display->irq.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index 3773a31e48f2..a1227cee885a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -51,14 +51,12 @@ void bdw_disable_vblank(struct drm_crtc *crtc);
void ilk_display_irq_master_disable(struct intel_display *display, u32 *de_ier, u32 *sde_ier);
void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u32 sde_ier);
-bool ilk_display_irq_handler(struct intel_display *display);
-void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl);
-void gen11_display_irq_handler(struct intel_display *display);
u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
struct intel_display_irq_state {
+ u32 master_ctl;
u32 iir;
u32 eir;
u32 hotplug_status;
@@ -69,6 +67,7 @@ struct intel_display_irq_state {
void intel_display_irq_reset(struct intel_display *display);
void intel_display_irq_postinstall(struct intel_display *display);
void intel_display_irq_ack(struct intel_display *display, struct intel_display_irq_state *state);
+bool intel_display_irq_handler(struct intel_display *display, const struct intel_display_irq_state *state);
u32 i9xx_display_irq_enable_mask(struct intel_display *display);
@@ -76,12 +75,6 @@ u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
-void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
-void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
-void valleyview_pipestat_irq_handler(struct intel_display *display, const u32 pipe_stats[I915_MAX_PIPES]);
-
-void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);
-
void intel_display_irq_init(struct intel_display *display);
void i915gm_irq_cstate_wa(struct intel_display *display, bool enable);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b28e89fdb6fd..30ce462e92ab 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -38,7 +38,6 @@
#include "display/intel_display_irq.h"
#include "display/intel_hotplug.h"
-#include "display/intel_hotplug_irq.h"
#include "gt/intel_breadcrumbs.h"
#include "gt/intel_gt.h"
@@ -286,13 +285,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
if (pm_iir)
gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);
- if (state.hotplug_status)
- i9xx_hpd_irq_handler(display, state.hotplug_status);
-
- if (state.iir & I915_MASTER_ERROR_INTERRUPT)
- vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
-
- valleyview_pipestat_irq_handler(display, state.pipe_stats);
+ intel_display_irq_handler(display, &state);
} while (0);
pmu_irq_stats(dev_priv, ret);
@@ -357,13 +350,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
- if (state.hotplug_status)
- i9xx_hpd_irq_handler(display, state.hotplug_status);
-
- if (state.iir & I915_MASTER_ERROR_INTERRUPT)
- vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
-
- valleyview_pipestat_irq_handler(display, state.pipe_stats);
+ intel_display_irq_handler(display, &state);
} while (0);
pmu_irq_stats(dev_priv, ret);
@@ -410,7 +397,7 @@ static irqreturn_t ilk_irq_handler(int irq, void *arg)
ret = IRQ_HANDLED;
}
- if (ilk_display_irq_handler(display))
+ if (intel_display_irq_handler(display, NULL))
ret = IRQ_HANDLED;
if (GRAPHICS_VER(i915) >= 6) {
@@ -472,8 +459,11 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
/* IRQs are synced during runtime_suspend, we don't require a wakeref */
if (master_ctl & ~GEN8_GT_IRQS) {
+ const struct intel_display_irq_state state = {
+ .master_ctl = master_ctl,
+ };
disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
- gen8_de_irq_handler(display, master_ctl);
+ intel_display_irq_handler(display, &state);
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
}
@@ -525,7 +515,7 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
/* IRQs are synced during runtime_suspend, we don't require a wakeref */
if (master_ctl & GEN11_DISPLAY_IRQ)
- gen11_display_irq_handler(display);
+ intel_display_irq_handler(display, NULL);
gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);
@@ -592,7 +582,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
gen11_gt_irq_handler(gt, master_ctl);
if (master_ctl & GEN11_DISPLAY_IRQ)
- gen11_display_irq_handler(display);
+ intel_display_irq_handler(display, NULL);
gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl);
@@ -896,10 +886,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
if (state.iir & I915_MASTER_ERROR_INTERRUPT)
i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
- if (state.hotplug_status)
- i9xx_hpd_irq_handler(display, state.hotplug_status);
-
- i915_pipestat_irq_handler(display, state.iir, state.pipe_stats);
+ intel_display_irq_handler(display, &state);
} while (0);
pmu_irq_stats(dev_priv, ret);
@@ -1003,10 +990,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
if (state.iir & I915_MASTER_ERROR_INTERRUPT)
i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
- if (state.hotplug_status)
- i9xx_hpd_irq_handler(display, state.hotplug_status);
-
- i965_pipestat_irq_handler(display, state.iir, state.pipe_stats);
+ intel_display_irq_handler(display, &state);
} while (0);
pmu_irq_stats(dev_priv, IRQ_HANDLED);
diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index 736a5e6938d6..4f283fb79554 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -214,7 +214,7 @@ void xe_display_irq_handler(struct xe_device *xe, u32 master_ctl)
return;
if (master_ctl & DISPLAY_IRQ)
- gen11_display_irq_handler(display);
+ intel_display_irq_handler(display, NULL);
}
void xe_display_irq_enable(struct xe_device *xe, u32 gu_misc_iir)
--
2.47.3
^ permalink raw reply related [flat|nested] 8+ messages in thread* ✗ i915.CI.BAT: failure for drm/i915: add display irq hooks
2026-05-04 22:26 [PATCH v2 0/6] drm/i915: add display irq hooks Jani Nikula
` (5 preceding siblings ...)
2026-05-04 22:26 ` [PATCH v2 6/6] drm/i915/irq: add intel_display_irq_handler() " Jani Nikula
@ 2026-05-04 23:26 ` Patchwork
6 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2026-05-04 23:26 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6262 bytes --]
== Series Details ==
Series: drm/i915: add display irq hooks
URL : https://patchwork.freedesktop.org/series/165935/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_18410 -> Patchwork_165935v1
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_165935v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_165935v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v1/index.html
Participating hosts (41 -> 40)
------------------------------
Additional (1): bat-adls-6
Missing (2): bat-dg2-13 fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_165935v1:
### IGT changes ###
#### Possible regressions ####
* igt@i915_module_load@load:
- bat-atsm-1: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18410/bat-atsm-1/igt@i915_module_load@load.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v1/bat-atsm-1/igt@i915_module_load@load.html
Known issues
------------
Here are the changes found in Patchwork_165935v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@dmabuf@all-tests:
- bat-adls-6: NOTRUN -> [SKIP][3] ([i915#15931])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v1/bat-adls-6/igt@dmabuf@all-tests.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-adls-6: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v1/bat-adls-6/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_tiled_pread_basic@basic:
- bat-adls-6: NOTRUN -> [SKIP][5] ([i915#15656])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v1/bat-adls-6/igt@gem_tiled_pread_basic@basic.html
* igt@intel_hwmon@hwmon-read:
- bat-adls-6: NOTRUN -> [SKIP][6] ([i915#7707]) +1 other test skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v1/bat-adls-6/igt@intel_hwmon@hwmon-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-adls-6: NOTRUN -> [SKIP][7] ([i915#4103]) +1 other test skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v1/bat-adls-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-adls-6: NOTRUN -> [SKIP][8] ([i915#3555] / [i915#3840])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v1/bat-adls-6/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-adls-6: NOTRUN -> [SKIP][9]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v1/bat-adls-6/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pm_backlight@basic-brightness:
- bat-adls-6: NOTRUN -> [SKIP][10] ([i915#5354])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v1/bat-adls-6/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_psr@psr-primary-mmap-gtt:
- bat-adls-6: NOTRUN -> [SKIP][11] ([i915#1072] / [i915#9732]) +3 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v1/bat-adls-6/igt@kms_psr@psr-primary-mmap-gtt.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-adls-6: NOTRUN -> [SKIP][12] ([i915#3555])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v1/bat-adls-6/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-read:
- bat-adls-6: NOTRUN -> [SKIP][13] ([i915#3291]) +2 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v1/bat-adls-6/igt@prime_vgem@basic-fence-read.html
#### Possible fixes ####
* igt@i915_selftest@live:
- bat-mtlp-8: [DMESG-FAIL][14] ([i915#12061]) -> [PASS][15] +1 other test pass
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18410/bat-mtlp-8/igt@i915_selftest@live.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v1/bat-mtlp-8/igt@i915_selftest@live.html
* igt@i915_selftest@live@workarounds:
- bat-mtlp-9: [DMESG-FAIL][16] ([i915#12061]) -> [PASS][17] +1 other test pass
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18410/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v1/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#15656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15656
[i915#15931]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15931
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
Build changes
-------------
* Linux: CI_DRM_18410 -> Patchwork_165935v1
CI-20190529: 20190529
CI_DRM_18410: 5521e3e7a175fef7d7a35a4b8fd17ca473be8e7e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8883: 8214859d2c4ecf8f81a08a3d2cd26f0a50d2b513 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_165935v1: 5521e3e7a175fef7d7a35a4b8fd17ca473be8e7e @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_165935v1/index.html
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