public inbox for intel-gfx@lists.freedesktop.org
 help / color / mirror / Atom feed
From: "Ceraolo Spurio, Daniele" <daniele.ceraolospurio@intel.com>
To: "Teres Alexis, Alan Previn" <alan.previn.teres.alexis@intel.com>,
	"daniel@ffwll.ch" <daniel@ffwll.ch>,
	"joonas.lahtinen@linux.intel.com"
	<joonas.lahtinen@linux.intel.com>
Cc: "Intel-gfx@lists.freedesktop.org"
	<Intel-gfx@lists.freedesktop.org>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>,
	"chris.p.wilson@linux.intel.com" <chris.p.wilson@linux.intel.com>,
	"Roper, Matthew D" <matthew.d.roper@intel.com>,
	"faith.ekstrand@collabora.com" <faith.ekstrand@collabora.com>,
	"Das, Nirmoy" <nirmoy.das@intel.com>
Subject: Re: [Intel-gfx] IOCTL feature detection (Was: Re: [PATCH 8/8] drm/i915: Allow user to set cache at BO creation)
Date: Wed, 26 Apr 2023 11:10:00 -0700	[thread overview]
Message-ID: <d6eb91b3-9a3e-40ea-a7f9-23c4591c860d@intel.com> (raw)
In-Reply-To: <a05b4a926fc84158476c59a7c7d39651d0ff1d9d.camel@intel.com>



On 4/26/2023 9:48 AM, Teres Alexis, Alan Previn wrote:
> On Wed, 2023-04-26 at 13:52 +0200, Daniel Vetter wrote:
>> On Tue, Apr 25, 2023 at 04:41:54PM +0300, Joonas Lahtinen wrote:
>>> (+ Faith and Daniel as they have been involved in previous discussions)
>>> Quoting Jordan Justen (2023-04-24 20:13:00)
>>>> On 2023-04-24 02:08:43, Tvrtko Ursulin wrote:
>>>>>
> alan:snip
>
>> - the more a feature spans drivers/modules, the more it should be
>>    discovered by trying it out, e.g. dma-buf fence import/export was a huge
>>    discussion, luckily mesa devs figured out how to transparantly fall back
>>    at runtime so we didn't end up merging the separate feature flag (I
>>    think at least, can't find it). pxp being split across i915/me/fw/who
>>    knows what else is kinda similar so I'd heavily lean towards discovery
>>    by creating a context
>>
>> - pxp taking 8s to init a ctx sounds very broken, irrespective of anything
>>    else

I think there has been a bit of confusion in regards to this timeout and 
to where it applies, so let me try to clarify to make sure we're all on 
the same page (Alan has already explained most of it below, but I'm 
going to go in a bit more detail and I want to make sure it's all in one 
place for reference).
Before we can do any PXP operation, dependencies need to be satisfied, 
some of which are outside of i915. For MTL, these are:

GSC FW needs to be loaded (~250 ms)
HuC FW needs to be authenticated for PXP ops (~20 ms)
MEI modules need to be bound (depends on the probe ordering, but usually 
a few secs)
GSC SW proxy via MEI needs to be established (~500 ms normally, but can 
take a few seconds on the first boot after a firmware update)

Due to the fact that these can take several seconds in total to 
complete, to avoid stalling driver load/resume for that long we moved 
the i915-side operations to a separate worker and we register i915 
before they've completed. This means that we can get a PXP context 
creation call before all the dependencies are in place, in which case we 
do need to wait and that's where the 8s come from. After all the pieces 
are in place, a PXP context creation call is much faster (up to ~150 ms, 
which is the time required to start the PXP session if it is not already 
running).

The reason why we suggested a dedicated getparam was to avoid requiring 
early users to wait for all of that to happen just to check the 
capability. By the time an user actually wants to use PXP, we're likely 
done with the prep steps (or at least we're far along with them) and 
therefore the wait will be short.

> Alan: Please be aware that:
> 1. the wait-timeout was changed to 1 second sometime back.
> 2. the I'm not deciding the time-out. I initially wanted to keep it at the same
> timeout as ADL (250 milisec) - and ask the UMD to retry if user needs it. (as per
> same ADL behavior). Daniele requested to move it to 8 seconds - but thru review
> process, we reduced it to 1 second.
> 3. In anycase, thats just the wait-timeout - and we know it wont succeed until
> ~6 seconds after i915 (~9 secs after boot). The issue isnt our hardware or i915
> - its the component driver load <-- this is what's broken.

I think the question here is whether the mei driver is taking a long 
time to probe or if it is just being probed late. In the latter case, I 
wouldn't call it broken.

>
> Details: PXP context is dependent on gsc-fw load, huc-firmware load, mei-gsc-proxy
> component driver load + bind, huc-authentication and gsc-proxy-init-handshake.
> Most of above steps begin rather quickly during i915 driver load - the delay
> seems to come from a very late mei-gsc-proxy component driver load. In fact the
> parent mei-me driver is only getting ~6 seconds after i915 init is done. That
> blocks the gsc-proxy-init-handshake and huc-authentication and lastly PXP.
>
> That said, what is broken is why it takes so long to get the component drivers
> to come up. NOTE: PXP isnt really doing anything differently in the context
> creation flow (in terms of time-consuming-steps compared to ADL) besides the
> extra dependency waits these.
>
> We can actually go back to the original timeout of 250 milisecs like we have in ADL
> but will fail if MESA calls in too early (but will succeed later) ... or...
> we can create the GET_PARAMs.
>
> A better idea would be to figure out how to control the driver load order and
> force mei driver + components to get called right after i915. I was informed
> there is no way to control this and changes here will likely not be accepted
> upstream.

we could add a device link to mark i915 as a consumer of mei, but I 
believe that wouldn't work for 2 reasons

1 - on discrete, mei binds to a child device of i915, so the dependency 
is reversed
2 - the link might just delay the i915 load to after the mei load, which 
I'm not sure it is something we want (and at that point we could also 
just wait for mei to bind from within the i915 load).

Daniele

>
> ++ Daniele - can you chime in?
>
> Take note that ADL has the same issue but for whatever reason, the dependant
> mei component on ADL loaded much sooner - so it was never an issue that was
> caught but still existed on ADL time merge (if users customize the kernel +
> compositor for fastboot it will happen).(i realize I havent tested ADL with the
> new kernel configs that we use to also boot PXP on MTL - wonder if the new
> mei configs are causing the delay - i.e. ADL customer could suddenly see this
> 6 sec delay too. - something i have to check now)


  reply	other threads:[~2023-04-26 18:10 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-19 23:00 [Intel-gfx] [PATCH 0/8] drm/i915/mtl: Define MOCS and PAT tables for MTL fei.yang
2023-04-19 23:00 ` [Intel-gfx] [PATCH 1/8] drm/i915/mtl: Set has_llc=0 fei.yang
2023-04-20 10:20   ` Das, Nirmoy
2023-04-19 23:00 ` [Intel-gfx] [PATCH 2/8] drm/i915/mtl: Define MOCS and PAT tables for MTL fei.yang
2023-04-20 20:29   ` Matt Roper
2023-04-19 23:00 ` [Intel-gfx] [PATCH 3/8] drm/i915/mtl: Add PTE encode function fei.yang
2023-04-20 20:40   ` Matt Roper
2023-04-21 17:27     ` Yang, Fei
2023-04-21 17:42       ` Matt Roper
2023-04-23  7:37         ` Yang, Fei
2023-04-24 17:20           ` Matt Roper
2023-04-24 18:41             ` Yang, Fei
2023-04-19 23:00 ` [Intel-gfx] [PATCH 4/8] drm/i915/mtl: workaround coherency issue for Media fei.yang
2023-04-20  8:26   ` Andrzej Hajda
2023-04-20 11:36   ` Das, Nirmoy
2023-04-20 20:52   ` Matt Roper
2023-04-19 23:00 ` [Intel-gfx] [PATCH 5/8] drm/i915/mtl: end support for set caching ioctl fei.yang
2023-04-20 21:05   ` Matt Roper
2023-04-19 23:00 ` [Intel-gfx] [PATCH 6/8] drm/i915: preparation for using PAT index fei.yang
2023-04-20  8:45   ` Andrzej Hajda
2023-04-20 21:14   ` Matt Roper
2023-04-19 23:00 ` [Intel-gfx] [PATCH 7/8] drm/i915: use pat_index instead of cache_level fei.yang
2023-04-20 10:13   ` Andrzej Hajda
2023-04-20 12:39     ` Tvrtko Ursulin
2023-04-20 20:34       ` Yang, Fei
2023-04-21  8:43   ` Tvrtko Ursulin
2023-04-21 10:17   ` Tvrtko Ursulin
2023-04-23  6:12     ` Yang, Fei
2023-04-24  8:41       ` Tvrtko Ursulin
2023-04-21 11:39   ` Tvrtko Ursulin
2023-04-23  6:52     ` Yang, Fei
2023-04-24  9:22       ` Tvrtko Ursulin
2023-04-19 23:00 ` [Intel-gfx] [PATCH 8/8] drm/i915: Allow user to set cache at BO creation fei.yang
2023-04-20 11:39   ` Andi Shyti
2023-04-20 13:06     ` Tvrtko Ursulin
2023-04-20 16:11       ` Yang, Fei
2023-04-20 16:29         ` Andi Shyti
2023-04-21 20:48         ` Jordan Justen
     [not found]           ` <BYAPR11MB2567F03AD43D7E2DE2628D5D9A669@BYAPR11MB2567.namprd11.prod.outlook.com>
     [not found]             ` <168232538771.392286.3227368099155268955@jljusten-skl>
2023-04-24  9:08               ` Tvrtko Ursulin
2023-04-24 17:13                 ` Jordan Justen
2023-04-25 13:41                   ` [Intel-gfx] IOCTL feature detection (Was: Re: [PATCH 8/8] drm/i915: Allow user to set cache at BO creation) Joonas Lahtinen
2023-04-25 17:21                     ` Teres Alexis, Alan Previn
2023-04-25 18:19                     ` Jordan Justen
2023-04-26 11:52                     ` Daniel Vetter
2023-04-26 16:48                       ` Teres Alexis, Alan Previn
2023-04-26 18:10                         ` Ceraolo Spurio, Daniele [this message]
2023-04-26 20:04                       ` Jordan Justen
2023-04-19 23:29 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Define MOCS and PAT tables for MTL (rev8) Patchwork
2023-04-19 23:51 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-04-20 11:30 ` [Intel-gfx] [PATCH 0/8] drm/i915/mtl: Define MOCS and PAT tables for MTL Andi Shyti

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=d6eb91b3-9a3e-40ea-a7f9-23c4591c860d@intel.com \
    --to=daniele.ceraolospurio@intel.com \
    --cc=Intel-gfx@lists.freedesktop.org \
    --cc=alan.previn.teres.alexis@intel.com \
    --cc=chris.p.wilson@linux.intel.com \
    --cc=daniel@ffwll.ch \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=faith.ekstrand@collabora.com \
    --cc=joonas.lahtinen@linux.intel.com \
    --cc=matthew.d.roper@intel.com \
    --cc=nirmoy.das@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox