From: Jani Nikula <jani.nikula@linux.intel.com>
To: Suraj Kandpal <suraj.kandpal@intel.com>,
intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: ankit.k.nautiyal@intel.com, Suraj Kandpal <suraj.kandpal@intel.com>
Subject: Re: [PATCH 1/3] drm/i915/ddi: add helper to compute DDI clock frequency
Date: Tue, 11 Aug 2026 20:07:14 +0300 [thread overview]
Message-ID: <d76160985b70527e3ba2f2fb7cb772b83c5d26e3@intel.com> (raw)
In-Reply-To: <20260811025658.2376173-2-suraj.kandpal@intel.com>
On Tue, 11 Aug 2026, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Add intel_ddi_link_symbol_clock() to return the DDI clock frequency for
> a given port clock:
> DP 8b/10b : rate / 10
rate
> DP 128b/132b (UHBR) : rate / 32
(10/32) * rate
> HDMI FRL : rate / 18
(10/18) * rate
> HDMI TMDS : rate
>
> The DP case reuses intel_dp_link_symbol_clock().
> This will help in upcoming commits to decide value to be written
> in DDI_CLK_VALFREQ.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 11 +++++++++++
> drivers/gpu/drm/i915/display/intel_ddi.h | 1 +
> 2 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index bf5788c5bbd3..dd9064592ec9 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1529,6 +1529,17 @@ int intel_ddi_level(struct intel_encoder *encoder,
> return level;
> }
>
> +int intel_ddi_link_symbol_clock(struct intel_encoder *encoder, int clock)
> +{
> + if (intel_encoder_is_dp(encoder))
> + return intel_dp_link_symbol_clock(clock);
> +
> + if (intel_hdmi_is_frl(clock))
> + return DIV_ROUND_CLOSEST(clock * 10, 18);
> +
> + return clock;
> +}
> +
> static void
> hsw_set_signal_levels(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
> index 580ecb09b8b6..239d5a403f91 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> @@ -81,6 +81,7 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
> int intel_ddi_level(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> int lane);
> +int intel_ddi_link_symbol_clock(struct intel_encoder *encoder, int clock);
> void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
> struct intel_encoder *encoder,
> struct intel_crtc *crtc);
--
Jani Nikula, Intel
next prev parent reply other threads:[~2026-08-11 17:07 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-11 2:56 [PATCH 0/3] Fix value being written to DDI_CLK_VALFREQ Suraj Kandpal
2026-08-11 2:56 ` [PATCH 1/3] drm/i915/ddi: add helper to compute DDI clock frequency Suraj Kandpal
2026-08-11 17:07 ` Jani Nikula [this message]
2026-08-11 17:24 ` Kandpal, Suraj
2026-08-11 2:56 ` [PATCH 2/3] drm/i915/cx0: program DDI_CLK_VALFREQ with " Suraj Kandpal
2026-08-11 2:56 ` [PATCH 3/3] drm/i915/lt_phy: " Suraj Kandpal
2026-08-11 3:59 ` ✓ i915.CI.BAT: success for Fix value being written to DDI_CLK_VALFREQ Patchwork
2026-08-11 6:08 ` ✗ i915.CI.Full: failure " Patchwork
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