* [PATCH v1 0/2] drm/i915/display: SKL_DSSM / DE_CAP fixes
@ 2026-07-27 22:21 Michał Grzelak
2026-07-27 22:21 ` [PATCH v1 1/2] drm/i915/display: fix SKL_DSSM register masks Michał Grzelak
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Michał Grzelak @ 2026-07-27 22:21 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jani Nikula, Michał Grzelak
Michał Grzelak (2):
drm/i915/display: fix SKL_DSSM register masks
drm/i915/xe2lpd+: disable 3D LUT if unsupported
drivers/gpu/drm/i915/display/intel_color.c | 3 +++
drivers/gpu/drm/i915/display/intel_display_device.c | 8 ++++++++
drivers/gpu/drm/i915/display/intel_display_device.h | 4 ++++
drivers/gpu/drm/i915/display/intel_display_regs.h | 9 +++++----
4 files changed, 20 insertions(+), 4 deletions(-)
--
2.45.2
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v1 1/2] drm/i915/display: fix SKL_DSSM register masks 2026-07-27 22:21 [PATCH v1 0/2] drm/i915/display: SKL_DSSM / DE_CAP fixes Michał Grzelak @ 2026-07-27 22:21 ` Michał Grzelak 2026-07-28 7:44 ` Jani Nikula 2026-07-27 22:21 ` [PATCH v1 2/2] drm/i915/xe2lpd+: disable 3D LUT if unsupported Michał Grzelak 2026-07-27 23:04 ` ✗ i915.CI.BAT: failure for drm/i915/display: SKL_DSSM / DE_CAP fixes Patchwork 2 siblings, 1 reply; 6+ messages in thread From: Michał Grzelak @ 2026-07-27 22:21 UTC (permalink / raw) To: intel-gfx, intel-xe; +Cc: Jani Nikula, Michał Grzelak Add indentation into SKL_DSSM reference clock macros. Replace bit shifts with REG_GENMASK(). Signed-off-by: Michał Grzelak <michal.grzelak@intel.com> --- drivers/gpu/drm/i915/display/intel_display_regs.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h index 0f5018482497..0677ca2dde00 100644 --- a/drivers/gpu/drm/i915/display/intel_display_regs.h +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h @@ -1779,10 +1779,10 @@ #define XE2LPD_DE_CAP_SCALER_SINGLE 1 #define SKL_DSSM _MMIO(0x51004) -#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) -#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) -#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) -#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) +#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK REG_GENMASK(31, 29) +#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz 0 +#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz REG_GENMASK(29, 29) +#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz REG_GENMASK(30, 29) /*GEN11 chicken */ #define _PIPEA_CHICKEN 0x70038 -- 2.45.2 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v1 1/2] drm/i915/display: fix SKL_DSSM register masks 2026-07-27 22:21 ` [PATCH v1 1/2] drm/i915/display: fix SKL_DSSM register masks Michał Grzelak @ 2026-07-28 7:44 ` Jani Nikula 0 siblings, 0 replies; 6+ messages in thread From: Jani Nikula @ 2026-07-28 7:44 UTC (permalink / raw) To: Michał Grzelak, intel-gfx, intel-xe; +Cc: Michał Grzelak On Tue, 28 Jul 2026, Michał Grzelak <michal.grzelak@intel.com> wrote: > Add indentation into SKL_DSSM reference clock macros. Replace bit shifts > with REG_GENMASK(). > > Signed-off-by: Michał Grzelak <michal.grzelak@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display_regs.h | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h > index 0f5018482497..0677ca2dde00 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h > @@ -1779,10 +1779,10 @@ > #define XE2LPD_DE_CAP_SCALER_SINGLE 1 > > #define SKL_DSSM _MMIO(0x51004) > -#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) > -#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) > -#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) > -#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) > +#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK REG_GENMASK(31, 29) > +#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz 0 > +#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz REG_GENMASK(29, 29) > +#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz REG_GENMASK(30, 29) Define _MASK with REG_GENMASK and values with REG_FIELD_PREP. The above is just plain wrong. > > /*GEN11 chicken */ > #define _PIPEA_CHICKEN 0x70038 -- Jani Nikula, Intel ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v1 2/2] drm/i915/xe2lpd+: disable 3D LUT if unsupported 2026-07-27 22:21 [PATCH v1 0/2] drm/i915/display: SKL_DSSM / DE_CAP fixes Michał Grzelak 2026-07-27 22:21 ` [PATCH v1 1/2] drm/i915/display: fix SKL_DSSM register masks Michał Grzelak @ 2026-07-27 22:21 ` Michał Grzelak 2026-07-28 7:42 ` Jani Nikula 2026-07-27 23:04 ` ✗ i915.CI.BAT: failure for drm/i915/display: SKL_DSSM / DE_CAP fixes Patchwork 2 siblings, 1 reply; 6+ messages in thread From: Michał Grzelak @ 2026-07-27 22:21 UTC (permalink / raw) To: intel-gfx, intel-xe Cc: Jani Nikula, Michał Grzelak, Chaitanya Borah Kumar XE2LPD_DE_CAP_3DLUT_MASK is defined but never used. Check with it if 3DLUT is enabled. Check DE_CAP register if 3D LUT is disabled. Store the info in a new field of struct intel_display_runtime_info. Add macros for checking both 3D LUT hardware and 3D LUT capability. Initialize has_3dlut to 1 on each platform since LNL. Log value of has_3dlut in intel_display_device_info_print(). Bspec: 71161 Cc: Chaitanya Borah Kumar <chaitanya.borah.kumar@intel.com> Signed-off-by: Michał Grzelak <michal.grzelak@intel.com> --- drivers/gpu/drm/i915/display/intel_color.c | 3 +++ drivers/gpu/drm/i915/display/intel_display_device.c | 8 ++++++++ drivers/gpu/drm/i915/display/intel_display_device.h | 4 ++++ drivers/gpu/drm/i915/display/intel_display_regs.h | 1 + 4 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 87ced9f6ff40..ffdefb51a264 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -4258,6 +4258,9 @@ intel_color_load_plane_luts(struct intel_dsb *dsb, bool intel_color_crtc_has_3dlut(struct intel_display *display, enum pipe pipe) { + if (!HAS_3DLUT(display)) + return false; + if (DISPLAY_VER(display) >= 12) return pipe == PIPE_A || pipe == PIPE_B; else diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index f17fc2c68472..45c791531f85 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -1335,6 +1335,7 @@ static const struct platform_desc dg2_desc = { BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B), \ + .__runtime_defaults.has_3dlut = 1, \ .__runtime_defaults.has_dmc = 1, \ .__runtime_defaults.has_dsc = 1, \ .__runtime_defaults.has_hdcp = 1, \ @@ -1345,6 +1346,7 @@ static const struct platform_desc dg2_desc = { static const struct intel_display_device_info xe_lpdp_display = { XE_LPDP_FEATURES, + .__runtime_defaults.has_3dlut = 0, }; static const struct intel_display_device_info xe2_lpd_display = { @@ -1385,6 +1387,7 @@ static const struct intel_display_device_info xe2_hpd_display = { XE_LPDP_FEATURES, .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), + .__runtime_defaults.has_3dlut = 0, }; static const u16 mtl_u_ids[] = { @@ -1935,6 +1938,10 @@ static void __intel_display_device_info_runtime_init(struct intel_display *displ if (DISPLAY_VER(display) >= 20) { u32 cap = intel_de_read(display, XE2LPD_DE_CAP); + if (REG_FIELD_GET(XE2LPD_DE_CAP_3DLUT_MASK, cap) == + XE2LPD_DE_CAP_3DLUT_REMOVED) + display_runtime->has_3dlut = 0; + if (REG_FIELD_GET(XE2LPD_DE_CAP_DSC_MASK, cap) == XE2LPD_DE_CAP_DSC_REMOVED) display_runtime->has_dsc = 0; @@ -1996,6 +2003,7 @@ void intel_display_device_info_print(const struct intel_display_device_info *inf DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); #undef PRINT_FLAG + drm_printf(p, "has_3dlut: %s\n", str_yes_no(runtime->has_3dlut)); drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp)); drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc)); drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc)); diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 7121e7cd9512..34ee7993be33 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -147,6 +147,9 @@ struct intel_display_platforms { #define HAS_128B_Y_TILING(__display) (!(__display)->platform.i915g && !(__display)->platform.i915gm) #define HAS_2PPC(__display) (DISPLAY_VER(__display) >= 10) +#define HAS_3DLUT_HW(__display) (DISPLAY_VER(__display) >= 10) +#define HAS_3DLUT_CAP(__display) (IS_DISPLAY_VER(__display, 10, 20) || DISPLAY_RUNTIME_INFO(__display)->has_3dlut) +#define HAS_3DLUT(__display) (HAS_3DLUT_HW(__display) && HAS_3DLUT_CAP(__display)) #define HAS_4TILE(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14) #define HAS_ASYNC_FLIPS(__display) (DISPLAY_VER(__display) >= 5) #define HAS_AS_SDP(__display) (DISPLAY_VER(__display) >= 13) @@ -304,6 +307,7 @@ struct intel_display_runtime_info { u8 fbc_mask; + bool has_3dlut; bool has_hdcp; bool has_dmc; bool has_dsc; diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h index 0677ca2dde00..7b2332e2fae2 100644 --- a/drivers/gpu/drm/i915/display/intel_display_regs.h +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h @@ -1773,6 +1773,7 @@ #define XE2LPD_DE_CAP _MMIO(0x41100) #define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30) +#define XE2LPD_DE_CAP_3DLUT_REMOVED 1 #define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28) #define XE2LPD_DE_CAP_DSC_REMOVED 1 #define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26) -- 2.45.2 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v1 2/2] drm/i915/xe2lpd+: disable 3D LUT if unsupported 2026-07-27 22:21 ` [PATCH v1 2/2] drm/i915/xe2lpd+: disable 3D LUT if unsupported Michał Grzelak @ 2026-07-28 7:42 ` Jani Nikula 0 siblings, 0 replies; 6+ messages in thread From: Jani Nikula @ 2026-07-28 7:42 UTC (permalink / raw) To: Michał Grzelak, intel-gfx, intel-xe Cc: Michał Grzelak, Chaitanya Borah Kumar On Tue, 28 Jul 2026, Michał Grzelak <michal.grzelak@intel.com> wrote: > XE2LPD_DE_CAP_3DLUT_MASK is defined but never used. Check with it if > 3DLUT is enabled. > > Check DE_CAP register if 3D LUT is disabled. Store the info in a new > field of struct intel_display_runtime_info. > > Add macros for checking both 3D LUT hardware and 3D LUT capability. What's the difference? > Initialize has_3dlut to 1 on each platform since LNL. > > Log value of has_3dlut in intel_display_device_info_print(). > > Bspec: 71161 > Cc: Chaitanya Borah Kumar <chaitanya.borah.kumar@intel.com> > Signed-off-by: Michał Grzelak <michal.grzelak@intel.com> > --- > drivers/gpu/drm/i915/display/intel_color.c | 3 +++ > drivers/gpu/drm/i915/display/intel_display_device.c | 8 ++++++++ > drivers/gpu/drm/i915/display/intel_display_device.h | 4 ++++ > drivers/gpu/drm/i915/display/intel_display_regs.h | 1 + > 4 files changed, 16 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c > index 87ced9f6ff40..ffdefb51a264 100644 > --- a/drivers/gpu/drm/i915/display/intel_color.c > +++ b/drivers/gpu/drm/i915/display/intel_color.c > @@ -4258,6 +4258,9 @@ intel_color_load_plane_luts(struct intel_dsb *dsb, > bool > intel_color_crtc_has_3dlut(struct intel_display *display, enum pipe pipe) > { > + if (!HAS_3DLUT(display)) > + return false; > + > if (DISPLAY_VER(display) >= 12) > return pipe == PIPE_A || pipe == PIPE_B; > else > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c > index f17fc2c68472..45c791531f85 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_device.c > +++ b/drivers/gpu/drm/i915/display/intel_display_device.c > @@ -1335,6 +1335,7 @@ static const struct platform_desc dg2_desc = { > BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ > BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \ > .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B), \ > + .__runtime_defaults.has_3dlut = 1, \ > .__runtime_defaults.has_dmc = 1, \ > .__runtime_defaults.has_dsc = 1, \ > .__runtime_defaults.has_hdcp = 1, \ > @@ -1345,6 +1346,7 @@ static const struct platform_desc dg2_desc = { > > static const struct intel_display_device_info xe_lpdp_display = { > XE_LPDP_FEATURES, > + .__runtime_defaults.has_3dlut = 0, There's no need to initialize to 0. > }; > > static const struct intel_display_device_info xe2_lpd_display = { > @@ -1385,6 +1387,7 @@ static const struct intel_display_device_info xe2_hpd_display = { > XE_LPDP_FEATURES, > .__runtime_defaults.port_mask = BIT(PORT_A) | > BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), > + .__runtime_defaults.has_3dlut = 0, Ditto. > }; > > static const u16 mtl_u_ids[] = { > @@ -1935,6 +1938,10 @@ static void __intel_display_device_info_runtime_init(struct intel_display *displ > if (DISPLAY_VER(display) >= 20) { > u32 cap = intel_de_read(display, XE2LPD_DE_CAP); > > + if (REG_FIELD_GET(XE2LPD_DE_CAP_3DLUT_MASK, cap) == > + XE2LPD_DE_CAP_3DLUT_REMOVED) > + display_runtime->has_3dlut = 0; > + > if (REG_FIELD_GET(XE2LPD_DE_CAP_DSC_MASK, cap) == > XE2LPD_DE_CAP_DSC_REMOVED) > display_runtime->has_dsc = 0; > @@ -1996,6 +2003,7 @@ void intel_display_device_info_print(const struct intel_display_device_info *inf > DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); > #undef PRINT_FLAG > > + drm_printf(p, "has_3dlut: %s\n", str_yes_no(runtime->has_3dlut)); > drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp)); > drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc)); > drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc)); > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h > index 7121e7cd9512..34ee7993be33 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_device.h > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h > @@ -147,6 +147,9 @@ struct intel_display_platforms { > > #define HAS_128B_Y_TILING(__display) (!(__display)->platform.i915g && !(__display)->platform.i915gm) > #define HAS_2PPC(__display) (DISPLAY_VER(__display) >= 10) > +#define HAS_3DLUT_HW(__display) (DISPLAY_VER(__display) >= 10) > +#define HAS_3DLUT_CAP(__display) (IS_DISPLAY_VER(__display, 10, 20) || DISPLAY_RUNTIME_INFO(__display)->has_3dlut) I don't understand the difference between "HW" and "CAP" or the need for both. It's generally better to either use the runtime info flag or the display version check, not both. > +#define HAS_3DLUT(__display) (HAS_3DLUT_HW(__display) && HAS_3DLUT_CAP(__display)) > #define HAS_4TILE(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14) > #define HAS_ASYNC_FLIPS(__display) (DISPLAY_VER(__display) >= 5) > #define HAS_AS_SDP(__display) (DISPLAY_VER(__display) >= 13) > @@ -304,6 +307,7 @@ struct intel_display_runtime_info { > > u8 fbc_mask; > > + bool has_3dlut; > bool has_hdcp; > bool has_dmc; > bool has_dsc; > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h > index 0677ca2dde00..7b2332e2fae2 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h > @@ -1773,6 +1773,7 @@ > > #define XE2LPD_DE_CAP _MMIO(0x41100) > #define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30) > +#define XE2LPD_DE_CAP_3DLUT_REMOVED 1 > #define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28) > #define XE2LPD_DE_CAP_DSC_REMOVED 1 > #define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26) -- Jani Nikula, Intel ^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ i915.CI.BAT: failure for drm/i915/display: SKL_DSSM / DE_CAP fixes 2026-07-27 22:21 [PATCH v1 0/2] drm/i915/display: SKL_DSSM / DE_CAP fixes Michał Grzelak 2026-07-27 22:21 ` [PATCH v1 1/2] drm/i915/display: fix SKL_DSSM register masks Michał Grzelak 2026-07-27 22:21 ` [PATCH v1 2/2] drm/i915/xe2lpd+: disable 3D LUT if unsupported Michał Grzelak @ 2026-07-27 23:04 ` Patchwork 2 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2026-07-27 23:04 UTC (permalink / raw) To: Michał Grzelak; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 7027 bytes --] == Series Details == Series: drm/i915/display: SKL_DSSM / DE_CAP fixes URL : https://patchwork.freedesktop.org/series/171137/ State : failure == Summary == CI Bug Log - changes from CI_DRM_18909 -> Patchwork_171137v1 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_171137v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_171137v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171137v1/index.html Participating hosts (41 -> 39) ------------------------------ Missing (2): bat-dg2-13 fi-snb-2520m Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_171137v1: ### IGT changes ### #### Possible regressions #### * igt@i915_module_load@load: - bat-adlp-6: [PASS][1] -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18909/bat-adlp-6/igt@i915_module_load@load.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171137v1/bat-adlp-6/igt@i915_module_load@load.html - bat-arlh-2: [PASS][3] -> [ABORT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18909/bat-arlh-2/igt@i915_module_load@load.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171137v1/bat-arlh-2/igt@i915_module_load@load.html - bat-arlh-3: [PASS][5] -> [ABORT][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18909/bat-arlh-3/igt@i915_module_load@load.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171137v1/bat-arlh-3/igt@i915_module_load@load.html - bat-dg1-7: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18909/bat-dg1-7/igt@i915_module_load@load.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171137v1/bat-dg1-7/igt@i915_module_load@load.html - bat-adlp-9: [PASS][9] -> [ABORT][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18909/bat-adlp-9/igt@i915_module_load@load.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171137v1/bat-adlp-9/igt@i915_module_load@load.html - bat-twl-2: [PASS][11] -> [ABORT][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18909/bat-twl-2/igt@i915_module_load@load.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171137v1/bat-twl-2/igt@i915_module_load@load.html - bat-rpls-4: [PASS][13] -> [ABORT][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18909/bat-rpls-4/igt@i915_module_load@load.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171137v1/bat-rpls-4/igt@i915_module_load@load.html - bat-twl-1: [PASS][15] -> [ABORT][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18909/bat-twl-1/igt@i915_module_load@load.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171137v1/bat-twl-1/igt@i915_module_load@load.html - bat-jsl-5: [PASS][17] -> [ABORT][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18909/bat-jsl-5/igt@i915_module_load@load.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171137v1/bat-jsl-5/igt@i915_module_load@load.html - bat-rplp-1: [PASS][19] -> [ABORT][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18909/bat-rplp-1/igt@i915_module_load@load.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171137v1/bat-rplp-1/igt@i915_module_load@load.html - fi-tgl-1115g4: [PASS][21] -> [ABORT][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18909/fi-tgl-1115g4/igt@i915_module_load@load.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171137v1/fi-tgl-1115g4/igt@i915_module_load@load.html - bat-mtlp-9: [PASS][23] -> [ABORT][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18909/bat-mtlp-9/igt@i915_module_load@load.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171137v1/bat-mtlp-9/igt@i915_module_load@load.html - bat-arls-6: [PASS][25] -> [ABORT][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18909/bat-arls-6/igt@i915_module_load@load.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171137v1/bat-arls-6/igt@i915_module_load@load.html - bat-adlp-11: [PASS][27] -> [ABORT][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18909/bat-adlp-11/igt@i915_module_load@load.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171137v1/bat-adlp-11/igt@i915_module_load@load.html - bat-mtlp-8: [PASS][29] -> [ABORT][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18909/bat-mtlp-8/igt@i915_module_load@load.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171137v1/bat-mtlp-8/igt@i915_module_load@load.html - bat-dg1-6: [PASS][31] -> [ABORT][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18909/bat-dg1-6/igt@i915_module_load@load.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171137v1/bat-dg1-6/igt@i915_module_load@load.html - bat-adls-6: [PASS][33] -> [ABORT][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18909/bat-adls-6/igt@i915_module_load@load.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171137v1/bat-adls-6/igt@i915_module_load@load.html Known issues ------------ Here are the changes found in Patchwork_171137v1 that come from known issues: ### IGT changes ### #### Possible fixes #### * igt@i915_selftest@live: - fi-bsw-n3050: [ABORT][35] ([i915#16562]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18909/fi-bsw-n3050/igt@i915_selftest@live.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171137v1/fi-bsw-n3050/igt@i915_selftest@live.html * igt@i915_selftest@live@hangcheck: - fi-bsw-n3050: [ABORT][37] ([i915#16633]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18909/fi-bsw-n3050/igt@i915_selftest@live@hangcheck.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171137v1/fi-bsw-n3050/igt@i915_selftest@live@hangcheck.html [i915#16562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16562 [i915#16633]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16633 Build changes ------------- * Linux: CI_DRM_18909 -> Patchwork_171137v1 CI-20190529: 20190529 CI_DRM_18909: 28e3f47d47a61b5e28e7566944479e9c9715d41d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_9027: 9027 Patchwork_171137v1: 28e3f47d47a61b5e28e7566944479e9c9715d41d @ git://anongit.freedesktop.org/gfx-ci/linux == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171137v1/index.html [-- Attachment #2: Type: text/html, Size: 7760 bytes --] ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-07-28 7:44 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-07-27 22:21 [PATCH v1 0/2] drm/i915/display: SKL_DSSM / DE_CAP fixes Michał Grzelak 2026-07-27 22:21 ` [PATCH v1 1/2] drm/i915/display: fix SKL_DSSM register masks Michał Grzelak 2026-07-28 7:44 ` Jani Nikula 2026-07-27 22:21 ` [PATCH v1 2/2] drm/i915/xe2lpd+: disable 3D LUT if unsupported Michał Grzelak 2026-07-28 7:42 ` Jani Nikula 2026-07-27 23:04 ` ✗ i915.CI.BAT: failure for drm/i915/display: SKL_DSSM / DE_CAP fixes Patchwork
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