From: John Harrison <john.c.harrison@intel.com>
To: "Teres Alexis, Alan Previn" <alan.previn.teres.alexis@intel.com>,
"Intel-GFX@Lists.FreeDesktop.Org"
<Intel-GFX@Lists.FreeDesktop.Org>
Cc: "DRI-Devel@Lists.FreeDesktop.Org" <DRI-Devel@Lists.FreeDesktop.Org>
Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915/guc: Clean up of register capture search
Date: Mon, 6 Feb 2023 19:18:33 -0800 [thread overview]
Message-ID: <e4060930-b631-39dc-d04d-c51a7680d096@intel.com> (raw)
In-Reply-To: <3b2ef1cbe2eea5c13da72feec8fc2bb9d3cc5ec1.camel@intel.com>
On 2/3/2023 23:29, Teres Alexis, Alan Previn wrote:
> I see you are inferring that a guc-id of zero can be valid.
> I am guessing that might have contributed to some lost captures?
> Thanks for catching this.
I'm not inferring anything. I might be implying something, though. The
patch description probably should have mentioned that change. I'll add
something in.
There is nothing special about id zero. The lower X many ids are
reserved for multi-LRC use. So you won't see zero being allocated
normally. But run a multi-LRC app/test and the first context allocated
should be id zero.
John.
>
> Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>
>
> On Thu, 2023-02-02 at 17:10 -0800, John.C.Harrison@Intel.com wrote:
>> From: John Harrison <John.C.Harrison@Intel.com>
>>
>> The comparison in the search for a matching register capture node was
>> not the most readable. So remove two redundant terms and re-format to
>> keep each term on a single line, and only one term per line.
>>
>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 5 ++---
>> 1 file changed, 2 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
>> index 710999d7189ee..87b080dd6bead 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
>> @@ -1627,9 +1627,8 @@ void intel_guc_capture_get_matching_node(struct intel_gt *gt,
>> list_for_each_entry_safe(n, ntmp, &guc->capture->outlist, link) {
>> if (n->eng_inst == GUC_ID_TO_ENGINE_INSTANCE(ee->engine->guc_id) &&
>> n->eng_class == GUC_ID_TO_ENGINE_CLASS(ee->engine->guc_id) &&
>> - n->guc_id && n->guc_id == ce->guc_id.id &&
>> - (n->lrca & CTX_GTT_ADDRESS_MASK) && (n->lrca & CTX_GTT_ADDRESS_MASK) ==
>> - (ce->lrc.lrca & CTX_GTT_ADDRESS_MASK)) {
>> + n->guc_id == ce->guc_id.id &&
>> + (n->lrca & CTX_GTT_ADDRESS_MASK) == (ce->lrc.lrca & CTX_GTT_ADDRESS_MASK)) {
>> list_del(&n->link);
>> ee->guc_capture_node = n;
>> ee->guc_capture = guc->capture;
next prev parent reply other threads:[~2023-02-07 3:18 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-03 1:10 [Intel-gfx] [PATCH 0/3] More error capture improvements John.C.Harrison
2023-02-03 1:10 ` [Intel-gfx] [PATCH 1/3] drm/i915/guc: Fix missing ecodes John.C.Harrison
2023-02-04 7:55 ` Teres Alexis, Alan Previn
2023-02-03 1:10 ` [Intel-gfx] [PATCH 2/3] drm/i915/guc: Clean up of register capture search John.C.Harrison
2023-02-04 7:29 ` Teres Alexis, Alan Previn
2023-02-07 3:18 ` John Harrison [this message]
2023-02-03 1:10 ` [Intel-gfx] [PATCH 3/3] drm/i915: Include timelines in error capture John.C.Harrison
2023-02-03 2:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for More error capture improvements Patchwork
2023-02-03 12:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-02-03 16:41 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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