From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Cc: matthew.auld@intel.com
Subject: Re: [Intel-gfx] [PATCH 1/6] drm/i915: Hold reference to previous active fence as we queue
Date: Mon, 3 Feb 2020 10:50:17 +0000 [thread overview]
Message-ID: <e4f36606-dff0-f65b-c225-8522e192d54e@linux.intel.com> (raw)
In-Reply-To: <20200203094152.4150550-1-chris@chris-wilson.co.uk>
On 03/02/2020 09:41, Chris Wilson wrote:
> Take a reference to the previous exclusive fence on the i915_active, as
> we wish to add an await to it in the caller (and so must prevent it from
> being freed until we have completed that task).
>
> Fixes: e3793468b466 ("drm/i915: Use the async worker to avoid reclaim tainting the ggtt->mutex")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Matthew Auld <matthew.auld@intel.com>
> ---
> drivers/gpu/drm/i915/i915_active.c | 6 +++++-
> drivers/gpu/drm/i915/i915_vma.c | 4 +++-
> 2 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_active.c b/drivers/gpu/drm/i915/i915_active.c
> index da58e5d084f4..9ccb931a733e 100644
> --- a/drivers/gpu/drm/i915/i915_active.c
> +++ b/drivers/gpu/drm/i915/i915_active.c
> @@ -398,9 +398,13 @@ i915_active_set_exclusive(struct i915_active *ref, struct dma_fence *f)
> /* We expect the caller to manage the exclusive timeline ordering */
> GEM_BUG_ON(i915_active_is_idle(ref));
>
> + rcu_read_lock();
> prev = __i915_active_fence_set(&ref->excl, f);
> - if (!prev)
> + if (prev)
> + prev = dma_fence_get_rcu(prev);
> + else
> atomic_inc(&ref->count);
> + rcu_read_unlock();
>
> return prev;
> }
> diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> index e801e28de470..74dc3ba59ce5 100644
> --- a/drivers/gpu/drm/i915/i915_vma.c
> +++ b/drivers/gpu/drm/i915/i915_vma.c
> @@ -422,10 +422,12 @@ int i915_vma_bind(struct i915_vma *vma,
> * execution and not content or object's backing store lifetime.
> */
> prev = i915_active_set_exclusive(&vma->active, &work->base.dma);
> - if (prev)
> + if (prev) {
> __i915_sw_fence_await_dma_fence(&work->base.chain,
> prev,
> &work->cb);
> + dma_fence_put(prev);
> + }
>
> work->base.dma.error = 0; /* enable the queue_work() */
>
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
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next prev parent reply other threads:[~2020-02-03 10:50 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-03 9:41 [Intel-gfx] [PATCH 1/6] drm/i915: Hold reference to previous active fence as we queue Chris Wilson
2020-02-03 9:41 ` [Intel-gfx] [PATCH 2/6] drm/i915: Initialise basic fence before acquiring seqno Chris Wilson
2020-02-03 10:55 ` Tvrtko Ursulin
2020-02-03 10:58 ` Chris Wilson
2020-02-03 11:02 ` Tvrtko Ursulin
2020-02-03 9:41 ` [Intel-gfx] [PATCH 3/6] drm/i915/gt: Warn about the hidden i915_vma_pin in timeline_get_seqno Chris Wilson
2020-02-03 9:41 ` [Intel-gfx] [PATCH 4/6] drm/i915/selftests: Add a simple rollover for the kernel context Chris Wilson
2020-02-03 17:32 ` Matthew Auld
2020-02-03 17:37 ` Chris Wilson
2020-02-03 9:41 ` [Intel-gfx] [PATCH 5/6] drm/i915: Flush execution tasklets before checking request status Chris Wilson
2020-02-03 9:41 ` [Intel-gfx] [PATCH 6/6] drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore Chris Wilson
2020-02-03 10:50 ` Tvrtko Ursulin [this message]
2020-02-03 11:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Hold reference to previous active fence as we queue Patchwork
2020-02-05 17:55 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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