From: "Teres Alexis, Alan Previn" <alan.previn.teres.alexis@intel.com>
To: "tvrtko.ursulin@linux.intel.com" <tvrtko.ursulin@linux.intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/guc: Add compute reglist for GuC error capture
Date: Mon, 17 Oct 2022 17:32:38 +0000 [thread overview]
Message-ID: <f1b85264b22665387aecce6b5891b6c138af3dbb.camel@intel.com> (raw)
In-Reply-To: <fb41a0fb-232e-a3b6-5fc6-6317298f89b5@linux.intel.com>
ADL-P doesnt support CCS and DG2 is stll force-probe (so hoping to get this before DG2 goes live).
...alan
On Mon, 2022-10-17 at 09:43 +0100, Tvrtko Ursulin wrote:
> On 15/10/2022 04:59, Alan Previn wrote:
> > Add compute reglist for GuC error capture.
> >
> > Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> > index 290c1e1343dd..da3a09c11d12 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> > @@ -169,6 +169,8 @@ static struct __guc_mmio_reg_descr_group default_lists[] = {
> > MAKE_REGLIST(default_global_regs, PF, GLOBAL, 0),
> > MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS),
> > MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS),
> > + MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS, GUC_COMPUTE_CLASS),
> > + MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_COMPUTE_CLASS),
>
> Does this means error capture on ADL-P was incomplete aka should
> something be sent to stable?
>
> Regards,
>
> Tvrtko
>
> > MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS),
> > MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS),
> > MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS),
> > @@ -182,6 +184,8 @@ static const struct __guc_mmio_reg_descr_group xe_lpd_lists[] = {
> > MAKE_REGLIST(xe_lpd_global_regs, PF, GLOBAL, 0),
> > MAKE_REGLIST(xe_lpd_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS),
> > MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS),
> > + MAKE_REGLIST(xe_lpd_rc_class_regs, PF, ENGINE_CLASS, GUC_COMPUTE_CLASS),
> > + MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_COMPUTE_CLASS),
> > MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS),
> > MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS),
> > MAKE_REGLIST(xe_lpd_vec_class_regs, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS),
next prev parent reply other threads:[~2022-10-17 17:32 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-15 3:59 [Intel-gfx] [PATCH 0/2] drm/i915/guc: Add GuC-Error-Capture-Init coverage of new engine types Alan Previn
2022-10-15 3:59 ` [Intel-gfx] [PATCH 1/2] drm/i915/guc: Add error-capture init warnings when needed Alan Previn
2022-10-17 8:42 ` Tvrtko Ursulin
2022-10-17 17:46 ` Teres Alexis, Alan Previn
2022-10-18 8:00 ` Tvrtko Ursulin
2022-10-19 5:14 ` Teres Alexis, Alan Previn
2022-10-19 5:28 ` Teres Alexis, Alan Previn
2022-10-17 19:33 ` John Harrison
2022-10-17 23:36 ` Teres Alexis, Alan Previn
2022-10-18 0:15 ` John Harrison
2022-10-15 3:59 ` [Intel-gfx] [PATCH 2/2] drm/i915/guc: Add compute reglist for GuC error capture Alan Previn
2022-10-17 8:43 ` Tvrtko Ursulin
2022-10-17 17:32 ` Teres Alexis, Alan Previn [this message]
2022-10-18 8:04 ` Tvrtko Ursulin
2022-10-15 4:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Add GuC-Error-Capture-Init coverage of new engine types Patchwork
2022-10-15 6:24 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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