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From: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
To: "Christian König" <christian.koenig@amd.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>,
	Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
	DRI Development <dri-devel@lists.freedesktop.org>
Subject: [Intel-gfx] Sparsely populated TTM bos
Date: Fri, 19 Nov 2021 15:28:30 +0100	[thread overview]
Message-ID: <f73304f7-6ada-bcd2-97b3-c7898cbd166c@linux.intel.com> (raw)

Hi, Christian,

We have an upcoming use-case in i915 where one solution would be 
sparsely populated TTM bos.

We had that at one point where ttm_tt pages were allocated on demand, 
but this time we'd rather be looking at multiple struct ttm_resources 
per bo and those resources could be from different managers.

There might theoretically be other ways we can handle this use-case but 
I wanted to check with you whether this is something AMD is already 
looking into and if not, your general opinion.

Thanks,
Thomas



             reply	other threads:[~2021-11-19 14:28 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-19 14:28 Thomas Hellström [this message]
2021-11-19 16:35 ` [Intel-gfx] Sparsely populated TTM bos Christian König
2021-11-19 17:06   ` Daniel Vetter

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