Re: [Intel-gfx] [PATCH 1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines

[Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>]

On 07/12/2022 17:36, Andrzej Hajda wrote:
> In case of Gen12.50 video and compute engines, TLB_INV registers are
> masked - to modify one bit, corresponding bit in upper half of the register
> must be enabled, otherwise nothing happens.
> 
> Fixes: 77fa9efc16a9 ("drm/i915/xehp: Create separate reg definitions for new MCR registers")

Just a note that target wasn't strictly the only one to blame, but it is 
a good target to ensure proper backporting.

> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
> ---
> This patch is simple enhancement of
> 04aa64375f48 ("drm/i915: fix TLB invalidation for Gen12 video and compute engines")
> for Gen12.5 which is added in dev branches.
> ---
>   drivers/gpu/drm/i915/gt/intel_gt.c | 8 +++++++-
>   1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index d114347c004ee5..f0224b607aa4a7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -1120,9 +1120,15 @@ static void mmio_invalidate_full(struct intel_gt *gt)
>   			continue;
>   
>   		if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
> +			u32 val = BIT(engine->instance);
> +
> +			if (engine->class == VIDEO_DECODE_CLASS ||
> +			    engine->class == VIDEO_ENHANCEMENT_CLASS ||
> +			    engine->class == COMPUTE_CLASS)
> +				val = _MASKED_BIT_ENABLE(val);
>   			intel_gt_mcr_multicast_write_fw(gt,
>   							xehp_regs[engine->class],
> -							BIT(engine->instance));
> +							val);
>   		} else {
>   			rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
>   			if (!i915_mmio_reg_offset(rb.reg))

Triple checked against bspec.

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko