* [Intel-gfx] [PATCH 1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines
@ 2022-12-07 17:36 Andrzej Hajda
2022-12-07 17:36 ` [Intel-gfx] [PATCH 2/2] drm/i915: cleanup TLB invalidation code Andrzej Hajda
` (7 more replies)
0 siblings, 8 replies; 15+ messages in thread
From: Andrzej Hajda @ 2022-12-07 17:36 UTC (permalink / raw)
To: intel-gfx
Cc: Chris Wilson, Matthew Auld, Andrzej Hajda, Rodrigo Vivi,
Daniel Vetter, Nirmoy Das
In case of Gen12.50 video and compute engines, TLB_INV registers are
masked - to modify one bit, corresponding bit in upper half of the register
must be enabled, otherwise nothing happens.
Fixes: 77fa9efc16a9 ("drm/i915/xehp: Create separate reg definitions for new MCR registers")
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
This patch is simple enhancement of
04aa64375f48 ("drm/i915: fix TLB invalidation for Gen12 video and compute engines")
for Gen12.5 which is added in dev branches.
---
drivers/gpu/drm/i915/gt/intel_gt.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index d114347c004ee5..f0224b607aa4a7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1120,9 +1120,15 @@ static void mmio_invalidate_full(struct intel_gt *gt)
continue;
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+ u32 val = BIT(engine->instance);
+
+ if (engine->class == VIDEO_DECODE_CLASS ||
+ engine->class == VIDEO_ENHANCEMENT_CLASS ||
+ engine->class == COMPUTE_CLASS)
+ val = _MASKED_BIT_ENABLE(val);
intel_gt_mcr_multicast_write_fw(gt,
xehp_regs[engine->class],
- BIT(engine->instance));
+ val);
} else {
rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
if (!i915_mmio_reg_offset(rb.reg))
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [Intel-gfx] [PATCH 2/2] drm/i915: cleanup TLB invalidation code 2022-12-07 17:36 [Intel-gfx] [PATCH 1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines Andrzej Hajda @ 2022-12-07 17:36 ` Andrzej Hajda 2022-12-09 10:16 ` Tvrtko Ursulin 2022-12-07 20:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines Patchwork ` (6 subsequent siblings) 7 siblings, 1 reply; 15+ messages in thread From: Andrzej Hajda @ 2022-12-07 17:36 UTC (permalink / raw) To: intel-gfx Cc: Chris Wilson, Matthew Auld, Andrzej Hajda, Rodrigo Vivi, Daniel Vetter, Nirmoy Das Whole register/bit selection logic has been moved to separate helper. Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt.c | 136 +++++++++++------------------ 1 file changed, 51 insertions(+), 85 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index f0224b607aa4a7..05520ec3264db8 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -1003,32 +1003,59 @@ void intel_gt_info_print(const struct intel_gt_info *info, intel_sseu_dump(&info->sseu, p); } -struct reg_and_bit { +struct reg_and_bits { union { i915_reg_t reg; i915_mcr_reg_t mcr_reg; }; - u32 bit; + u32 bits; }; -static struct reg_and_bit -get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8, - const i915_reg_t *regs, const unsigned int num) +static struct reg_and_bits +get_tlb_inv_reg_and_bits(const struct intel_engine_cs *engine, bool write) { + static const i915_reg_t gen8_regs[MAX_ENGINE_CLASS + 1] = { + [RENDER_CLASS] = GEN8_RTCR, + [VIDEO_DECODE_CLASS] = GEN8_M1TCR, + [VIDEO_ENHANCEMENT_CLASS] = GEN8_VTCR, + [COPY_ENGINE_CLASS] = GEN8_BTCR, + }; + static const i915_reg_t gen12_regs[MAX_ENGINE_CLASS + 1] = { + [RENDER_CLASS] = GEN12_GFX_TLB_INV_CR, + [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, + [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, + [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR, + [COMPUTE_CLASS] = GEN12_COMPCTX_TLB_INV_CR, + }; + static const i915_mcr_reg_t xehp_regs[MAX_ENGINE_CLASS + 1] = { + [RENDER_CLASS] = XEHP_GFX_TLB_INV_CR, + [VIDEO_DECODE_CLASS] = XEHP_VD_TLB_INV_CR, + [VIDEO_ENHANCEMENT_CLASS] = XEHP_VE_TLB_INV_CR, + [COPY_ENGINE_CLASS] = XEHP_BLT_TLB_INV_CR, + [COMPUTE_CLASS] = XEHP_COMPCTX_TLB_INV_CR, + }; const unsigned int class = engine->class; - struct reg_and_bit rb = { }; + struct reg_and_bits rb = { .bits = BIT(engine->instance) }; - if (drm_WARN_ON_ONCE(&engine->i915->drm, - class >= num || !regs[class].reg)) + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) + rb.mcr_reg = xehp_regs[class]; + else if (GRAPHICS_VER(engine->i915) >= 12) + rb.reg = gen12_regs[class]; + else if (GRAPHICS_VER(engine->i915) >= 8) + rb.reg = gen8_regs[class]; + + if (drm_WARN_ON_ONCE(&engine->i915->drm, !i915_mmio_reg_offset(rb.reg))) return rb; - rb.reg = regs[class]; - if (gen8 && class == VIDEO_DECODE_CLASS) - rb.reg.reg += 4 * engine->instance; /* GEN8_M2TCR */ - else - rb.bit = engine->instance; + if (GRAPHICS_VER(engine->i915) < 12 && class == VIDEO_DECODE_CLASS) { + rb.bits = 1; + rb.reg.reg += 4 * engine->instance; + } - rb.bit = BIT(rb.bit); + if (write && GRAPHICS_VER(engine->i915) >= 12 && + (class == VIDEO_DECODE_CLASS || class == VIDEO_ENHANCEMENT_CLASS || + class == COMPUTE_CLASS)) + rb.bits = _MASKED_BIT_ENABLE(rb.bits); return rb; } @@ -1046,14 +1073,14 @@ get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8, * but are now considered MCR registers. Since they exist within a GAM range, * the primary instance of the register rolls up the status from each unit. */ -static int wait_for_invalidate(struct intel_gt *gt, struct reg_and_bit rb) +static int wait_for_invalidate(struct intel_gt *gt, struct reg_and_bits rb) { if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) - return intel_gt_mcr_wait_for_reg(gt, rb.mcr_reg, rb.bit, 0, + return intel_gt_mcr_wait_for_reg(gt, rb.mcr_reg, rb.bits, 0, TLB_INVAL_TIMEOUT_US, TLB_INVAL_TIMEOUT_MS); else - return __intel_wait_for_register_fw(gt->uncore, rb.reg, rb.bit, 0, + return __intel_wait_for_register_fw(gt->uncore, rb.reg, rb.bits, 0, TLB_INVAL_TIMEOUT_US, TLB_INVAL_TIMEOUT_MS, NULL); @@ -1061,50 +1088,14 @@ static int wait_for_invalidate(struct intel_gt *gt, struct reg_and_bit rb) static void mmio_invalidate_full(struct intel_gt *gt) { - static const i915_reg_t gen8_regs[] = { - [RENDER_CLASS] = GEN8_RTCR, - [VIDEO_DECODE_CLASS] = GEN8_M1TCR, /* , GEN8_M2TCR */ - [VIDEO_ENHANCEMENT_CLASS] = GEN8_VTCR, - [COPY_ENGINE_CLASS] = GEN8_BTCR, - }; - static const i915_reg_t gen12_regs[] = { - [RENDER_CLASS] = GEN12_GFX_TLB_INV_CR, - [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, - [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, - [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR, - [COMPUTE_CLASS] = GEN12_COMPCTX_TLB_INV_CR, - }; - static const i915_mcr_reg_t xehp_regs[] = { - [RENDER_CLASS] = XEHP_GFX_TLB_INV_CR, - [VIDEO_DECODE_CLASS] = XEHP_VD_TLB_INV_CR, - [VIDEO_ENHANCEMENT_CLASS] = XEHP_VE_TLB_INV_CR, - [COPY_ENGINE_CLASS] = XEHP_BLT_TLB_INV_CR, - [COMPUTE_CLASS] = XEHP_COMPCTX_TLB_INV_CR, - }; struct drm_i915_private *i915 = gt->i915; struct intel_uncore *uncore = gt->uncore; struct intel_engine_cs *engine; intel_engine_mask_t awake, tmp; enum intel_engine_id id; - const i915_reg_t *regs; - unsigned int num = 0; unsigned long flags; - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { - regs = NULL; - num = ARRAY_SIZE(xehp_regs); - } else if (GRAPHICS_VER(i915) == 12) { - regs = gen12_regs; - num = ARRAY_SIZE(gen12_regs); - } else if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) <= 11) { - regs = gen8_regs; - num = ARRAY_SIZE(gen8_regs); - } else if (GRAPHICS_VER(i915) < 8) { - return; - } - - if (drm_WARN_ONCE(&i915->drm, !num, - "Platform does not implement TLB invalidation!")) + if (GRAPHICS_VER(i915) < 8) return; intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); @@ -1114,33 +1105,15 @@ static void mmio_invalidate_full(struct intel_gt *gt) awake = 0; for_each_engine(engine, gt, id) { - struct reg_and_bit rb; + struct reg_and_bits rb = get_tlb_inv_reg_and_bits(engine, true); if (!intel_engine_pm_is_awake(engine)) continue; - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { - u32 val = BIT(engine->instance); - - if (engine->class == VIDEO_DECODE_CLASS || - engine->class == VIDEO_ENHANCEMENT_CLASS || - engine->class == COMPUTE_CLASS) - val = _MASKED_BIT_ENABLE(val); - intel_gt_mcr_multicast_write_fw(gt, - xehp_regs[engine->class], - val); - } else { - rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); - if (!i915_mmio_reg_offset(rb.reg)) - continue; - - if (GRAPHICS_VER(i915) == 12 && (engine->class == VIDEO_DECODE_CLASS || - engine->class == VIDEO_ENHANCEMENT_CLASS || - engine->class == COMPUTE_CLASS)) - rb.bit = _MASKED_BIT_ENABLE(rb.bit); - - intel_uncore_write_fw(uncore, rb.reg, rb.bit); - } + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) + intel_gt_mcr_multicast_write_fw(gt, rb.mcr_reg, rb.bits); + else + intel_uncore_write_fw(uncore, rb.reg, rb.bits); awake |= engine->mask; } @@ -1159,14 +1132,7 @@ static void mmio_invalidate_full(struct intel_gt *gt) intel_gt_mcr_unlock(gt, flags); for_each_engine_masked(engine, gt, awake, tmp) { - struct reg_and_bit rb; - - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { - rb.mcr_reg = xehp_regs[engine->class]; - rb.bit = BIT(engine->instance); - } else { - rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); - } + struct reg_and_bits rb = get_tlb_inv_reg_and_bits(engine, false); if (wait_for_invalidate(gt, rb)) drm_err_ratelimited(>->i915->drm, -- 2.34.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915: cleanup TLB invalidation code 2022-12-07 17:36 ` [Intel-gfx] [PATCH 2/2] drm/i915: cleanup TLB invalidation code Andrzej Hajda @ 2022-12-09 10:16 ` Tvrtko Ursulin 2022-12-09 11:33 ` Andrzej Hajda 0 siblings, 1 reply; 15+ messages in thread From: Tvrtko Ursulin @ 2022-12-09 10:16 UTC (permalink / raw) To: Andrzej Hajda, intel-gfx Cc: Chris Wilson, Daniel Vetter, Matthew Auld, Rodrigo Vivi, Nirmoy Das On 07/12/2022 17:36, Andrzej Hajda wrote: > Whole register/bit selection logic has been moved to separate helper. Why is missing. > Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt.c | 136 +++++++++++------------------ > 1 file changed, 51 insertions(+), 85 deletions(-) Diffstat suggests because more streamlined code. Any other reason? > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c > index f0224b607aa4a7..05520ec3264db8 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > @@ -1003,32 +1003,59 @@ void intel_gt_info_print(const struct intel_gt_info *info, > intel_sseu_dump(&info->sseu, p); > } > > -struct reg_and_bit { > +struct reg_and_bits { > union { > i915_reg_t reg; > i915_mcr_reg_t mcr_reg; > }; > - u32 bit; > + u32 bits; > }; > > -static struct reg_and_bit > -get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8, > - const i915_reg_t *regs, const unsigned int num) > +static struct reg_and_bits > +get_tlb_inv_reg_and_bits(const struct intel_engine_cs *engine, bool write) > { > + static const i915_reg_t gen8_regs[MAX_ENGINE_CLASS + 1] = { > + [RENDER_CLASS] = GEN8_RTCR, > + [VIDEO_DECODE_CLASS] = GEN8_M1TCR, > + [VIDEO_ENHANCEMENT_CLASS] = GEN8_VTCR, > + [COPY_ENGINE_CLASS] = GEN8_BTCR, > + }; > + static const i915_reg_t gen12_regs[MAX_ENGINE_CLASS + 1] = { > + [RENDER_CLASS] = GEN12_GFX_TLB_INV_CR, > + [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, > + [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, > + [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR, > + [COMPUTE_CLASS] = GEN12_COMPCTX_TLB_INV_CR, > + }; > + static const i915_mcr_reg_t xehp_regs[MAX_ENGINE_CLASS + 1] = { > + [RENDER_CLASS] = XEHP_GFX_TLB_INV_CR, > + [VIDEO_DECODE_CLASS] = XEHP_VD_TLB_INV_CR, > + [VIDEO_ENHANCEMENT_CLASS] = XEHP_VE_TLB_INV_CR, > + [COPY_ENGINE_CLASS] = XEHP_BLT_TLB_INV_CR, > + [COMPUTE_CLASS] = XEHP_COMPCTX_TLB_INV_CR, > + }; > const unsigned int class = engine->class; > - struct reg_and_bit rb = { }; > + struct reg_and_bits rb = { .bits = BIT(engine->instance) }; > > - if (drm_WARN_ON_ONCE(&engine->i915->drm, > - class >= num || !regs[class].reg)) > + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) > + rb.mcr_reg = xehp_regs[class]; > + else if (GRAPHICS_VER(engine->i915) >= 12) > + rb.reg = gen12_regs[class]; > + else if (GRAPHICS_VER(engine->i915) >= 8) > + rb.reg = gen8_regs[class]; > + > + if (drm_WARN_ON_ONCE(&engine->i915->drm, !i915_mmio_reg_offset(rb.reg))) I'd prefer user readable message was kept but not a blocker. > return rb; > > - rb.reg = regs[class]; > - if (gen8 && class == VIDEO_DECODE_CLASS) > - rb.reg.reg += 4 * engine->instance; /* GEN8_M2TCR */ > - else > - rb.bit = engine->instance; > + if (GRAPHICS_VER(engine->i915) < 12 && class == VIDEO_DECODE_CLASS) { > + rb.bits = 1; > + rb.reg.reg += 4 * engine->instance; No reason to drop the comment IMO. It explains things somewhat, or at least provides a hint. > + } > > - rb.bit = BIT(rb.bit); > + if (write && GRAPHICS_VER(engine->i915) >= 12 && > + (class == VIDEO_DECODE_CLASS || class == VIDEO_ENHANCEMENT_CLASS || > + class == COMPUTE_CLASS)) > + rb.bits = _MASKED_BIT_ENABLE(rb.bits); This could be else if to not have < 12 followed by explicit >= 12, but perhaps it is clearer like this, to signify it's two completely separate quirks. Also, I would perhaps consider having a local i915 since there's a good number of engine->i915, but it's up to you what looks nicer. > > return rb; > } > @@ -1046,14 +1073,14 @@ get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8, > * but are now considered MCR registers. Since they exist within a GAM range, > * the primary instance of the register rolls up the status from each unit. > */ > -static int wait_for_invalidate(struct intel_gt *gt, struct reg_and_bit rb) > +static int wait_for_invalidate(struct intel_gt *gt, struct reg_and_bits rb) > { > if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) > - return intel_gt_mcr_wait_for_reg(gt, rb.mcr_reg, rb.bit, 0, > + return intel_gt_mcr_wait_for_reg(gt, rb.mcr_reg, rb.bits, 0, > TLB_INVAL_TIMEOUT_US, > TLB_INVAL_TIMEOUT_MS); > else > - return __intel_wait_for_register_fw(gt->uncore, rb.reg, rb.bit, 0, > + return __intel_wait_for_register_fw(gt->uncore, rb.reg, rb.bits, 0, > TLB_INVAL_TIMEOUT_US, > TLB_INVAL_TIMEOUT_MS, > NULL); > @@ -1061,50 +1088,14 @@ static int wait_for_invalidate(struct intel_gt *gt, struct reg_and_bit rb) > > static void mmio_invalidate_full(struct intel_gt *gt) > { > - static const i915_reg_t gen8_regs[] = { > - [RENDER_CLASS] = GEN8_RTCR, > - [VIDEO_DECODE_CLASS] = GEN8_M1TCR, /* , GEN8_M2TCR */ > - [VIDEO_ENHANCEMENT_CLASS] = GEN8_VTCR, > - [COPY_ENGINE_CLASS] = GEN8_BTCR, > - }; > - static const i915_reg_t gen12_regs[] = { > - [RENDER_CLASS] = GEN12_GFX_TLB_INV_CR, > - [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, > - [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, > - [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR, > - [COMPUTE_CLASS] = GEN12_COMPCTX_TLB_INV_CR, > - }; > - static const i915_mcr_reg_t xehp_regs[] = { > - [RENDER_CLASS] = XEHP_GFX_TLB_INV_CR, > - [VIDEO_DECODE_CLASS] = XEHP_VD_TLB_INV_CR, > - [VIDEO_ENHANCEMENT_CLASS] = XEHP_VE_TLB_INV_CR, > - [COPY_ENGINE_CLASS] = XEHP_BLT_TLB_INV_CR, > - [COMPUTE_CLASS] = XEHP_COMPCTX_TLB_INV_CR, > - }; > struct drm_i915_private *i915 = gt->i915; > struct intel_uncore *uncore = gt->uncore; > struct intel_engine_cs *engine; > intel_engine_mask_t awake, tmp; > enum intel_engine_id id; > - const i915_reg_t *regs; > - unsigned int num = 0; > unsigned long flags; > > - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { > - regs = NULL; > - num = ARRAY_SIZE(xehp_regs); > - } else if (GRAPHICS_VER(i915) == 12) { > - regs = gen12_regs; > - num = ARRAY_SIZE(gen12_regs); > - } else if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) <= 11) { > - regs = gen8_regs; > - num = ARRAY_SIZE(gen8_regs); > - } else if (GRAPHICS_VER(i915) < 8) { > - return; > - } > - > - if (drm_WARN_ONCE(&i915->drm, !num, > - "Platform does not implement TLB invalidation!")) > + if (GRAPHICS_VER(i915) < 8) > return; > > intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); > @@ -1114,33 +1105,15 @@ static void mmio_invalidate_full(struct intel_gt *gt) > > awake = 0; > for_each_engine(engine, gt, id) { > - struct reg_and_bit rb; > + struct reg_and_bits rb = get_tlb_inv_reg_and_bits(engine, true); Ugh so actually what was a once per invalidation lookup is now repeated per engine, times two. I wonder if we can do this better. Lets think about it a bit. Regards, Tvrtko > > if (!intel_engine_pm_is_awake(engine)) > continue; > > - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { > - u32 val = BIT(engine->instance); > - > - if (engine->class == VIDEO_DECODE_CLASS || > - engine->class == VIDEO_ENHANCEMENT_CLASS || > - engine->class == COMPUTE_CLASS) > - val = _MASKED_BIT_ENABLE(val); > - intel_gt_mcr_multicast_write_fw(gt, > - xehp_regs[engine->class], > - val); > - } else { > - rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); > - if (!i915_mmio_reg_offset(rb.reg)) > - continue; > - > - if (GRAPHICS_VER(i915) == 12 && (engine->class == VIDEO_DECODE_CLASS || > - engine->class == VIDEO_ENHANCEMENT_CLASS || > - engine->class == COMPUTE_CLASS)) > - rb.bit = _MASKED_BIT_ENABLE(rb.bit); > - > - intel_uncore_write_fw(uncore, rb.reg, rb.bit); > - } > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) > + intel_gt_mcr_multicast_write_fw(gt, rb.mcr_reg, rb.bits); > + else > + intel_uncore_write_fw(uncore, rb.reg, rb.bits); > awake |= engine->mask; > } > > @@ -1159,14 +1132,7 @@ static void mmio_invalidate_full(struct intel_gt *gt) > intel_gt_mcr_unlock(gt, flags); > > for_each_engine_masked(engine, gt, awake, tmp) { > - struct reg_and_bit rb; > - > - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { > - rb.mcr_reg = xehp_regs[engine->class]; > - rb.bit = BIT(engine->instance); > - } else { > - rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); > - } > + struct reg_and_bits rb = get_tlb_inv_reg_and_bits(engine, false); > > if (wait_for_invalidate(gt, rb)) > drm_err_ratelimited(>->i915->drm, ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915: cleanup TLB invalidation code 2022-12-09 10:16 ` Tvrtko Ursulin @ 2022-12-09 11:33 ` Andrzej Hajda 2022-12-09 12:04 ` Tvrtko Ursulin 0 siblings, 1 reply; 15+ messages in thread From: Andrzej Hajda @ 2022-12-09 11:33 UTC (permalink / raw) To: Tvrtko Ursulin, intel-gfx Cc: Chris Wilson, Daniel Vetter, Matthew Auld, Rodrigo Vivi, Nirmoy Das On 09.12.2022 11:16, Tvrtko Ursulin wrote: > > On 07/12/2022 17:36, Andrzej Hajda wrote: >> Whole register/bit selection logic has been moved to separate helper. > > Why is missing. ...to clean up mmio_invalidate_full function. Will add. > >> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> >> --- >> drivers/gpu/drm/i915/gt/intel_gt.c | 136 +++++++++++------------------ >> 1 file changed, 51 insertions(+), 85 deletions(-) > > Diffstat suggests because more streamlined code. Any other reason? > >> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c >> b/drivers/gpu/drm/i915/gt/intel_gt.c >> index f0224b607aa4a7..05520ec3264db8 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_gt.c >> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c >> @@ -1003,32 +1003,59 @@ void intel_gt_info_print(const struct >> intel_gt_info *info, >> intel_sseu_dump(&info->sseu, p); >> } >> -struct reg_and_bit { >> +struct reg_and_bits { >> union { >> i915_reg_t reg; >> i915_mcr_reg_t mcr_reg; >> }; >> - u32 bit; >> + u32 bits; >> }; >> -static struct reg_and_bit >> -get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8, >> - const i915_reg_t *regs, const unsigned int num) >> +static struct reg_and_bits >> +get_tlb_inv_reg_and_bits(const struct intel_engine_cs *engine, bool >> write) >> { >> + static const i915_reg_t gen8_regs[MAX_ENGINE_CLASS + 1] = { >> + [RENDER_CLASS] = GEN8_RTCR, >> + [VIDEO_DECODE_CLASS] = GEN8_M1TCR, >> + [VIDEO_ENHANCEMENT_CLASS] = GEN8_VTCR, >> + [COPY_ENGINE_CLASS] = GEN8_BTCR, >> + }; >> + static const i915_reg_t gen12_regs[MAX_ENGINE_CLASS + 1] = { >> + [RENDER_CLASS] = GEN12_GFX_TLB_INV_CR, >> + [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, >> + [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, >> + [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR, >> + [COMPUTE_CLASS] = GEN12_COMPCTX_TLB_INV_CR, >> + }; >> + static const i915_mcr_reg_t xehp_regs[MAX_ENGINE_CLASS + 1] = { >> + [RENDER_CLASS] = XEHP_GFX_TLB_INV_CR, >> + [VIDEO_DECODE_CLASS] = XEHP_VD_TLB_INV_CR, >> + [VIDEO_ENHANCEMENT_CLASS] = XEHP_VE_TLB_INV_CR, >> + [COPY_ENGINE_CLASS] = XEHP_BLT_TLB_INV_CR, >> + [COMPUTE_CLASS] = XEHP_COMPCTX_TLB_INV_CR, >> + }; >> const unsigned int class = engine->class; >> - struct reg_and_bit rb = { }; >> + struct reg_and_bits rb = { .bits = BIT(engine->instance) }; >> - if (drm_WARN_ON_ONCE(&engine->i915->drm, >> - class >= num || !regs[class].reg)) >> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) >> + rb.mcr_reg = xehp_regs[class]; >> + else if (GRAPHICS_VER(engine->i915) >= 12) >> + rb.reg = gen12_regs[class]; >> + else if (GRAPHICS_VER(engine->i915) >= 8) >> + rb.reg = gen8_regs[class]; >> + >> + if (drm_WARN_ON_ONCE(&engine->i915->drm, >> !i915_mmio_reg_offset(rb.reg))) > > I'd prefer user readable message was kept but not a blocker. Tried to avoid changes in refactoring, will change. > >> return rb; >> - rb.reg = regs[class]; >> - if (gen8 && class == VIDEO_DECODE_CLASS) >> - rb.reg.reg += 4 * engine->instance; /* GEN8_M2TCR */ >> - else >> - rb.bit = engine->instance; >> + if (GRAPHICS_VER(engine->i915) < 12 && class == >> VIDEO_DECODE_CLASS) { >> + rb.bits = 1; >> + rb.reg.reg += 4 * engine->instance; > > No reason to drop the comment IMO. It explains things somewhat, or at > least provides a hint. OK > >> + } >> - rb.bit = BIT(rb.bit); >> + if (write && GRAPHICS_VER(engine->i915) >= 12 && >> + (class == VIDEO_DECODE_CLASS || class == >> VIDEO_ENHANCEMENT_CLASS || >> + class == COMPUTE_CLASS)) >> + rb.bits = _MASKED_BIT_ENABLE(rb.bits); > > This could be else if to not have < 12 followed by explicit >= 12, but > perhaps it is clearer like this, to signify it's two completely > separate quirks. > > Also, I would perhaps consider having a local i915 since there's a > good number of engine->i915, but it's up to you what looks nicer. OK > >> return rb; >> } >> @@ -1046,14 +1073,14 @@ get_reg_and_bit(const struct intel_engine_cs >> *engine, const bool gen8, >> * but are now considered MCR registers. Since they exist within a >> GAM range, >> * the primary instance of the register rolls up the status from >> each unit. >> */ >> -static int wait_for_invalidate(struct intel_gt *gt, struct >> reg_and_bit rb) >> +static int wait_for_invalidate(struct intel_gt *gt, struct >> reg_and_bits rb) >> { >> if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) >> - return intel_gt_mcr_wait_for_reg(gt, rb.mcr_reg, rb.bit, 0, >> + return intel_gt_mcr_wait_for_reg(gt, rb.mcr_reg, rb.bits, 0, >> TLB_INVAL_TIMEOUT_US, >> TLB_INVAL_TIMEOUT_MS); >> else >> - return __intel_wait_for_register_fw(gt->uncore, rb.reg, >> rb.bit, 0, >> + return __intel_wait_for_register_fw(gt->uncore, rb.reg, >> rb.bits, 0, >> TLB_INVAL_TIMEOUT_US, >> TLB_INVAL_TIMEOUT_MS, >> NULL); >> @@ -1061,50 +1088,14 @@ static int wait_for_invalidate(struct >> intel_gt *gt, struct reg_and_bit rb) >> static void mmio_invalidate_full(struct intel_gt *gt) >> { >> - static const i915_reg_t gen8_regs[] = { >> - [RENDER_CLASS] = GEN8_RTCR, >> - [VIDEO_DECODE_CLASS] = GEN8_M1TCR, /* , GEN8_M2TCR */ >> - [VIDEO_ENHANCEMENT_CLASS] = GEN8_VTCR, >> - [COPY_ENGINE_CLASS] = GEN8_BTCR, >> - }; >> - static const i915_reg_t gen12_regs[] = { >> - [RENDER_CLASS] = GEN12_GFX_TLB_INV_CR, >> - [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, >> - [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, >> - [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR, >> - [COMPUTE_CLASS] = GEN12_COMPCTX_TLB_INV_CR, >> - }; >> - static const i915_mcr_reg_t xehp_regs[] = { >> - [RENDER_CLASS] = XEHP_GFX_TLB_INV_CR, >> - [VIDEO_DECODE_CLASS] = XEHP_VD_TLB_INV_CR, >> - [VIDEO_ENHANCEMENT_CLASS] = XEHP_VE_TLB_INV_CR, >> - [COPY_ENGINE_CLASS] = XEHP_BLT_TLB_INV_CR, >> - [COMPUTE_CLASS] = XEHP_COMPCTX_TLB_INV_CR, >> - }; >> struct drm_i915_private *i915 = gt->i915; >> struct intel_uncore *uncore = gt->uncore; >> struct intel_engine_cs *engine; >> intel_engine_mask_t awake, tmp; >> enum intel_engine_id id; >> - const i915_reg_t *regs; >> - unsigned int num = 0; >> unsigned long flags; >> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { >> - regs = NULL; >> - num = ARRAY_SIZE(xehp_regs); >> - } else if (GRAPHICS_VER(i915) == 12) { >> - regs = gen12_regs; >> - num = ARRAY_SIZE(gen12_regs); >> - } else if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) <= 11) { >> - regs = gen8_regs; >> - num = ARRAY_SIZE(gen8_regs); >> - } else if (GRAPHICS_VER(i915) < 8) { >> - return; >> - } >> - >> - if (drm_WARN_ONCE(&i915->drm, !num, >> - "Platform does not implement TLB invalidation!")) >> + if (GRAPHICS_VER(i915) < 8) >> return; >> intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); >> @@ -1114,33 +1105,15 @@ static void mmio_invalidate_full(struct >> intel_gt *gt) >> awake = 0; >> for_each_engine(engine, gt, id) { >> - struct reg_and_bit rb; >> + struct reg_and_bits rb = get_tlb_inv_reg_and_bits(engine, >> true); > > Ugh so actually what was a once per invalidation lookup is now > repeated per engine, times two. I wonder if we can do this better. > Lets think about it a bit. It was always twice, see below. > > Regards, > > Tvrtko > >> if (!intel_engine_pm_is_awake(engine)) >> continue; >> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { >> - u32 val = BIT(engine->instance); >> - >> - if (engine->class == VIDEO_DECODE_CLASS || >> - engine->class == VIDEO_ENHANCEMENT_CLASS || >> - engine->class == COMPUTE_CLASS) >> - val = _MASKED_BIT_ENABLE(val); >> - intel_gt_mcr_multicast_write_fw(gt, >> - xehp_regs[engine->class], >> - val); >> - } else { >> - rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); Here is the 2nd call, from old code. Since there are two separate loops there are two calls, caching call results would be overkill IMO. Or I can put back whole logic to mmio_invalidate_full, GEN12 quirk is needed only in 1st loop (write), the only redundancy will be with GEN8 quirk, which could be handled with some helper. Is it worth trying? I guess it is no big gain. Regards Andrzej >> - if (!i915_mmio_reg_offset(rb.reg)) >> - continue; >> - >> - if (GRAPHICS_VER(i915) == 12 && (engine->class == >> VIDEO_DECODE_CLASS || >> - engine->class == VIDEO_ENHANCEMENT_CLASS || >> - engine->class == COMPUTE_CLASS)) >> - rb.bit = _MASKED_BIT_ENABLE(rb.bit); >> - >> - intel_uncore_write_fw(uncore, rb.reg, rb.bit); >> - } >> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) >> + intel_gt_mcr_multicast_write_fw(gt, rb.mcr_reg, rb.bits); >> + else >> + intel_uncore_write_fw(uncore, rb.reg, rb.bits); >> awake |= engine->mask; >> } >> @@ -1159,14 +1132,7 @@ static void mmio_invalidate_full(struct >> intel_gt *gt) >> intel_gt_mcr_unlock(gt, flags); >> for_each_engine_masked(engine, gt, awake, tmp) { >> - struct reg_and_bit rb; >> - >> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { >> - rb.mcr_reg = xehp_regs[engine->class]; >> - rb.bit = BIT(engine->instance); >> - } else { >> - rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); >> - } >> + struct reg_and_bits rb = get_tlb_inv_reg_and_bits(engine, >> false); >> if (wait_for_invalidate(gt, rb)) >> drm_err_ratelimited(>->i915->drm, ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915: cleanup TLB invalidation code 2022-12-09 11:33 ` Andrzej Hajda @ 2022-12-09 12:04 ` Tvrtko Ursulin 2022-12-09 12:35 ` Tvrtko Ursulin 0 siblings, 1 reply; 15+ messages in thread From: Tvrtko Ursulin @ 2022-12-09 12:04 UTC (permalink / raw) To: Andrzej Hajda, intel-gfx Cc: Chris Wilson, Daniel Vetter, Matthew Auld, Rodrigo Vivi, Nirmoy Das On 09/12/2022 11:33, Andrzej Hajda wrote: > > > On 09.12.2022 11:16, Tvrtko Ursulin wrote: >> >> On 07/12/2022 17:36, Andrzej Hajda wrote: >>> Whole register/bit selection logic has been moved to separate helper. >> >> Why is missing. > > ...to clean up mmio_invalidate_full function. > > Will add. > >> >>> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> >>> --- >>> drivers/gpu/drm/i915/gt/intel_gt.c | 136 +++++++++++------------------ >>> 1 file changed, 51 insertions(+), 85 deletions(-) >> >> Diffstat suggests because more streamlined code. Any other reason? >> >>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c >>> b/drivers/gpu/drm/i915/gt/intel_gt.c >>> index f0224b607aa4a7..05520ec3264db8 100644 >>> --- a/drivers/gpu/drm/i915/gt/intel_gt.c >>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c >>> @@ -1003,32 +1003,59 @@ void intel_gt_info_print(const struct >>> intel_gt_info *info, >>> intel_sseu_dump(&info->sseu, p); >>> } >>> -struct reg_and_bit { >>> +struct reg_and_bits { >>> union { >>> i915_reg_t reg; >>> i915_mcr_reg_t mcr_reg; >>> }; >>> - u32 bit; >>> + u32 bits; >>> }; >>> -static struct reg_and_bit >>> -get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8, >>> - const i915_reg_t *regs, const unsigned int num) >>> +static struct reg_and_bits >>> +get_tlb_inv_reg_and_bits(const struct intel_engine_cs *engine, bool >>> write) >>> { >>> + static const i915_reg_t gen8_regs[MAX_ENGINE_CLASS + 1] = { >>> + [RENDER_CLASS] = GEN8_RTCR, >>> + [VIDEO_DECODE_CLASS] = GEN8_M1TCR, >>> + [VIDEO_ENHANCEMENT_CLASS] = GEN8_VTCR, >>> + [COPY_ENGINE_CLASS] = GEN8_BTCR, >>> + }; >>> + static const i915_reg_t gen12_regs[MAX_ENGINE_CLASS + 1] = { >>> + [RENDER_CLASS] = GEN12_GFX_TLB_INV_CR, >>> + [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, >>> + [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, >>> + [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR, >>> + [COMPUTE_CLASS] = GEN12_COMPCTX_TLB_INV_CR, >>> + }; >>> + static const i915_mcr_reg_t xehp_regs[MAX_ENGINE_CLASS + 1] = { >>> + [RENDER_CLASS] = XEHP_GFX_TLB_INV_CR, >>> + [VIDEO_DECODE_CLASS] = XEHP_VD_TLB_INV_CR, >>> + [VIDEO_ENHANCEMENT_CLASS] = XEHP_VE_TLB_INV_CR, >>> + [COPY_ENGINE_CLASS] = XEHP_BLT_TLB_INV_CR, >>> + [COMPUTE_CLASS] = XEHP_COMPCTX_TLB_INV_CR, >>> + }; >>> const unsigned int class = engine->class; >>> - struct reg_and_bit rb = { }; >>> + struct reg_and_bits rb = { .bits = BIT(engine->instance) }; >>> - if (drm_WARN_ON_ONCE(&engine->i915->drm, >>> - class >= num || !regs[class].reg)) >>> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) >>> + rb.mcr_reg = xehp_regs[class]; >>> + else if (GRAPHICS_VER(engine->i915) >= 12) >>> + rb.reg = gen12_regs[class]; >>> + else if (GRAPHICS_VER(engine->i915) >= 8) >>> + rb.reg = gen8_regs[class]; >>> + >>> + if (drm_WARN_ON_ONCE(&engine->i915->drm, >>> !i915_mmio_reg_offset(rb.reg))) >> >> I'd prefer user readable message was kept but not a blocker. > > Tried to avoid changes in refactoring, will change. > >> >>> return rb; >>> - rb.reg = regs[class]; >>> - if (gen8 && class == VIDEO_DECODE_CLASS) >>> - rb.reg.reg += 4 * engine->instance; /* GEN8_M2TCR */ >>> - else >>> - rb.bit = engine->instance; >>> + if (GRAPHICS_VER(engine->i915) < 12 && class == >>> VIDEO_DECODE_CLASS) { >>> + rb.bits = 1; >>> + rb.reg.reg += 4 * engine->instance; >> >> No reason to drop the comment IMO. It explains things somewhat, or at >> least provides a hint. > > OK > >> >>> + } >>> - rb.bit = BIT(rb.bit); >>> + if (write && GRAPHICS_VER(engine->i915) >= 12 && >>> + (class == VIDEO_DECODE_CLASS || class == >>> VIDEO_ENHANCEMENT_CLASS || >>> + class == COMPUTE_CLASS)) >>> + rb.bits = _MASKED_BIT_ENABLE(rb.bits); >> >> This could be else if to not have < 12 followed by explicit >= 12, but >> perhaps it is clearer like this, to signify it's two completely >> separate quirks. >> >> Also, I would perhaps consider having a local i915 since there's a >> good number of engine->i915, but it's up to you what looks nicer. > > OK > >> >>> return rb; >>> } >>> @@ -1046,14 +1073,14 @@ get_reg_and_bit(const struct intel_engine_cs >>> *engine, const bool gen8, >>> * but are now considered MCR registers. Since they exist within a >>> GAM range, >>> * the primary instance of the register rolls up the status from >>> each unit. >>> */ >>> -static int wait_for_invalidate(struct intel_gt *gt, struct >>> reg_and_bit rb) >>> +static int wait_for_invalidate(struct intel_gt *gt, struct >>> reg_and_bits rb) >>> { >>> if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) >>> - return intel_gt_mcr_wait_for_reg(gt, rb.mcr_reg, rb.bit, 0, >>> + return intel_gt_mcr_wait_for_reg(gt, rb.mcr_reg, rb.bits, 0, >>> TLB_INVAL_TIMEOUT_US, >>> TLB_INVAL_TIMEOUT_MS); >>> else >>> - return __intel_wait_for_register_fw(gt->uncore, rb.reg, >>> rb.bit, 0, >>> + return __intel_wait_for_register_fw(gt->uncore, rb.reg, >>> rb.bits, 0, >>> TLB_INVAL_TIMEOUT_US, >>> TLB_INVAL_TIMEOUT_MS, >>> NULL); >>> @@ -1061,50 +1088,14 @@ static int wait_for_invalidate(struct >>> intel_gt *gt, struct reg_and_bit rb) >>> static void mmio_invalidate_full(struct intel_gt *gt) >>> { >>> - static const i915_reg_t gen8_regs[] = { >>> - [RENDER_CLASS] = GEN8_RTCR, >>> - [VIDEO_DECODE_CLASS] = GEN8_M1TCR, /* , GEN8_M2TCR */ >>> - [VIDEO_ENHANCEMENT_CLASS] = GEN8_VTCR, >>> - [COPY_ENGINE_CLASS] = GEN8_BTCR, >>> - }; >>> - static const i915_reg_t gen12_regs[] = { >>> - [RENDER_CLASS] = GEN12_GFX_TLB_INV_CR, >>> - [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, >>> - [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, >>> - [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR, >>> - [COMPUTE_CLASS] = GEN12_COMPCTX_TLB_INV_CR, >>> - }; >>> - static const i915_mcr_reg_t xehp_regs[] = { >>> - [RENDER_CLASS] = XEHP_GFX_TLB_INV_CR, >>> - [VIDEO_DECODE_CLASS] = XEHP_VD_TLB_INV_CR, >>> - [VIDEO_ENHANCEMENT_CLASS] = XEHP_VE_TLB_INV_CR, >>> - [COPY_ENGINE_CLASS] = XEHP_BLT_TLB_INV_CR, >>> - [COMPUTE_CLASS] = XEHP_COMPCTX_TLB_INV_CR, >>> - }; >>> struct drm_i915_private *i915 = gt->i915; >>> struct intel_uncore *uncore = gt->uncore; >>> struct intel_engine_cs *engine; >>> intel_engine_mask_t awake, tmp; >>> enum intel_engine_id id; >>> - const i915_reg_t *regs; >>> - unsigned int num = 0; >>> unsigned long flags; >>> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { >>> - regs = NULL; >>> - num = ARRAY_SIZE(xehp_regs); >>> - } else if (GRAPHICS_VER(i915) == 12) { >>> - regs = gen12_regs; >>> - num = ARRAY_SIZE(gen12_regs); >>> - } else if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) <= 11) { >>> - regs = gen8_regs; >>> - num = ARRAY_SIZE(gen8_regs); >>> - } else if (GRAPHICS_VER(i915) < 8) { >>> - return; >>> - } >>> - >>> - if (drm_WARN_ONCE(&i915->drm, !num, >>> - "Platform does not implement TLB invalidation!")) >>> + if (GRAPHICS_VER(i915) < 8) >>> return; >>> intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); >>> @@ -1114,33 +1105,15 @@ static void mmio_invalidate_full(struct >>> intel_gt *gt) >>> awake = 0; >>> for_each_engine(engine, gt, id) { >>> - struct reg_and_bit rb; >>> + struct reg_and_bits rb = get_tlb_inv_reg_and_bits(engine, >>> true); >> >> Ugh so actually what was a once per invalidation lookup is now >> repeated per engine, times two. I wonder if we can do this better. >> Lets think about it a bit. > > It was always twice, see below. > >> >> Regards, >> >> Tvrtko >> >>> if (!intel_engine_pm_is_awake(engine)) >>> continue; >>> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { >>> - u32 val = BIT(engine->instance); >>> - >>> - if (engine->class == VIDEO_DECODE_CLASS || >>> - engine->class == VIDEO_ENHANCEMENT_CLASS || >>> - engine->class == COMPUTE_CLASS) >>> - val = _MASKED_BIT_ENABLE(val); >>> - intel_gt_mcr_multicast_write_fw(gt, >>> - xehp_regs[engine->class], >>> - val); >>> - } else { >>> - rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); > > Here is the 2nd call, from old code. > Since there are two separate loops there are two calls, caching call > results would be overkill IMO. > Or I can put back whole logic to mmio_invalidate_full, GEN12 quirk is > needed only in 1st loop (write), the only redundancy will be with GEN8 > quirk, which could be handled with some helper. > Is it worth trying? I guess it is no big gain. Yes it was always twice in get_reg_and_bit but not the whole register table selection. We have some checkes which are per platform, and some which are platform and engine. I propose to keep them split. I made a stab at it like this: diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 0377e1b25be9..d907b9005dd6 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -988,33 +988,50 @@ void intel_gt_info_print(const struct intel_gt_info *info, intel_sseu_dump(&info->sseu, p); } -struct reg_and_bit { +struct inv_reg { union { i915_reg_t reg; i915_mcr_reg_t mcr_reg; }; +}; + +struct reg_and_bit { + struct inv_reg reg; u32 bit; }; static struct reg_and_bit -get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8, - const i915_reg_t *regs, const unsigned int num) +get_reg_and_bit(const struct intel_engine_cs *engine, + const i915_reg_t *regs, const unsigned int num, + bool write) { + struct drm_i915_private *i915 = engine->i915; const unsigned int class = engine->class; struct reg_and_bit rb = { }; + BUILD_BUG_ON(sizeof(rb.reg.reg) != sizeof(rb.reg.mcr_reg)); + BUILD_BUG_ON(!__builtin_types_compatible_p(typeof(rb.reg.reg.reg), + typeof(rb.reg.mcr_reg.reg))); + if (drm_WARN_ON_ONCE(&engine->i915->drm, class >= num || !regs[class].reg)) return rb; - rb.reg = regs[class]; - if (gen8 && class == VIDEO_DECODE_CLASS) - rb.reg.reg += 4 * engine->instance; /* GEN8_M2TCR */ + rb.reg.reg = regs[class]; + + if (GRAPHICS_VER(i915) < 12 && class == VIDEO_DECODE_CLASS) + rb.reg.reg.reg += 4 * engine->instance; /* GEN8_M2TCR */ else rb.bit = engine->instance; rb.bit = BIT(rb.bit); + if (write && GRAPHICS_VER(i915) >= 12 && + (engine->class == VIDEO_DECODE_CLASS || + engine->class == VIDEO_ENHANCEMENT_CLASS || + engine->class == COMPUTE_CLASS)) + rb.bit = _MASKED_BIT_ENABLE(rb.bit); + return rb; } @@ -1031,14 +1048,16 @@ get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8, * but are now considered MCR registers. Since they exist within a GAM range, * the primary instance of the register rolls up the status from each unit. */ -static int wait_for_invalidate(struct intel_gt *gt, struct reg_and_bit rb) +static int +wait_for_invalidate(struct intel_gt *gt, struct reg_and_bit rb, bool mcr) { - if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) - return intel_gt_mcr_wait_for_reg(gt, rb.mcr_reg, rb.bit, 0, + if (mcr) + return intel_gt_mcr_wait_for_reg(gt, rb.reg.mcr_reg, rb.bit, 0, TLB_INVAL_TIMEOUT_US, TLB_INVAL_TIMEOUT_MS); else - return __intel_wait_for_register_fw(gt->uncore, rb.reg, rb.bit, 0, + return __intel_wait_for_register_fw(gt->uncore, + rb.reg.reg, rb.bit, 0, TLB_INVAL_TIMEOUT_US, TLB_INVAL_TIMEOUT_MS, NULL); @@ -1068,6 +1087,7 @@ static void mmio_invalidate_full(struct intel_gt *gt) }; struct drm_i915_private *i915 = gt->i915; struct intel_uncore *uncore = gt->uncore; + const bool mcr = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50); struct intel_engine_cs *engine; intel_engine_mask_t awake, tmp; enum intel_engine_id id; @@ -1076,7 +1096,7 @@ static void mmio_invalidate_full(struct intel_gt *gt) unsigned long flags; if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { - regs = NULL; + regs = (i915_reg_t *)xehp_regs; num = ARRAY_SIZE(xehp_regs); } else if (GRAPHICS_VER(i915) == 12) { regs = gen12_regs; @@ -1104,28 +1124,15 @@ static void mmio_invalidate_full(struct intel_gt *gt) if (!intel_engine_pm_is_awake(engine)) continue; - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { - u32 val = BIT(engine->instance); - - if (engine->class == VIDEO_DECODE_CLASS || - engine->class == VIDEO_ENHANCEMENT_CLASS || - engine->class == COMPUTE_CLASS) - val = _MASKED_BIT_ENABLE(val); - intel_gt_mcr_multicast_write_fw(gt, - xehp_regs[engine->class], - val); - } else { - rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); - if (!i915_mmio_reg_offset(rb.reg)) - continue; - - if (GRAPHICS_VER(i915) == 12 && (engine->class == VIDEO_DECODE_CLASS || - engine->class == VIDEO_ENHANCEMENT_CLASS || - engine->class == COMPUTE_CLASS)) - rb.bit = _MASKED_BIT_ENABLE(rb.bit); - - intel_uncore_write_fw(uncore, rb.reg, rb.bit); - } + rb = get_reg_and_bit(engine, regs, num, true); + if (!i915_mmio_reg_offset(rb.reg.reg)) + continue; + + if (mcr) + intel_gt_mcr_multicast_write_fw(gt, rb.reg.mcr_reg, + rb.bit); + else + intel_uncore_write_fw(uncore, rb.reg.reg, rb.bit); awake |= engine->mask; } @@ -1144,16 +1151,10 @@ static void mmio_invalidate_full(struct intel_gt *gt) intel_gt_mcr_unlock(gt, flags); for_each_engine_masked(engine, gt, awake, tmp) { - struct reg_and_bit rb; - - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { - rb.mcr_reg = xehp_regs[engine->class]; - rb.bit = BIT(engine->instance); - } else { - rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); - } + struct reg_and_bit rb = + get_reg_and_bit(engine, regs, num, false); - if (wait_for_invalidate(gt, rb)) + if (wait_for_invalidate(gt, rb, mcr)) drm_err_ratelimited(>->i915->drm, "%s TLB invalidation did not complete in %ums!\n", engine->name, TLB_INVAL_TIMEOUT_MS); So only questions which vary per engine are asked in the engine loops. A bit hacky with asserts i915_reg_t and i915_mcr_reg_t are the same underlying type really but may be passable. See what you think. Regards, Tvrtko ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915: cleanup TLB invalidation code 2022-12-09 12:04 ` Tvrtko Ursulin @ 2022-12-09 12:35 ` Tvrtko Ursulin 2022-12-13 9:21 ` [Intel-gfx] [PATCH] " Andrzej Hajda 0 siblings, 1 reply; 15+ messages in thread From: Tvrtko Ursulin @ 2022-12-09 12:35 UTC (permalink / raw) To: Andrzej Hajda, intel-gfx Cc: Chris Wilson, Daniel Vetter, Matthew Auld, Rodrigo Vivi, Nirmoy Das On 09/12/2022 12:04, Tvrtko Ursulin wrote: > > On 09/12/2022 11:33, Andrzej Hajda wrote: >> >> >> On 09.12.2022 11:16, Tvrtko Ursulin wrote: >>> >>> On 07/12/2022 17:36, Andrzej Hajda wrote: >>>> Whole register/bit selection logic has been moved to separate helper. >>> >>> Why is missing. >> >> ...to clean up mmio_invalidate_full function. >> >> Will add. >> >>> >>>> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> >>>> --- >>>> drivers/gpu/drm/i915/gt/intel_gt.c | 136 >>>> +++++++++++------------------ >>>> 1 file changed, 51 insertions(+), 85 deletions(-) >>> >>> Diffstat suggests because more streamlined code. Any other reason? >>> >>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c >>>> b/drivers/gpu/drm/i915/gt/intel_gt.c >>>> index f0224b607aa4a7..05520ec3264db8 100644 >>>> --- a/drivers/gpu/drm/i915/gt/intel_gt.c >>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c >>>> @@ -1003,32 +1003,59 @@ void intel_gt_info_print(const struct >>>> intel_gt_info *info, >>>> intel_sseu_dump(&info->sseu, p); >>>> } >>>> -struct reg_and_bit { >>>> +struct reg_and_bits { >>>> union { >>>> i915_reg_t reg; >>>> i915_mcr_reg_t mcr_reg; >>>> }; >>>> - u32 bit; >>>> + u32 bits; >>>> }; >>>> -static struct reg_and_bit >>>> -get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8, >>>> - const i915_reg_t *regs, const unsigned int num) >>>> +static struct reg_and_bits >>>> +get_tlb_inv_reg_and_bits(const struct intel_engine_cs *engine, bool >>>> write) >>>> { >>>> + static const i915_reg_t gen8_regs[MAX_ENGINE_CLASS + 1] = { >>>> + [RENDER_CLASS] = GEN8_RTCR, >>>> + [VIDEO_DECODE_CLASS] = GEN8_M1TCR, >>>> + [VIDEO_ENHANCEMENT_CLASS] = GEN8_VTCR, >>>> + [COPY_ENGINE_CLASS] = GEN8_BTCR, >>>> + }; >>>> + static const i915_reg_t gen12_regs[MAX_ENGINE_CLASS + 1] = { >>>> + [RENDER_CLASS] = GEN12_GFX_TLB_INV_CR, >>>> + [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, >>>> + [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, >>>> + [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR, >>>> + [COMPUTE_CLASS] = GEN12_COMPCTX_TLB_INV_CR, >>>> + }; >>>> + static const i915_mcr_reg_t xehp_regs[MAX_ENGINE_CLASS + 1] = { >>>> + [RENDER_CLASS] = XEHP_GFX_TLB_INV_CR, >>>> + [VIDEO_DECODE_CLASS] = XEHP_VD_TLB_INV_CR, >>>> + [VIDEO_ENHANCEMENT_CLASS] = XEHP_VE_TLB_INV_CR, >>>> + [COPY_ENGINE_CLASS] = XEHP_BLT_TLB_INV_CR, >>>> + [COMPUTE_CLASS] = XEHP_COMPCTX_TLB_INV_CR, >>>> + }; >>>> const unsigned int class = engine->class; >>>> - struct reg_and_bit rb = { }; >>>> + struct reg_and_bits rb = { .bits = BIT(engine->instance) }; >>>> - if (drm_WARN_ON_ONCE(&engine->i915->drm, >>>> - class >= num || !regs[class].reg)) >>>> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) >>>> + rb.mcr_reg = xehp_regs[class]; >>>> + else if (GRAPHICS_VER(engine->i915) >= 12) >>>> + rb.reg = gen12_regs[class]; >>>> + else if (GRAPHICS_VER(engine->i915) >= 8) >>>> + rb.reg = gen8_regs[class]; >>>> + >>>> + if (drm_WARN_ON_ONCE(&engine->i915->drm, >>>> !i915_mmio_reg_offset(rb.reg))) >>> >>> I'd prefer user readable message was kept but not a blocker. >> >> Tried to avoid changes in refactoring, will change. >> >>> >>>> return rb; >>>> - rb.reg = regs[class]; >>>> - if (gen8 && class == VIDEO_DECODE_CLASS) >>>> - rb.reg.reg += 4 * engine->instance; /* GEN8_M2TCR */ >>>> - else >>>> - rb.bit = engine->instance; >>>> + if (GRAPHICS_VER(engine->i915) < 12 && class == >>>> VIDEO_DECODE_CLASS) { >>>> + rb.bits = 1; >>>> + rb.reg.reg += 4 * engine->instance; >>> >>> No reason to drop the comment IMO. It explains things somewhat, or at >>> least provides a hint. >> >> OK >> >>> >>>> + } >>>> - rb.bit = BIT(rb.bit); >>>> + if (write && GRAPHICS_VER(engine->i915) >= 12 && >>>> + (class == VIDEO_DECODE_CLASS || class == >>>> VIDEO_ENHANCEMENT_CLASS || >>>> + class == COMPUTE_CLASS)) >>>> + rb.bits = _MASKED_BIT_ENABLE(rb.bits); >>> >>> This could be else if to not have < 12 followed by explicit >= 12, >>> but perhaps it is clearer like this, to signify it's two completely >>> separate quirks. >>> >>> Also, I would perhaps consider having a local i915 since there's a >>> good number of engine->i915, but it's up to you what looks nicer. >> >> OK >> >>> >>>> return rb; >>>> } >>>> @@ -1046,14 +1073,14 @@ get_reg_and_bit(const struct intel_engine_cs >>>> *engine, const bool gen8, >>>> * but are now considered MCR registers. Since they exist within >>>> a GAM range, >>>> * the primary instance of the register rolls up the status from >>>> each unit. >>>> */ >>>> -static int wait_for_invalidate(struct intel_gt *gt, struct >>>> reg_and_bit rb) >>>> +static int wait_for_invalidate(struct intel_gt *gt, struct >>>> reg_and_bits rb) >>>> { >>>> if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) >>>> - return intel_gt_mcr_wait_for_reg(gt, rb.mcr_reg, rb.bit, 0, >>>> + return intel_gt_mcr_wait_for_reg(gt, rb.mcr_reg, rb.bits, 0, >>>> TLB_INVAL_TIMEOUT_US, >>>> TLB_INVAL_TIMEOUT_MS); >>>> else >>>> - return __intel_wait_for_register_fw(gt->uncore, rb.reg, >>>> rb.bit, 0, >>>> + return __intel_wait_for_register_fw(gt->uncore, rb.reg, >>>> rb.bits, 0, >>>> TLB_INVAL_TIMEOUT_US, >>>> TLB_INVAL_TIMEOUT_MS, >>>> NULL); >>>> @@ -1061,50 +1088,14 @@ static int wait_for_invalidate(struct >>>> intel_gt *gt, struct reg_and_bit rb) >>>> static void mmio_invalidate_full(struct intel_gt *gt) >>>> { >>>> - static const i915_reg_t gen8_regs[] = { >>>> - [RENDER_CLASS] = GEN8_RTCR, >>>> - [VIDEO_DECODE_CLASS] = GEN8_M1TCR, /* , GEN8_M2TCR */ >>>> - [VIDEO_ENHANCEMENT_CLASS] = GEN8_VTCR, >>>> - [COPY_ENGINE_CLASS] = GEN8_BTCR, >>>> - }; >>>> - static const i915_reg_t gen12_regs[] = { >>>> - [RENDER_CLASS] = GEN12_GFX_TLB_INV_CR, >>>> - [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, >>>> - [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, >>>> - [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR, >>>> - [COMPUTE_CLASS] = GEN12_COMPCTX_TLB_INV_CR, >>>> - }; >>>> - static const i915_mcr_reg_t xehp_regs[] = { >>>> - [RENDER_CLASS] = XEHP_GFX_TLB_INV_CR, >>>> - [VIDEO_DECODE_CLASS] = XEHP_VD_TLB_INV_CR, >>>> - [VIDEO_ENHANCEMENT_CLASS] = XEHP_VE_TLB_INV_CR, >>>> - [COPY_ENGINE_CLASS] = XEHP_BLT_TLB_INV_CR, >>>> - [COMPUTE_CLASS] = XEHP_COMPCTX_TLB_INV_CR, >>>> - }; >>>> struct drm_i915_private *i915 = gt->i915; >>>> struct intel_uncore *uncore = gt->uncore; >>>> struct intel_engine_cs *engine; >>>> intel_engine_mask_t awake, tmp; >>>> enum intel_engine_id id; >>>> - const i915_reg_t *regs; >>>> - unsigned int num = 0; >>>> unsigned long flags; >>>> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { >>>> - regs = NULL; >>>> - num = ARRAY_SIZE(xehp_regs); >>>> - } else if (GRAPHICS_VER(i915) == 12) { >>>> - regs = gen12_regs; >>>> - num = ARRAY_SIZE(gen12_regs); >>>> - } else if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) <= 11) { >>>> - regs = gen8_regs; >>>> - num = ARRAY_SIZE(gen8_regs); >>>> - } else if (GRAPHICS_VER(i915) < 8) { >>>> - return; >>>> - } >>>> - >>>> - if (drm_WARN_ONCE(&i915->drm, !num, >>>> - "Platform does not implement TLB invalidation!")) >>>> + if (GRAPHICS_VER(i915) < 8) >>>> return; >>>> intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); >>>> @@ -1114,33 +1105,15 @@ static void mmio_invalidate_full(struct >>>> intel_gt *gt) >>>> awake = 0; >>>> for_each_engine(engine, gt, id) { >>>> - struct reg_and_bit rb; >>>> + struct reg_and_bits rb = get_tlb_inv_reg_and_bits(engine, >>>> true); >>> >>> Ugh so actually what was a once per invalidation lookup is now >>> repeated per engine, times two. I wonder if we can do this better. >>> Lets think about it a bit. >> >> It was always twice, see below. >> >>> >>> Regards, >>> >>> Tvrtko >>> >>>> if (!intel_engine_pm_is_awake(engine)) >>>> continue; >>>> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { >>>> - u32 val = BIT(engine->instance); >>>> - >>>> - if (engine->class == VIDEO_DECODE_CLASS || >>>> - engine->class == VIDEO_ENHANCEMENT_CLASS || >>>> - engine->class == COMPUTE_CLASS) >>>> - val = _MASKED_BIT_ENABLE(val); >>>> - intel_gt_mcr_multicast_write_fw(gt, >>>> - xehp_regs[engine->class], >>>> - val); >>>> - } else { >>>> - rb = get_reg_and_bit(engine, regs == gen8_regs, regs, >>>> num); >> >> Here is the 2nd call, from old code. >> Since there are two separate loops there are two calls, caching call >> results would be overkill IMO. >> Or I can put back whole logic to mmio_invalidate_full, GEN12 quirk is >> needed only in 1st loop (write), the only redundancy will be with GEN8 >> quirk, which could be handled with some helper. >> Is it worth trying? I guess it is no big gain. > > Yes it was always twice in get_reg_and_bit but not the whole register > table selection. > > We have some checkes which are per platform, and some which are platform > and engine. I propose to keep them split. I made a stab at it like this: > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c > b/drivers/gpu/drm/i915/gt/intel_gt.c > index 0377e1b25be9..d907b9005dd6 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > @@ -988,33 +988,50 @@ void intel_gt_info_print(const struct > intel_gt_info *info, > intel_sseu_dump(&info->sseu, p); > } > > -struct reg_and_bit { > +struct inv_reg { > union { > i915_reg_t reg; > i915_mcr_reg_t mcr_reg; > }; > +}; > + > +struct reg_and_bit { > + struct inv_reg reg; > u32 bit; > }; > > static struct reg_and_bit > -get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8, > - const i915_reg_t *regs, const unsigned int num) > +get_reg_and_bit(const struct intel_engine_cs *engine, > + const i915_reg_t *regs, const unsigned int num, > + bool write) > { > + struct drm_i915_private *i915 = engine->i915; > const unsigned int class = engine->class; > struct reg_and_bit rb = { }; > > + BUILD_BUG_ON(sizeof(rb.reg.reg) != sizeof(rb.reg.mcr_reg)); > + BUILD_BUG_ON(!__builtin_types_compatible_p(typeof(rb.reg.reg.reg), > + > typeof(rb.reg.mcr_reg.reg))); > + > if (drm_WARN_ON_ONCE(&engine->i915->drm, > class >= num || !regs[class].reg)) > return rb; > > - rb.reg = regs[class]; > - if (gen8 && class == VIDEO_DECODE_CLASS) > - rb.reg.reg += 4 * engine->instance; /* GEN8_M2TCR */ > + rb.reg.reg = regs[class]; > + > + if (GRAPHICS_VER(i915) < 12 && class == VIDEO_DECODE_CLASS) > + rb.reg.reg.reg += 4 * engine->instance; /* GEN8_M2TCR */ > else > rb.bit = engine->instance; > > rb.bit = BIT(rb.bit); > > + if (write && GRAPHICS_VER(i915) >= 12 && > + (engine->class == VIDEO_DECODE_CLASS || > + engine->class == VIDEO_ENHANCEMENT_CLASS || > + engine->class == COMPUTE_CLASS)) > + rb.bit = _MASKED_BIT_ENABLE(rb.bit); > + > return rb; > } > > @@ -1031,14 +1048,16 @@ get_reg_and_bit(const struct intel_engine_cs > *engine, const bool gen8, > * but are now considered MCR registers. Since they exist within a > GAM range, > * the primary instance of the register rolls up the status from each > unit. > */ > -static int wait_for_invalidate(struct intel_gt *gt, struct reg_and_bit rb) > +static int > +wait_for_invalidate(struct intel_gt *gt, struct reg_and_bit rb, bool mcr) > { > - if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) > - return intel_gt_mcr_wait_for_reg(gt, rb.mcr_reg, rb.bit, 0, > + if (mcr) > + return intel_gt_mcr_wait_for_reg(gt, rb.reg.mcr_reg, > rb.bit, 0, > TLB_INVAL_TIMEOUT_US, > TLB_INVAL_TIMEOUT_MS); > else > - return __intel_wait_for_register_fw(gt->uncore, rb.reg, > rb.bit, 0, > + return __intel_wait_for_register_fw(gt->uncore, > + rb.reg.reg, rb.bit, 0, > TLB_INVAL_TIMEOUT_US, > TLB_INVAL_TIMEOUT_MS, > NULL); > @@ -1068,6 +1087,7 @@ static void mmio_invalidate_full(struct intel_gt *gt) > }; > struct drm_i915_private *i915 = gt->i915; > struct intel_uncore *uncore = gt->uncore; > + const bool mcr = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50); > struct intel_engine_cs *engine; > intel_engine_mask_t awake, tmp; > enum intel_engine_id id; > @@ -1076,7 +1096,7 @@ static void mmio_invalidate_full(struct intel_gt *gt) > unsigned long flags; > > if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { > - regs = NULL; > + regs = (i915_reg_t *)xehp_regs; > num = ARRAY_SIZE(xehp_regs); > } else if (GRAPHICS_VER(i915) == 12) { > regs = gen12_regs; > @@ -1104,28 +1124,15 @@ static void mmio_invalidate_full(struct intel_gt > *gt) > if (!intel_engine_pm_is_awake(engine)) > continue; > > - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { > - u32 val = BIT(engine->instance); > - > - if (engine->class == VIDEO_DECODE_CLASS || > - engine->class == VIDEO_ENHANCEMENT_CLASS || > - engine->class == COMPUTE_CLASS) > - val = _MASKED_BIT_ENABLE(val); > - intel_gt_mcr_multicast_write_fw(gt, > - > xehp_regs[engine->class], > - val); > - } else { > - rb = get_reg_and_bit(engine, regs == gen8_regs, > regs, num); > - if (!i915_mmio_reg_offset(rb.reg)) > - continue; > - > - if (GRAPHICS_VER(i915) == 12 && (engine->class > == VIDEO_DECODE_CLASS || > - engine->class == VIDEO_ENHANCEMENT_CLASS || > - engine->class == COMPUTE_CLASS)) > - rb.bit = _MASKED_BIT_ENABLE(rb.bit); > - > - intel_uncore_write_fw(uncore, rb.reg, rb.bit); > - } > + rb = get_reg_and_bit(engine, regs, num, true); > + if (!i915_mmio_reg_offset(rb.reg.reg)) > + continue; > + > + if (mcr) > + intel_gt_mcr_multicast_write_fw(gt, rb.reg.mcr_reg, > + rb.bit); > + else > + intel_uncore_write_fw(uncore, rb.reg.reg, rb.bit); > awake |= engine->mask; > } > > @@ -1144,16 +1151,10 @@ static void mmio_invalidate_full(struct intel_gt > *gt) > intel_gt_mcr_unlock(gt, flags); > > for_each_engine_masked(engine, gt, awake, tmp) { > - struct reg_and_bit rb; > - > - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { > - rb.mcr_reg = xehp_regs[engine->class]; > - rb.bit = BIT(engine->instance); > - } else { > - rb = get_reg_and_bit(engine, regs == gen8_regs, > regs, num); > - } > + struct reg_and_bit rb = > + get_reg_and_bit(engine, regs, num, false); > > - if (wait_for_invalidate(gt, rb)) > + if (wait_for_invalidate(gt, rb, mcr)) > drm_err_ratelimited(>->i915->drm, > "%s TLB invalidation did > not complete in %ums!\n", > engine->name, > TLB_INVAL_TIMEOUT_MS); > > So only questions which vary per engine are asked in the engine loops. > > A bit hacky with asserts i915_reg_t and i915_mcr_reg_t are the same > underlying type really but may be passable. See what you think. Or even store register and values (write/read) in struct intel_engine_cs at engine init time? Regards, Tvrtko ^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH] drm/i915: cleanup TLB invalidation code 2022-12-09 12:35 ` Tvrtko Ursulin @ 2022-12-13 9:21 ` Andrzej Hajda 0 siblings, 0 replies; 15+ messages in thread From: Andrzej Hajda @ 2022-12-13 9:21 UTC (permalink / raw) To: intel-gfx; +Cc: Andrzej Hajda, Rodrigo Vivi After adding multicast and write mask support the TLB invalidation code become slightly incosistent and redundant. Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> --- Hi, This is another cleanup attempt. Multicast makes things quite complicated, either lot of ifs, either redundancy. I guess we will end up with some common helpers to support cases where the same code should access mcr and traditional registers, depending on GPU version. I took some ideas from your proposition, but I've replaced get_reg_and_bit with two very simple helpers. Regards Andrzej --- drivers/gpu/drm/i915/gt/intel_gt.c | 148 +++++++++++++---------------- 1 file changed, 64 insertions(+), 84 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 7eeee5a7cb33cb..e777600e0425ed 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -983,35 +983,15 @@ void intel_gt_info_print(const struct intel_gt_info *info, intel_sseu_dump(&info->sseu, p); } -struct reg_and_bit { - union { - i915_reg_t reg; - i915_mcr_reg_t mcr_reg; - }; - u32 bit; +union inv_reg { + i915_reg_t reg; + i915_mcr_reg_t mcr_reg; }; -static struct reg_and_bit -get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8, - const i915_reg_t *regs, const unsigned int num) -{ - const unsigned int class = engine->class; - struct reg_and_bit rb = { }; - - if (drm_WARN_ON_ONCE(&engine->i915->drm, - class >= num || !regs[class].reg)) - return rb; - - rb.reg = regs[class]; - if (gen8 && class == VIDEO_DECODE_CLASS) - rb.reg.reg += 4 * engine->instance; /* GEN8_M2TCR */ - else - rb.bit = engine->instance; - - rb.bit = BIT(rb.bit); - - return rb; -} +struct inv_reg_and_bit { + union inv_reg addr; + u32 bit; +}; /* * HW architecture suggest typical invalidation time at 40us, @@ -1026,52 +1006,72 @@ get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8, * but are now considered MCR registers. Since they exist within a GAM range, * the primary instance of the register rolls up the status from each unit. */ -static int wait_for_invalidate(struct intel_gt *gt, struct reg_and_bit rb) +static int wait_for_invalidate(struct intel_gt *gt, struct inv_reg_and_bit rb) { if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) - return intel_gt_mcr_wait_for_reg(gt, rb.mcr_reg, rb.bit, 0, + return intel_gt_mcr_wait_for_reg(gt, rb.addr.mcr_reg, rb.bit, 0, TLB_INVAL_TIMEOUT_US, TLB_INVAL_TIMEOUT_MS); else - return __intel_wait_for_register_fw(gt->uncore, rb.reg, rb.bit, 0, + return __intel_wait_for_register_fw(gt->uncore, rb.addr.reg, + rb.bit, 0, TLB_INVAL_TIMEOUT_US, TLB_INVAL_TIMEOUT_MS, NULL); } +static void inv_reg_set_write_mask(struct inv_reg_and_bit *rb, u8 class, u8 ver) +{ + if (ver >= 12 && (class == VIDEO_DECODE_CLASS || + class == VIDEO_ENHANCEMENT_CLASS || + class == COMPUTE_CLASS)) + rb->bit = _MASKED_BIT_ENABLE(rb->bit); +} + +static void inv_reg_set_instance(struct inv_reg_and_bit *rb, u8 class, + u8 instance, u8 ver) +{ + if (ver < 11 && class == VIDEO_DECODE_CLASS) { + rb->addr.reg.reg += 4 * instance; /* GEN8_M2TCR */ + rb->bit = 1; + } else { + rb->bit = BIT(instance); + } +} + static void mmio_invalidate_full(struct intel_gt *gt) { - static const i915_reg_t gen8_regs[] = { - [RENDER_CLASS] = GEN8_RTCR, - [VIDEO_DECODE_CLASS] = GEN8_M1TCR, /* , GEN8_M2TCR */ - [VIDEO_ENHANCEMENT_CLASS] = GEN8_VTCR, - [COPY_ENGINE_CLASS] = GEN8_BTCR, + static const union inv_reg gen8_regs[] = { + [RENDER_CLASS].reg = GEN8_RTCR, + [VIDEO_DECODE_CLASS].reg = GEN8_M1TCR, /* , GEN8_M2TCR */ + [VIDEO_ENHANCEMENT_CLASS].reg = GEN8_VTCR, + [COPY_ENGINE_CLASS].reg = GEN8_BTCR, }; - static const i915_reg_t gen12_regs[] = { - [RENDER_CLASS] = GEN12_GFX_TLB_INV_CR, - [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, - [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, - [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR, - [COMPUTE_CLASS] = GEN12_COMPCTX_TLB_INV_CR, + static const union inv_reg gen12_regs[] = { + [RENDER_CLASS].reg = GEN12_GFX_TLB_INV_CR, + [VIDEO_DECODE_CLASS].reg = GEN12_VD_TLB_INV_CR, + [VIDEO_ENHANCEMENT_CLASS].reg = GEN12_VE_TLB_INV_CR, + [COPY_ENGINE_CLASS].reg = GEN12_BLT_TLB_INV_CR, + [COMPUTE_CLASS].reg = GEN12_COMPCTX_TLB_INV_CR, }; - static const i915_mcr_reg_t xehp_regs[] = { - [RENDER_CLASS] = XEHP_GFX_TLB_INV_CR, - [VIDEO_DECODE_CLASS] = XEHP_VD_TLB_INV_CR, - [VIDEO_ENHANCEMENT_CLASS] = XEHP_VE_TLB_INV_CR, - [COPY_ENGINE_CLASS] = XEHP_BLT_TLB_INV_CR, - [COMPUTE_CLASS] = XEHP_COMPCTX_TLB_INV_CR, + static const union inv_reg xehp_regs[] = { + [RENDER_CLASS].mcr_reg = XEHP_GFX_TLB_INV_CR, + [VIDEO_DECODE_CLASS].mcr_reg = XEHP_VD_TLB_INV_CR, + [VIDEO_ENHANCEMENT_CLASS].mcr_reg = XEHP_VE_TLB_INV_CR, + [COPY_ENGINE_CLASS].mcr_reg = XEHP_BLT_TLB_INV_CR, + [COMPUTE_CLASS].mcr_reg = XEHP_COMPCTX_TLB_INV_CR, }; struct drm_i915_private *i915 = gt->i915; struct intel_uncore *uncore = gt->uncore; struct intel_engine_cs *engine; intel_engine_mask_t awake, tmp; + const union inv_reg *regs; enum intel_engine_id id; - const i915_reg_t *regs; unsigned int num = 0; unsigned long flags; if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { - regs = NULL; + regs = xehp_regs; num = ARRAY_SIZE(xehp_regs); } else if (GRAPHICS_VER(i915) == 12) { regs = gen12_regs; @@ -1083,10 +1083,6 @@ static void mmio_invalidate_full(struct intel_gt *gt) return; } - if (drm_WARN_ONCE(&i915->drm, !num, - "Platform does not implement TLB invalidation!")) - return; - intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); intel_gt_mcr_lock(gt, &flags); @@ -1094,33 +1090,22 @@ static void mmio_invalidate_full(struct intel_gt *gt) awake = 0; for_each_engine(engine, gt, id) { - struct reg_and_bit rb; + struct inv_reg_and_bit rb; if (!intel_engine_pm_is_awake(engine)) continue; - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { - u32 val = BIT(engine->instance); - - if (engine->class == VIDEO_DECODE_CLASS || - engine->class == VIDEO_ENHANCEMENT_CLASS || - engine->class == COMPUTE_CLASS) - val = _MASKED_BIT_ENABLE(val); - intel_gt_mcr_multicast_write_fw(gt, - xehp_regs[engine->class], - val); - } else { - rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); - if (!i915_mmio_reg_offset(rb.reg)) - continue; - - if (GRAPHICS_VER(i915) == 12 && (engine->class == VIDEO_DECODE_CLASS || - engine->class == VIDEO_ENHANCEMENT_CLASS || - engine->class == COMPUTE_CLASS)) - rb.bit = _MASKED_BIT_ENABLE(rb.bit); - - intel_uncore_write_fw(uncore, rb.reg, rb.bit); - } + rb.addr = regs[engine->class]; + if (!i915_mmio_reg_offset(rb.addr.reg)) + continue; + inv_reg_set_instance(&rb, engine->class, engine->instance, + GRAPHICS_VER(i915)); + inv_reg_set_write_mask(&rb, engine->class, GRAPHICS_VER(i915)); + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) + intel_gt_mcr_multicast_write_fw(gt, rb.addr.mcr_reg, + rb.bit); + else + intel_uncore_write_fw(uncore, rb.addr.reg, rb.bit); awake |= engine->mask; } @@ -1139,15 +1124,10 @@ static void mmio_invalidate_full(struct intel_gt *gt) intel_gt_mcr_unlock(gt, flags); for_each_engine_masked(engine, gt, awake, tmp) { - struct reg_and_bit rb; - - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { - rb.mcr_reg = xehp_regs[engine->class]; - rb.bit = BIT(engine->instance); - } else { - rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); - } + struct inv_reg_and_bit rb = { .addr = regs[engine->class] }; + inv_reg_set_instance(&rb, engine->class, engine->instance, + GRAPHICS_VER(i915)); if (wait_for_invalidate(gt, rb)) drm_err_ratelimited(>->i915->drm, "%s TLB invalidation did not complete in %ums!\n", -- 2.34.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines 2022-12-07 17:36 [Intel-gfx] [PATCH 1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines Andrzej Hajda 2022-12-07 17:36 ` [Intel-gfx] [PATCH 2/2] drm/i915: cleanup TLB invalidation code Andrzej Hajda @ 2022-12-07 20:36 ` Patchwork 2022-12-08 5:05 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork ` (5 subsequent siblings) 7 siblings, 0 replies; 15+ messages in thread From: Patchwork @ 2022-12-07 20:36 UTC (permalink / raw) To: Andrzej Hajda; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 5450 bytes --] == Series Details == Series: series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines URL : https://patchwork.freedesktop.org/series/111744/ State : success == Summary == CI Bug Log - changes from CI_DRM_12478 -> Patchwork_111744v1 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/index.html Participating hosts (39 -> 40) ------------------------------ Additional (3): bat-rpls-2 fi-bwr-2160 fi-bsw-nick Missing (2): fi-hsw-4770 bat-atsm-1 Known issues ------------ Here are the changes found in Patchwork_111744v1 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_gttfill@basic: - fi-pnv-d510: [PASS][1] -> [FAIL][2] ([i915#7229]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/fi-pnv-d510/igt@gem_exec_gttfill@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/fi-pnv-d510/igt@gem_exec_gttfill@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-bsw-nick: NOTRUN -> [SKIP][3] ([fdo#109271]) +39 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/fi-bsw-nick/igt@gem_lmem_swapping@parallel-random-engines.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: [PASS][4] -> [DMESG-FAIL][5] ([i915#5334]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-bsw-nick: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/fi-bsw-nick/igt@kms_chamelium@hdmi-hpd-fast.html * igt@kms_psr@primary_mmap_gtt: - fi-bwr-2160: NOTRUN -> [SKIP][7] ([fdo#109271]) +54 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/fi-bwr-2160/igt@kms_psr@primary_mmap_gtt.html #### Possible fixes #### * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions: - fi-bsw-kefka: [FAIL][8] ([i915#6298]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html #### Warnings #### * igt@i915_module_load@load: - fi-bsw-n3050: [DMESG-WARN][10] ([i915#1982] / [i915#7430]) -> [DMESG-WARN][11] ([i915#7430]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/fi-bsw-n3050/igt@i915_module_load@load.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/fi-bsw-n3050/igt@i915_module_load@load.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298 [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621 [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229 [i915#7346]: https://gitlab.freedesktop.org/drm/intel/issues/7346 [i915#7430]: https://gitlab.freedesktop.org/drm/intel/issues/7430 [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456 [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561 Build changes ------------- * Linux: CI_DRM_12478 -> Patchwork_111744v1 CI-20190529: 20190529 CI_DRM_12478: f5d2f00fe4daf65ecd6634dec39fbf66b44535e3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7085: 11af20de3877b23a244b816453bfc41d83591a15 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_111744v1: f5d2f00fe4daf65ecd6634dec39fbf66b44535e3 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 139c22791978 drm/i915: cleanup TLB invalidation code 5cc77dea1402 drm/i915: fix TLB invalidation for Gen12.50 video and compute engines == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/index.html [-- Attachment #2: Type: text/html, Size: 5340 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines 2022-12-07 17:36 [Intel-gfx] [PATCH 1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines Andrzej Hajda 2022-12-07 17:36 ` [Intel-gfx] [PATCH 2/2] drm/i915: cleanup TLB invalidation code Andrzej Hajda 2022-12-07 20:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines Patchwork @ 2022-12-08 5:05 ` Patchwork 2022-12-09 9:37 ` [Intel-gfx] [PATCH 1/2] " Tvrtko Ursulin ` (4 subsequent siblings) 7 siblings, 0 replies; 15+ messages in thread From: Patchwork @ 2022-12-08 5:05 UTC (permalink / raw) To: Andrzej Hajda; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 44847 bytes --] == Series Details == Series: series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines URL : https://patchwork.freedesktop.org/series/111744/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12478_full -> Patchwork_111744v1_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_111744v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_111744v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (14 -> 14) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_111744v1_full: ### IGT changes ### #### Possible regressions #### * igt@i915_selftest@perf@engine_cs: - shard-apl: [PASS][1] -> [DMESG-WARN][2] +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl1/igt@i915_selftest@perf@engine_cs.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl3/igt@i915_selftest@perf@engine_cs.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@gem_ctx_isolation@nonpriv@vcs0: - {shard-dg1}: NOTRUN -> [FAIL][3] +15 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-dg1-18/igt@gem_ctx_isolation@nonpriv@vcs0.html * igt@kms_content_protection@legacy: - {shard-tglu-9}: NOTRUN -> [SKIP][4] +22 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-tglu-9/igt@kms_content_protection@legacy.html New tests --------- New tests have been introduced between CI_DRM_12478_full and Patchwork_111744v1_full: ### New IGT tests (1) ### * igt@i915_pm_rpm: - Statuses : - Exec time: [None] s Known issues ------------ Here are the changes found in Patchwork_111744v1_full that come from known issues: ### CI changes ### #### Possible fixes #### * boot: - shard-apl: ([PASS][5], [PASS][6], [PASS][7], [PASS][8], [FAIL][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29]) ([i915#4386]) -> ([PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl1/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl1/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl1/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl1/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl2/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl2/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl2/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl2/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl2/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl3/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl3/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl3/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl3/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl6/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl6/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl6/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl7/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl7/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl7/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl7/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl8/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl8/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl8/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl8/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl1/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl8/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl8/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl8/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl8/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl8/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl1/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl1/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl1/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl1/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl2/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl2/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl2/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl2/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl3/boot.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl3/boot.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl3/boot.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl3/boot.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl6/boot.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl6/boot.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl6/boot.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl6/boot.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl7/boot.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl7/boot.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl7/boot.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl7/boot.html ### IGT changes ### #### Issues hit #### * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-apl: [PASS][55] -> [DMESG-WARN][56] ([i915#180]) +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl8/igt@gem_ctx_isolation@preservation-s3@vcs0.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl8/igt@gem_ctx_isolation@preservation-s3@vcs0.html * igt@gem_ctx_sseu@mmap-args: - shard-tglb: NOTRUN -> [SKIP][57] ([i915#280]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-tglb7/igt@gem_ctx_sseu@mmap-args.html * igt@gem_exec_balancer@parallel: - shard-iclb: [PASS][58] -> [SKIP][59] ([i915#4525]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-iclb1/igt@gem_exec_balancer@parallel.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-iclb3/igt@gem_exec_balancer@parallel.html * igt@gem_exec_fair@basic-deadline: - shard-skl: NOTRUN -> [FAIL][60] ([i915#2846]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl4/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][61] -> [FAIL][62] ([i915#2842]) +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-apl: NOTRUN -> [FAIL][63] ([i915#2842]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_exec_reloc@basic-write-wc: - shard-apl: [PASS][64] -> [DMESG-WARN][65] ([i915#180] / [i915#1982] / [i915#62]) [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl1/igt@gem_exec_reloc@basic-write-wc.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl3/igt@gem_exec_reloc@basic-write-wc.html * igt@gem_lmem_swapping@heavy-verify-multi-ccs: - shard-skl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#4613]) +3 similar issues [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl2/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html * igt@gem_pread@exhaustion: - shard-skl: NOTRUN -> [WARN][67] ([i915#2658]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl2/igt@gem_pread@exhaustion.html * igt@gem_softpin@evict-single-offset: - shard-tglb: [PASS][68] -> [FAIL][69] ([i915#4171]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-tglb6/igt@gem_softpin@evict-single-offset.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-tglb6/igt@gem_softpin@evict-single-offset.html * igt@gem_userptr_blits@input-checking: - shard-skl: NOTRUN -> [DMESG-WARN][70] ([i915#4991]) [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl1/igt@gem_userptr_blits@input-checking.html * igt@gen7_exec_parse@cmd-crossing-page: - shard-tglb: NOTRUN -> [SKIP][71] ([fdo#109289]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-tglb7/igt@gen7_exec_parse@cmd-crossing-page.html * igt@i915_pm_dc@dc6-psr: - shard-skl: NOTRUN -> [FAIL][72] ([i915#3989] / [i915#454]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl4/igt@i915_pm_dc@dc6-psr.html * igt@i915_pm_lpsp@screens-disabled: - shard-tglb: NOTRUN -> [SKIP][73] ([i915#1902]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-tglb7/igt@i915_pm_lpsp@screens-disabled.html * igt@i915_pm_rc6_residency@rc6-idle@vcs0: - shard-skl: [PASS][74] -> [WARN][75] ([i915#1804]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-skl3/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl4/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html * igt@i915_pm_rpm@pc8-residency: - shard-tglb: NOTRUN -> [SKIP][76] ([fdo#109506] / [i915#2411]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-tglb7/igt@i915_pm_rpm@pc8-residency.html * igt@i915_selftest@live@gt_heartbeat: - shard-skl: NOTRUN -> [DMESG-FAIL][77] ([i915#5334]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl5/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_pm: - shard-skl: NOTRUN -> [DMESG-FAIL][78] ([i915#1886]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl5/igt@i915_selftest@live@gt_pm.html * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip: - shard-tglb: NOTRUN -> [SKIP][79] ([i915#5286]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-tglb7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip: - shard-tglb: NOTRUN -> [SKIP][80] ([fdo#111615]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-tglb7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs: - shard-tglb: NOTRUN -> [SKIP][81] ([i915#3689] / [i915#3886]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-tglb7/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs: - shard-skl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#3886]) +8 similar issues [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl2/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_dg2_mc_ccs: - shard-tglb: NOTRUN -> [SKIP][83] ([i915#6095]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-tglb7/igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_dg2_mc_ccs.html * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc: - shard-apl: NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#3886]) +1 similar issue [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl7/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_rc_ccs_cc: - shard-tglb: NOTRUN -> [SKIP][85] ([i915#3689]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-tglb7/igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_rc_ccs_cc.html * igt@kms_chamelium@dp-edid-stress-resolution-4k: - shard-tglb: NOTRUN -> [SKIP][86] ([fdo#109284] / [fdo#111827]) [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-tglb7/igt@kms_chamelium@dp-edid-stress-resolution-4k.html * igt@kms_chamelium@hdmi-aspect-ratio: - shard-apl: NOTRUN -> [SKIP][87] ([fdo#109271] / [fdo#111827]) +3 similar issues [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl7/igt@kms_chamelium@hdmi-aspect-ratio.html * igt@kms_chamelium@hdmi-crc-multiple: - shard-skl: NOTRUN -> [SKIP][88] ([fdo#109271] / [fdo#111827]) +9 similar issues [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl1/igt@kms_chamelium@hdmi-crc-multiple.html * igt@kms_content_protection@uevent@pipe-a-dp-1: - shard-apl: NOTRUN -> [FAIL][89] ([i915#1339]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl7/igt@kms_content_protection@uevent@pipe-a-dp-1.html * igt@kms_cursor_legacy@cursor-vs-flip@toggle: - shard-skl: [PASS][90] -> [FAIL][91] ([i915#5072]) [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-skl1/igt@kms_cursor_legacy@cursor-vs-flip@toggle.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl2/igt@kms_cursor_legacy@cursor-vs-flip@toggle.html * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size: - shard-glk: [PASS][92] -> [FAIL][93] ([i915#2346]) [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html - shard-skl: NOTRUN -> [FAIL][94] ([i915#2346]) +1 similar issue [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html * igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2: - shard-glk: [PASS][95] -> [FAIL][96] ([i915#79]) [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1: - shard-skl: NOTRUN -> [FAIL][97] ([i915#2122]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1: - shard-skl: NOTRUN -> [FAIL][98] ([i915#79]) +1 similar issue [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html * igt@kms_flip@plain-flip-fb-recreate@a-edp1: - shard-skl: [PASS][99] -> [FAIL][100] ([i915#2122]) +2 similar issues [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-skl2/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl5/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][101] ([i915#2672]) +1 similar issue [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][102] ([i915#3555]) [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling@pipe-a-valid-mode: - shard-iclb: NOTRUN -> [SKIP][103] ([i915#2587] / [i915#2672]) +3 similar issues [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode: - shard-tglb: NOTRUN -> [SKIP][104] ([i915#2587] / [i915#2672]) [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-tglb7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][105] ([i915#2672] / [i915#3555]) +1 similar issue [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite: - shard-apl: NOTRUN -> [SKIP][106] ([fdo#109271]) +40 similar issues [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc: - shard-tglb: NOTRUN -> [SKIP][107] ([fdo#109280] / [fdo#111825]) +2 similar issues [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbcpsr-suspend: - shard-skl: NOTRUN -> [SKIP][108] ([fdo#109271]) +229 similar issues [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl4/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html * igt@kms_plane_alpha_blend@alpha-basic@pipe-a-edp-1: - shard-skl: NOTRUN -> [FAIL][109] ([i915#4573]) +1 similar issue [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl4/igt@kms_plane_alpha_blend@alpha-basic@pipe-a-edp-1.html * igt@kms_plane_alpha_blend@alpha-basic@pipe-c-edp-1: - shard-skl: NOTRUN -> [DMESG-FAIL][110] ([IGT#6]) [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl4/igt@kms_plane_alpha_blend@alpha-basic@pipe-c-edp-1.html * igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf: - shard-tglb: NOTRUN -> [SKIP][111] ([i915#2920]) [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-tglb7/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area: - shard-apl: NOTRUN -> [SKIP][112] ([fdo#109271] / [i915#658]) [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html * igt@kms_psr2_su@frontbuffer-xrgb8888: - shard-skl: NOTRUN -> [SKIP][113] ([fdo#109271] / [i915#658]) +2 similar issues [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl1/igt@kms_psr2_su@frontbuffer-xrgb8888.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][114] -> [SKIP][115] ([fdo#109441]) +2 similar issues [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html * igt@kms_psr_stress_test@flip-primary-invalidate-overlay: - shard-tglb: [PASS][116] -> [SKIP][117] ([i915#5519]) [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-tglb2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-tglb6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html * igt@kms_writeback@writeback-fb-id: - shard-skl: NOTRUN -> [SKIP][118] ([fdo#109271] / [i915#2437]) +1 similar issue [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl1/igt@kms_writeback@writeback-fb-id.html * igt@perf@stress-open-close: - shard-glk: [PASS][119] -> [INCOMPLETE][120] ([i915#5213]) [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-glk1/igt@perf@stress-open-close.html [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-glk6/igt@perf@stress-open-close.html * igt@sysfs_clients@pidname: - shard-skl: NOTRUN -> [SKIP][121] ([fdo#109271] / [i915#2994]) +1 similar issue [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl1/igt@sysfs_clients@pidname.html * igt@sysfs_clients@split-25: - shard-apl: NOTRUN -> [SKIP][122] ([fdo#109271] / [i915#2994]) [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl7/igt@sysfs_clients@split-25.html #### Possible fixes #### * igt@drm_read@short-buffer-block: - {shard-rkl}: [SKIP][123] ([i915#4098]) -> [PASS][124] +1 similar issue [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-rkl-1/igt@drm_read@short-buffer-block.html [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-rkl-6/igt@drm_read@short-buffer-block.html * igt@gem_blits@basic: - {shard-rkl}: [FAIL][125] -> [PASS][126] [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-rkl-1/igt@gem_blits@basic.html [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-rkl-5/igt@gem_blits@basic.html * igt@gem_exec_capture@pi@bcs0: - shard-skl: [INCOMPLETE][127] ([i915#3371]) -> [PASS][128] [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-skl1/igt@gem_exec_capture@pi@bcs0.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl1/igt@gem_exec_capture@pi@bcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-iclb: [FAIL][129] ([i915#2842]) -> [PASS][130] +1 similar issue [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-iclb3/igt@gem_exec_fair@basic-pace@vecs0.html [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-iclb5/igt@gem_exec_fair@basic-pace@vecs0.html * igt@gem_exec_reloc@basic-write-gtt: - {shard-rkl}: [SKIP][131] ([i915#3281]) -> [PASS][132] +4 similar issues [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-rkl-1/igt@gem_exec_reloc@basic-write-gtt.html [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-rkl-5/igt@gem_exec_reloc@basic-write-gtt.html * igt@gem_partial_pwrite_pread@reads: - {shard-rkl}: [SKIP][133] ([i915#3282]) -> [PASS][134] +1 similar issue [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-rkl-1/igt@gem_partial_pwrite_pread@reads.html [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-rkl-5/igt@gem_partial_pwrite_pread@reads.html * igt@gem_spin_batch@user-each: - shard-skl: [FAIL][135] ([i915#2898]) -> [PASS][136] [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-skl2/igt@gem_spin_batch@user-each.html [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl5/igt@gem_spin_batch@user-each.html * igt@gen9_exec_parse@bb-start-out: - {shard-rkl}: [SKIP][137] ([i915#2527]) -> [PASS][138] +1 similar issue [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-rkl-1/igt@gen9_exec_parse@bb-start-out.html [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-rkl-5/igt@gen9_exec_parse@bb-start-out.html * igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1: - shard-skl: [FAIL][139] ([i915#2521]) -> [PASS][140] +1 similar issue [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-skl4/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl4/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip: - {shard-rkl}: [SKIP][141] ([i915#1845] / [i915#4098]) -> [PASS][142] +4 similar issues [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-rkl-1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-rkl-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2: - shard-glk: [FAIL][143] ([i915#2122]) -> [PASS][144] [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html * igt@kms_flip@plain-flip-fb-recreate@b-edp1: - shard-skl: [FAIL][145] ([i915#2122]) -> [PASS][146] +1 similar issue [145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-skl2/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl5/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move: - {shard-rkl}: [SKIP][147] ([i915#1849] / [i915#4098]) -> [PASS][148] +8 similar issues [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite: - shard-skl: [DMESG-WARN][149] ([i915#1982]) -> [PASS][150] [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite.html [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite.html * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1: - shard-iclb: [SKIP][151] ([i915#5235]) -> [PASS][152] +2 similar issues [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-iclb1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html * igt@kms_psr@psr2_cursor_mmap_gtt: - shard-iclb: [SKIP][153] ([fdo#109441]) -> [PASS][154] +1 similar issue [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_gtt.html [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html * igt@kms_psr_stress_test@invalidate-primary-flip-overlay: - shard-iclb: [SKIP][155] ([i915#5519]) -> [PASS][156] [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-iclb7/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-iclb8/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html * igt@perf_pmu@module-unload: - {shard-tglu}: [DMESG-WARN][157] ([i915#2867]) -> [PASS][158] [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-tglu-3/igt@perf_pmu@module-unload.html [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-tglu-3/igt@perf_pmu@module-unload.html #### Warnings #### * igt@gem_exec_balancer@parallel-ordering: - shard-iclb: [SKIP][159] ([i915#4525]) -> [FAIL][160] ([i915#6117]) [159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-iclb8/igt@gem_exec_balancer@parallel-ordering.html [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf: - shard-iclb: [SKIP][161] ([i915#2920]) -> [SKIP][162] ([i915#658]) [161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-iclb1/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area: - shard-iclb: [SKIP][163] ([fdo#111068] / [i915#658]) -> [SKIP][164] ([i915#2920]) +2 similar issues [163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-iclb8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html * igt@kms_psr2_sf@plane-move-sf-dmg-area: - shard-iclb: [SKIP][165] ([i915#2920]) -> [SKIP][166] ([fdo#111068] / [i915#658]) [165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area.html [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-iclb1/igt@kms_psr2_sf@plane-move-sf-dmg-area.html * igt@perf@non-zero-reason: - shard-skl: [DMESG-FAIL][167] ([i915#1982]) -> [TIMEOUT][168] ([i915#6943]) [167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-skl1/igt@perf@non-zero-reason.html [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-skl5/igt@perf@non-zero-reason.html * igt@runner@aborted: - shard-apl: ([FAIL][169], [FAIL][170]) ([i915#3002] / [i915#4312]) -> ([FAIL][171], [FAIL][172], [FAIL][173], [FAIL][174]) ([i915#180] / [i915#3002] / [i915#4312]) [169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl8/igt@runner@aborted.html [170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12478/shard-apl8/igt@runner@aborted.html [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl1/igt@runner@aborted.html [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl8/igt@runner@aborted.html [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl8/igt@runner@aborted.html [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/shard-apl8/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302 [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307 [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312 [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542 [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644 [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054 [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132 [i915#1339]: https://gitlab.freedesktop.org/drm/intel/issues/1339 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804 [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 [i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681 [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705 [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846 [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856 [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867 [i915#2898]: https://gitlab.freedesktop.org/drm/intel/issues/2898 [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299 [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361 [i915#3371]: https://gitlab.freedesktop.org/drm/intel/issues/3371 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469 [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742 [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966 [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171 [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349 [i915#4386]: https://gitlab.freedesktop.org/drm/intel/issues/4386 [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525 [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565 [i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771 [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 [i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818 [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833 [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852 [i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854 [i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855 [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859 [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880 [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881 [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991 [i915#5072]: https://gitlab.freedesktop.org/drm/intel/issues/5072 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288 [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461 [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519 [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563 [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227 [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248 [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252 [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334 [i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344 [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433 [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497 [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621 [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768 [i915#6943]: https://gitlab.freedesktop.org/drm/intel/issues/6943 [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946 [i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953 [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116 [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118 [i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128 [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456 [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561 [i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 Build changes ------------- * Linux: CI_DRM_12478 -> Patchwork_111744v1 CI-20190529: 20190529 CI_DRM_12478: f5d2f00fe4daf65ecd6634dec39fbf66b44535e3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7085: 11af20de3877b23a244b816453bfc41d83591a15 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_111744v1: f5d2f00fe4daf65ecd6634dec39fbf66b44535e3 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v1/index.html [-- Attachment #2: Type: text/html, Size: 44625 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines 2022-12-07 17:36 [Intel-gfx] [PATCH 1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines Andrzej Hajda ` (2 preceding siblings ...) 2022-12-08 5:05 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork @ 2022-12-09 9:37 ` Tvrtko Ursulin 2022-12-09 12:05 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines (rev2) Patchwork ` (3 subsequent siblings) 7 siblings, 0 replies; 15+ messages in thread From: Tvrtko Ursulin @ 2022-12-09 9:37 UTC (permalink / raw) To: Andrzej Hajda, intel-gfx Cc: Chris Wilson, Daniel Vetter, Matthew Auld, Rodrigo Vivi, Nirmoy Das On 07/12/2022 17:36, Andrzej Hajda wrote: > In case of Gen12.50 video and compute engines, TLB_INV registers are > masked - to modify one bit, corresponding bit in upper half of the register > must be enabled, otherwise nothing happens. > > Fixes: 77fa9efc16a9 ("drm/i915/xehp: Create separate reg definitions for new MCR registers") Just a note that target wasn't strictly the only one to blame, but it is a good target to ensure proper backporting. > Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> > --- > This patch is simple enhancement of > 04aa64375f48 ("drm/i915: fix TLB invalidation for Gen12 video and compute engines") > for Gen12.5 which is added in dev branches. > --- > drivers/gpu/drm/i915/gt/intel_gt.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c > index d114347c004ee5..f0224b607aa4a7 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > @@ -1120,9 +1120,15 @@ static void mmio_invalidate_full(struct intel_gt *gt) > continue; > > if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { > + u32 val = BIT(engine->instance); > + > + if (engine->class == VIDEO_DECODE_CLASS || > + engine->class == VIDEO_ENHANCEMENT_CLASS || > + engine->class == COMPUTE_CLASS) > + val = _MASKED_BIT_ENABLE(val); > intel_gt_mcr_multicast_write_fw(gt, > xehp_regs[engine->class], > - BIT(engine->instance)); > + val); > } else { > rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); > if (!i915_mmio_reg_offset(rb.reg)) Triple checked against bspec. Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Regards, Tvrtko ^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines (rev2) 2022-12-07 17:36 [Intel-gfx] [PATCH 1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines Andrzej Hajda ` (3 preceding siblings ...) 2022-12-09 9:37 ` [Intel-gfx] [PATCH 1/2] " Tvrtko Ursulin @ 2022-12-09 12:05 ` Patchwork 2022-12-13 9:55 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines (rev3) Patchwork ` (2 subsequent siblings) 7 siblings, 0 replies; 15+ messages in thread From: Patchwork @ 2022-12-09 12:05 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines (rev2) URL : https://patchwork.freedesktop.org/series/111744/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/111744/revisions/2/mbox/ not applied Applying: drm/i915: fix TLB invalidation for Gen12.50 video and compute engines Applying: drm/i915: cleanup TLB invalidation code error: patch failed: drivers/gpu/drm/i915/gt/intel_gt.c:988 error: drivers/gpu/drm/i915/gt/intel_gt.c: patch does not apply error: Did you hand edit your patch? It does not apply to blobs recorded in its index. hint: Use 'git am --show-current-patch=diff' to see the failed patch Using index info to reconstruct a base tree... Patch failed at 0002 drm/i915: cleanup TLB invalidation code When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines (rev3) 2022-12-07 17:36 [Intel-gfx] [PATCH 1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines Andrzej Hajda ` (4 preceding siblings ...) 2022-12-09 12:05 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines (rev2) Patchwork @ 2022-12-13 9:55 ` Patchwork 2022-12-13 10:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-12-14 11:24 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 7 siblings, 0 replies; 15+ messages in thread From: Patchwork @ 2022-12-13 9:55 UTC (permalink / raw) To: Andrzej Hajda; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines (rev3) URL : https://patchwork.freedesktop.org/series/111744/ State : warning == Summary == Error: make htmldocs had i915 warnings ./drivers/gpu/drm/i915/display/intel_dsb.c:201: warning: Excess function parameter 'crtc_state' description in 'intel_dsb_reg_write' ./drivers/gpu/drm/i915/display/intel_dsb.c:201: warning: Function parameter or member 'dsb' not described in 'intel_dsb_reg_write' ./drivers/gpu/drm/i915/display/intel_dsb.c:201: warning: Excess function parameter 'crtc_state' description in 'intel_dsb_reg_write' ^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines (rev3) 2022-12-07 17:36 [Intel-gfx] [PATCH 1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines Andrzej Hajda ` (5 preceding siblings ...) 2022-12-13 9:55 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines (rev3) Patchwork @ 2022-12-13 10:15 ` Patchwork 2022-12-14 11:24 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 7 siblings, 0 replies; 15+ messages in thread From: Patchwork @ 2022-12-13 10:15 UTC (permalink / raw) To: Andrzej Hajda; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 5235 bytes --] == Series Details == Series: series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines (rev3) URL : https://patchwork.freedesktop.org/series/111744/ State : success == Summary == CI Bug Log - changes from CI_DRM_12501 -> Patchwork_111744v3 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/index.html Participating hosts (38 -> 41) ------------------------------ Additional (3): fi-skl-guc bat-rpls-1 bat-jsl-1 Known issues ------------ Here are the changes found in Patchwork_111744v3 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_lmem_swapping@basic: - fi-skl-guc: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4613]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/fi-skl-guc/igt@gem_lmem_swapping@basic.html * igt@i915_suspend@basic-s3-without-i915: - fi-rkl-11600: [PASS][2] -> [INCOMPLETE][3] ([i915#4817]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html * igt@kms_chamelium@hdmi-crc-fast: - fi-skl-guc: NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/fi-skl-guc/igt@kms_chamelium@hdmi-crc-fast.html * igt@kms_psr@sprite_plane_onoff: - fi-skl-guc: NOTRUN -> [SKIP][5] ([fdo#109271]) +9 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/fi-skl-guc/igt@kms_psr@sprite_plane_onoff.html #### Possible fixes #### * igt@gem_exec_gttfill@basic: - fi-pnv-d510: [FAIL][6] ([i915#7229]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/fi-pnv-d510/igt@gem_exec_gttfill@basic.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/fi-pnv-d510/igt@gem_exec_gttfill@basic.html * igt@i915_selftest@live@migrate: - {bat-adlp-9}: [DMESG-FAIL][8] -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/bat-adlp-9/igt@i915_selftest@live@migrate.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/bat-adlp-9/igt@i915_selftest@live@migrate.html - {bat-adlp-6}: [DMESG-FAIL][10] -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/bat-adlp-6/igt@i915_selftest@live@migrate.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/bat-adlp-6/igt@i915_selftest@live@migrate.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867 [i915#3003]: https://gitlab.freedesktop.org/drm/intel/issues/3003 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817 [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621 [i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794 [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229 [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456 [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561 Build changes ------------- * Linux: CI_DRM_12501 -> Patchwork_111744v3 CI-20190529: 20190529 CI_DRM_12501: 1b38b5a419ab3d838b6ac95d22f1fe057fc8889d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7091: b8015f920c9f469d3733854263cb878373c1df51 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_111744v3: 1b38b5a419ab3d838b6ac95d22f1fe057fc8889d @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits fa0e6651d2b5 drm/i915: cleanup TLB invalidation code 7f2e0208920a drm/i915: fix TLB invalidation for Gen12.50 video and compute engines == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/index.html [-- Attachment #2: Type: text/html, Size: 4862 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines (rev3) 2022-12-07 17:36 [Intel-gfx] [PATCH 1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines Andrzej Hajda ` (6 preceding siblings ...) 2022-12-13 10:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2022-12-14 11:24 ` Patchwork 7 siblings, 0 replies; 15+ messages in thread From: Patchwork @ 2022-12-14 11:24 UTC (permalink / raw) To: Andrzej Hajda; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 34623 bytes --] == Series Details == Series: series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines (rev3) URL : https://patchwork.freedesktop.org/series/111744/ State : success == Summary == CI Bug Log - changes from CI_DRM_12501_full -> Patchwork_111744v3_full ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (14 -> 14) ------------------------------ No changes in participating hosts New tests --------- New tests have been introduced between CI_DRM_12501_full and Patchwork_111744v3_full: ### New IGT tests (25) ### * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-linear-to-linear: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-linear-to-x: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-linear-to-y: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-linear-to-y-rc_ccs: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-linear-to-y-rc_ccs-cc: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-x-to-linear: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-x-to-x: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-x-to-y: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-x-to-y-rc_ccs: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-x-to-y-rc_ccs-cc: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-y-rc_ccs-cc-to-linear: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-y-rc_ccs-cc-to-x: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-y-rc_ccs-cc-to-y: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-y-rc_ccs-cc-to-y-rc_ccs: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-y-rc_ccs-cc-to-y-rc_ccs-cc: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-y-rc_ccs-to-linear: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-y-rc_ccs-to-x: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-y-rc_ccs-to-y: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-y-rc_ccs-to-y-rc_ccs: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-y-rc_ccs-to-y-rc_ccs-cc: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-y-to-linear: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-y-to-x: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-y-to-y: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-y-to-y-rc_ccs: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-1-pipe-d-y-to-y-rc_ccs-cc: - Statuses : 1 pass(s) - Exec time: [0.0] s Known issues ------------ Here are the changes found in Patchwork_111744v3_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: [PASS][1] -> [FAIL][2] ([i915#2842]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-glk5/igt@gem_exec_fair@basic-none@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-glk8/igt@gem_exec_fair@basic-none@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][3] ([i915#2842]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-iclb1/igt@gem_exec_fair@basic-none@vcs1.html * igt@gen9_exec_parse@allowed-single: - shard-glk: [PASS][4] -> [DMESG-WARN][5] ([i915#5566] / [i915#716]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-glk3/igt@gen9_exec_parse@allowed-single.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-glk3/igt@gen9_exec_parse@allowed-single.html * igt@i915_selftest@live@hangcheck: - shard-tglb: [PASS][6] -> [DMESG-WARN][7] ([i915#5591]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-tglb5/igt@i915_selftest@live@hangcheck.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-tglb3/igt@i915_selftest@live@hangcheck.html * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1: - shard-glk: [PASS][8] -> [FAIL][9] ([i915#2521]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-glk2/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-glk9/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1.html * igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs: - shard-skl: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#3886]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-skl1/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_rc_ccs: - shard-skl: NOTRUN -> [SKIP][11] ([fdo#109271]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-skl4/igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_rc_ccs.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1: - shard-skl: [PASS][12] -> [FAIL][13] ([i915#79]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html * igt@kms_flip@flip-vs-suspend-interruptible@b-dp1: - shard-apl: [PASS][14] -> [DMESG-WARN][15] ([i915#180]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html * igt@kms_flip@flip-vs-suspend@c-edp1: - shard-iclb: [PASS][16] -> [DMESG-WARN][17] ([i915#2867]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-iclb3/igt@kms_flip@flip-vs-suspend@c-edp1.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-iclb3/igt@kms_flip@flip-vs-suspend@c-edp1.html * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1: - shard-skl: [PASS][18] -> [FAIL][19] ([i915#2122]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][20] ([i915#2672]) +3 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode: - shard-iclb: NOTRUN -> [SKIP][21] ([i915#2587] / [i915#2672]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][22] ([i915#3555]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][23] ([i915#2672] / [i915#3555]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode.html * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1: - shard-iclb: [PASS][24] -> [SKIP][25] ([i915#5235]) +2 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-iclb3/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-iclb2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1.html * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb: [PASS][26] -> [SKIP][27] ([fdo#109441]) +1 similar issue [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-iclb5/igt@kms_psr@psr2_cursor_plane_move.html * igt@kms_psr_stress_test@flip-primary-invalidate-overlay: - shard-skl: [PASS][28] -> [SKIP][29] ([fdo#109271]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-skl7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-skl4/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html - shard-iclb: [PASS][30] -> [SKIP][31] ([i915#5519]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-iclb7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-iclb7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html #### Possible fixes #### * igt@debugfs_test@read_all_entries_display_on: - shard-skl: [DMESG-WARN][32] ([i915#1982]) -> [PASS][33] +3 similar issues [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-skl6/igt@debugfs_test@read_all_entries_display_on.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-skl7/igt@debugfs_test@read_all_entries_display_on.html * igt@drm_read@short-buffer-block: - {shard-rkl}: [SKIP][34] ([i915#4098]) -> [PASS][35] +1 similar issue [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-rkl-1/igt@drm_read@short-buffer-block.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-rkl-6/igt@drm_read@short-buffer-block.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-tglb: [FAIL][36] ([i915#6268]) -> [PASS][37] [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-tglb2/igt@gem_ctx_exec@basic-nohangcheck.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-tglb5/igt@gem_ctx_exec@basic-nohangcheck.html * igt@gem_ctx_isolation@preservation-s3@vcs0: - {shard-rkl}: [FAIL][38] ([i915#7673]) -> [PASS][39] +3 similar issues [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-rkl-4/igt@gem_ctx_isolation@preservation-s3@vcs0.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-rkl-5/igt@gem_ctx_isolation@preservation-s3@vcs0.html * igt@gem_ctx_persistence@hang: - {shard-rkl}: [SKIP][40] ([i915#6252]) -> [PASS][41] [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-rkl-5/igt@gem_ctx_persistence@hang.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-rkl-1/igt@gem_ctx_persistence@hang.html * igt@gem_ctx_shared@q-in-order@rcs0: - {shard-rkl}: [FAIL][42] ([i915#7672]) -> [PASS][43] +3 similar issues [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-rkl-4/igt@gem_ctx_shared@q-in-order@rcs0.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-rkl-5/igt@gem_ctx_shared@q-in-order@rcs0.html * igt@gem_eio@in-flight-contexts-1us: - shard-snb: [FAIL][44] ([i915#4409]) -> [PASS][45] [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-snb5/igt@gem_eio@in-flight-contexts-1us.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-snb4/igt@gem_eio@in-flight-contexts-1us.html * igt@gem_eio@in-flight-suspend: - {shard-dg1}: [FAIL][46] ([i915#7052]) -> [PASS][47] [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-dg1-12/igt@gem_eio@in-flight-suspend.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-dg1-13/igt@gem_eio@in-flight-suspend.html * igt@gem_exec_balancer@parallel-keep-submit-fence: - shard-iclb: [SKIP][48] ([i915#4525]) -> [PASS][49] [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-iclb3/igt@gem_exec_balancer@parallel-keep-submit-fence.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-iclb2/igt@gem_exec_balancer@parallel-keep-submit-fence.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [FAIL][50] ([i915#2842]) -> [PASS][51] +1 similar issue [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [FAIL][52] ([i915#2842]) -> [PASS][53] [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-glk9/igt@gem_exec_fair@basic-throttle@rcs0.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_exec_reloc@basic-gtt-wc: - {shard-rkl}: [SKIP][54] ([i915#3281]) -> [PASS][55] [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-rkl-4/igt@gem_exec_reloc@basic-gtt-wc.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-rkl-5/igt@gem_exec_reloc@basic-gtt-wc.html * igt@gem_mmap_wc@set-cache-level: - {shard-rkl}: [SKIP][56] ([i915#1850]) -> [PASS][57] [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-rkl-2/igt@gem_mmap_wc@set-cache-level.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-rkl-6/igt@gem_mmap_wc@set-cache-level.html * igt@gem_partial_pwrite_pread@writes-after-reads-uncached: - {shard-rkl}: [SKIP][58] ([i915#3282]) -> [PASS][59] +1 similar issue [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-rkl-4/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-rkl-5/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html * igt@gen9_exec_parse@bb-start-param: - {shard-rkl}: [SKIP][60] ([i915#2527]) -> [PASS][61] [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-rkl-4/igt@gen9_exec_parse@bb-start-param.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-rkl-5/igt@gen9_exec_parse@bb-start-param.html * igt@i915_pm_rpm@modeset-non-lpsp: - {shard-dg1}: [SKIP][62] ([i915#1397]) -> [PASS][63] [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-dg1-14/igt@i915_pm_rpm@modeset-non-lpsp.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-dg1-16/igt@i915_pm_rpm@modeset-non-lpsp.html * igt@i915_selftest@live@gt_heartbeat: - shard-skl: [DMESG-FAIL][64] ([i915#5334]) -> [PASS][65] [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-skl1/igt@i915_selftest@live@gt_heartbeat.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-skl1/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1: - shard-skl: [FAIL][66] ([i915#2521]) -> [PASS][67] +2 similar issues [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-skl7/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-skl7/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions: - shard-glk: [FAIL][68] ([i915#2346]) -> [PASS][69] [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html * igt@kms_flip@flip-vs-expired-vblank@a-edp1: - shard-skl: [FAIL][70] ([i915#79]) -> [PASS][71] +1 similar issue [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html * igt@kms_flip@flip-vs-expired-vblank@d-edp1: - shard-tglb: [FAIL][72] ([i915#79]) -> [PASS][73] [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-tglb1/igt@kms_flip@flip-vs-expired-vblank@d-edp1.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-tglb1/igt@kms_flip@flip-vs-expired-vblank@d-edp1.html * igt@kms_flip@plain-flip-ts-check@a-edp1: - shard-skl: [FAIL][74] ([i915#2122]) -> [PASS][75] [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-skl6/igt@kms_flip@plain-flip-ts-check@a-edp1.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-skl7/igt@kms_flip@plain-flip-ts-check@a-edp1.html * igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary: - {shard-rkl}: [SKIP][76] ([i915#1849] / [i915#4098]) -> [PASS][77] +17 similar issues [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html * igt@kms_plane@pixel-format@pipe-a-planes: - {shard-rkl}: [SKIP][78] ([i915#1849] / [i915#3558]) -> [PASS][79] +1 similar issue [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-rkl-2/igt@kms_plane@pixel-format@pipe-a-planes.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-rkl-6/igt@kms_plane@pixel-format@pipe-a-planes.html * igt@kms_psr@primary_render: - {shard-rkl}: [SKIP][80] ([i915#1072]) -> [PASS][81] [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-rkl-1/igt@kms_psr@primary_render.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-rkl-6/igt@kms_psr@primary_render.html * igt@kms_psr@psr2_primary_render: - shard-iclb: [SKIP][82] ([fdo#109441]) -> [PASS][83] +1 similar issue [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-iclb1/igt@kms_psr@psr2_primary_render.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-iclb2/igt@kms_psr@psr2_primary_render.html * igt@kms_psr_stress_test@flip-primary-invalidate-overlay: - {shard-rkl}: [SKIP][84] ([i915#5461]) -> [PASS][85] [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-rkl-1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-rkl-6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html * igt@kms_psr_stress_test@invalidate-primary-flip-overlay: - shard-tglb: [SKIP][86] ([i915#5519]) -> [PASS][87] [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-tglb6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-tglb7/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html * igt@kms_rotation_crc@primary-rotation-90: - {shard-rkl}: [SKIP][88] ([i915#1845] / [i915#4098]) -> [PASS][89] +25 similar issues [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-rkl-1/igt@kms_rotation_crc@primary-rotation-90.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-rkl-6/igt@kms_rotation_crc@primary-rotation-90.html * igt@kms_universal_plane@disable-primary-vs-flip-pipe-b: - {shard-rkl}: [SKIP][90] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][91] [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-rkl-1/igt@kms_universal_plane@disable-primary-vs-flip-pipe-b.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-rkl-6/igt@kms_universal_plane@disable-primary-vs-flip-pipe-b.html #### Warnings #### * igt@gem_exec_balancer@parallel-ordering: - shard-iclb: [SKIP][92] ([i915#4525]) -> [FAIL][93] ([i915#6117]) [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-iclb6/igt@gem_exec_balancer@parallel-ordering.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf: - shard-iclb: [SKIP][94] ([i915#658]) -> [SKIP][95] ([i915#2920]) +3 similar issues [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-iclb3/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html * igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf: - shard-iclb: [SKIP][96] ([i915#2920]) -> [SKIP][97] ([i915#658]) [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-iclb5/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html * igt@kms_psr2_sf@plane-move-sf-dmg-area: - shard-iclb: [SKIP][98] ([fdo#111068] / [i915#658]) -> [SKIP][99] ([i915#2920]) [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-iclb6/igt@kms_psr2_sf@plane-move-sf-dmg-area.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area.html * igt@runner@aborted: - shard-apl: ([FAIL][100], [FAIL][101], [FAIL][102]) ([fdo#109271] / [i915#3002] / [i915#4312]) -> ([FAIL][103], [FAIL][104], [FAIL][105], [FAIL][106]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312]) [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-apl2/igt@runner@aborted.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-apl3/igt@runner@aborted.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12501/shard-apl6/igt@runner@aborted.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-apl3/igt@runner@aborted.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-apl8/igt@runner@aborted.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-apl3/igt@runner@aborted.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/shard-apl1/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279 [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307 [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308 [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309 [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644 [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054 [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722 [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 [i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850 [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681 [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705 [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280 [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856 [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867 [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116 [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299 [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469 [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 [i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558 [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742 [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804 [i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387 [i915#4409]: https://gitlab.freedesktop.org/drm/intel/issues/4409 [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288 [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461 [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519 [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566 [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117 [i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245 [i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247 [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248 [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252 [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268 [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335 [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433 [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497 [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590 [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768 [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946 [i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037 [i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052 [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116 [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456 [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561 [i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651 [i915#7672]: https://gitlab.freedesktop.org/drm/intel/issues/7672 [i915#7673]: https://gitlab.freedesktop.org/drm/intel/issues/7673 [i915#7679]: https://gitlab.freedesktop.org/drm/intel/issues/7679 [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 Build changes ------------- * Linux: CI_DRM_12501 -> Patchwork_111744v3 CI-20190529: 20190529 CI_DRM_12501: 1b38b5a419ab3d838b6ac95d22f1fe057fc8889d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7091: b8015f920c9f469d3733854263cb878373c1df51 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_111744v3: 1b38b5a419ab3d838b6ac95d22f1fe057fc8889d @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111744v3/index.html [-- Attachment #2: Type: text/html, Size: 33535 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines
@ 2022-12-13 12:39 Tvrtko Ursulin
0 siblings, 0 replies; 15+ messages in thread
From: Tvrtko Ursulin @ 2022-12-13 12:39 UTC (permalink / raw)
To: Intel-gfx, dri-devel; +Cc: Andrzej Hajda
From: Andrzej Hajda <andrzej.hajda@intel.com>
In case of Gen12.50 video and compute engines, TLB_INV registers are
masked - to modify one bit, corresponding bit in upper half of the register
must be enabled, otherwise nothing happens.
Fixes: 77fa9efc16a9 ("drm/i915/xehp: Create separate reg definitions for new MCR registers")
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 63f95c5f3614..7eeee5a7cb33 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1100,9 +1100,15 @@ static void mmio_invalidate_full(struct intel_gt *gt)
continue;
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+ u32 val = BIT(engine->instance);
+
+ if (engine->class == VIDEO_DECODE_CLASS ||
+ engine->class == VIDEO_ENHANCEMENT_CLASS ||
+ engine->class == COMPUTE_CLASS)
+ val = _MASKED_BIT_ENABLE(val);
intel_gt_mcr_multicast_write_fw(gt,
xehp_regs[engine->class],
- BIT(engine->instance));
+ val);
} else {
rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
if (!i915_mmio_reg_offset(rb.reg))
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in threadend of thread, other threads:[~2022-12-14 11:25 UTC | newest] Thread overview: 15+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-12-07 17:36 [Intel-gfx] [PATCH 1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines Andrzej Hajda 2022-12-07 17:36 ` [Intel-gfx] [PATCH 2/2] drm/i915: cleanup TLB invalidation code Andrzej Hajda 2022-12-09 10:16 ` Tvrtko Ursulin 2022-12-09 11:33 ` Andrzej Hajda 2022-12-09 12:04 ` Tvrtko Ursulin 2022-12-09 12:35 ` Tvrtko Ursulin 2022-12-13 9:21 ` [Intel-gfx] [PATCH] " Andrzej Hajda 2022-12-07 20:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines Patchwork 2022-12-08 5:05 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2022-12-09 9:37 ` [Intel-gfx] [PATCH 1/2] " Tvrtko Ursulin 2022-12-09 12:05 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines (rev2) Patchwork 2022-12-13 9:55 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines (rev3) Patchwork 2022-12-13 10:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-12-14 11:24 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork -- strict thread matches above, loose matches on Subject: below -- 2022-12-13 12:39 [Intel-gfx] [PATCH 1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines Tvrtko Ursulin
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