[Intel-gfx] [RFC] drm/i915/display: Move cdclk checks to atomic check

[Intel-gfx] [RFC] drm/i915/display: Move cdclk checks to atomic check

[Anusha Srivatsa]

i915 has squashing for DG2 and crawling for ADLP.
Moving the checks to atomic check phase so
at a later phase we know how the cdclk changes.

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 49 +++++++++++++---------
 drivers/gpu/drm/i915/i915_drv.h            | 11 +++++
 2 files changed, 41 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 639a64733f61..9382dd24d889 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1707,9 +1707,27 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 		return;
 	}
 
-	if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
-		if (dev_priv->cdclk.hw.vco != vco)
-			adlp_cdclk_pll_crawl(dev_priv, vco);
+	if (DISPLAY_VER(dev_priv) >= 12) {
+		int i = 0;
+		u32 squash_ctl = 0;
+		struct cdclk_steps *cdclk_steps = dev_priv->cdclk.steps;
+
+		for (i = 0; i < CDCLK_ACTIONS; i++) {
+			switch (cdclk_steps[i].action) {
+			case CRAWL:
+				adlp_cdclk_pll_crawl(dev_priv, vco);
+				break;
+			case SQUASH:
+				waveform =  cdclk_squash_waveform(dev_priv, cdclk_steps[i].cdclk);
+				clock = vco / 2;
+				squash_ctl = CDCLK_SQUASH_ENABLE |
+				CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
+				intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
+				break;
+			default:
+				break;
+			}
+		}
 	} else if (DISPLAY_VER(dev_priv) >= 11) {
 		if (dev_priv->cdclk.hw.vco != 0 &&
 		    dev_priv->cdclk.hw.vco != vco)
@@ -1726,22 +1744,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 			bxt_de_pll_enable(dev_priv, vco);
 	}
 
-	waveform = cdclk_squash_waveform(dev_priv, cdclk);
-
-	if (waveform)
-		clock = vco / 2;
-	else
-		clock = cdclk;
-
-	if (has_cdclk_squasher(dev_priv)) {
-		u32 squash_ctl = 0;
-
-		if (waveform)
-			squash_ctl = CDCLK_SQUASH_ENABLE |
-				CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
-
-		intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
-	}
+	clock = cdclk;
 
 	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
 		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
@@ -1934,6 +1937,7 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
 				  const struct intel_cdclk_config *a,
 				  const struct intel_cdclk_config *b)
 {
+	struct cdclk_steps *cdclk_transition = dev_priv->cdclk.steps;
 	int a_div, b_div;
 
 	if (!HAS_CDCLK_CRAWL(dev_priv))
@@ -1946,6 +1950,9 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
 	a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
 	b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
 
+	cdclk_transition[0].action = CRAWL;
+	cdclk_transition[0].cdclk = b->cdclk;
+
 	return a->vco != 0 && b->vco != 0 &&
 		a->vco != b->vco &&
 		a_div == b_div &&
@@ -1956,6 +1963,7 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
 				   const struct intel_cdclk_config *a,
 				   const struct intel_cdclk_config *b)
 {
+	struct cdclk_steps *cdclk_transition = dev_priv->cdclk.steps;
 	/*
 	 * FIXME should store a bit more state in intel_cdclk_config
 	 * to differentiate squasher vs. cd2x divider properly. For
@@ -1965,6 +1973,9 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
 	if (!has_cdclk_squasher(dev_priv))
 		return false;
 
+	cdclk_transition[0].action = SQUASH;
+	cdclk_transition[0].cdclk = b->cdclk;
+
 	return a->cdclk != b->cdclk &&
 		a->vco != 0 &&
 		a->vco == b->vco &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ae7dc7862b5d..c03299253b81 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -117,6 +117,12 @@
 
 struct drm_i915_gem_object;
 
+enum cdclk_actions {
+	SQUASH = 0,
+	CRAWL,
+	CDCLK_ACTIONS
+};
+
 /* Threshold == 5 for long IRQs, 50 for short */
 #define HPD_STORM_DEFAULT_THRESHOLD 50
 
@@ -782,6 +788,11 @@ struct drm_i915_private {
 		const struct intel_cdclk_vals *table;
 
 		struct intel_global_obj obj;
+
+		struct cdclk_steps {
+			enum cdclk_actions action;
+			u32 cdclk;
+		} steps[CDCLK_ACTIONS];
 	} cdclk;
 
 	struct {
-- 
2.25.1

Re: [Intel-gfx] [RFC] drm/i915/display: Move cdclk checks to atomic check

[Jani Nikula]

On Thu, 09 Dec 2021, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
> i915 has squashing for DG2 and crawling for ADLP.
> Moving the checks to atomic check phase so
> at a later phase we know how the cdclk changes.

Just some high level comments:

- Functions named intel_cdclk_can_foo() must *not* change the state,
  that's unexpected and surprising.

- There's a bunch of state handling already for cdclk, please don't just
  dump new state in drm_i915_private, outside of the existing states. In
  particular, storing yet another copy of cdclk is suspicious.

- Please don't add short stuff like CRAWL and SQUASH to our module
  namespace.


BR,
Jani.


>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 49 +++++++++++++---------
>  drivers/gpu/drm/i915/i915_drv.h            | 11 +++++
>  2 files changed, 41 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 639a64733f61..9382dd24d889 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1707,9 +1707,27 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  		return;
>  	}
>  
> -	if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
> -		if (dev_priv->cdclk.hw.vco != vco)
> -			adlp_cdclk_pll_crawl(dev_priv, vco);
> +	if (DISPLAY_VER(dev_priv) >= 12) {
> +		int i = 0;
> +		u32 squash_ctl = 0;
> +		struct cdclk_steps *cdclk_steps = dev_priv->cdclk.steps;
> +
> +		for (i = 0; i < CDCLK_ACTIONS; i++) {
> +			switch (cdclk_steps[i].action) {
> +			case CRAWL:
> +				adlp_cdclk_pll_crawl(dev_priv, vco);
> +				break;
> +			case SQUASH:
> +				waveform =  cdclk_squash_waveform(dev_priv, cdclk_steps[i].cdclk);
> +				clock = vco / 2;
> +				squash_ctl = CDCLK_SQUASH_ENABLE |
> +				CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
> +				intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
> +				break;
> +			default:
> +				break;
> +			}
> +		}
>  	} else if (DISPLAY_VER(dev_priv) >= 11) {
>  		if (dev_priv->cdclk.hw.vco != 0 &&
>  		    dev_priv->cdclk.hw.vco != vco)
> @@ -1726,22 +1744,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  			bxt_de_pll_enable(dev_priv, vco);
>  	}
>  
> -	waveform = cdclk_squash_waveform(dev_priv, cdclk);
> -
> -	if (waveform)
> -		clock = vco / 2;
> -	else
> -		clock = cdclk;
> -
> -	if (has_cdclk_squasher(dev_priv)) {
> -		u32 squash_ctl = 0;
> -
> -		if (waveform)
> -			squash_ctl = CDCLK_SQUASH_ENABLE |
> -				CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
> -
> -		intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
> -	}
> +	clock = cdclk;
>  
>  	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
>  		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
> @@ -1934,6 +1937,7 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
>  				  const struct intel_cdclk_config *a,
>  				  const struct intel_cdclk_config *b)
>  {
> +	struct cdclk_steps *cdclk_transition = dev_priv->cdclk.steps;
>  	int a_div, b_div;
>  
>  	if (!HAS_CDCLK_CRAWL(dev_priv))
> @@ -1946,6 +1950,9 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
>  	a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
>  	b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
>  
> +	cdclk_transition[0].action = CRAWL;
> +	cdclk_transition[0].cdclk = b->cdclk;
> +
>  	return a->vco != 0 && b->vco != 0 &&
>  		a->vco != b->vco &&
>  		a_div == b_div &&
> @@ -1956,6 +1963,7 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
>  				   const struct intel_cdclk_config *a,
>  				   const struct intel_cdclk_config *b)
>  {
> +	struct cdclk_steps *cdclk_transition = dev_priv->cdclk.steps;
>  	/*
>  	 * FIXME should store a bit more state in intel_cdclk_config
>  	 * to differentiate squasher vs. cd2x divider properly. For
> @@ -1965,6 +1973,9 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
>  	if (!has_cdclk_squasher(dev_priv))
>  		return false;
>  
> +	cdclk_transition[0].action = SQUASH;
> +	cdclk_transition[0].cdclk = b->cdclk;
> +
>  	return a->cdclk != b->cdclk &&
>  		a->vco != 0 &&
>  		a->vco == b->vco &&
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ae7dc7862b5d..c03299253b81 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -117,6 +117,12 @@
>  
>  struct drm_i915_gem_object;
>  
> +enum cdclk_actions {
> +	SQUASH = 0,
> +	CRAWL,
> +	CDCLK_ACTIONS
> +};
> +
>  /* Threshold == 5 for long IRQs, 50 for short */
>  #define HPD_STORM_DEFAULT_THRESHOLD 50
>  
> @@ -782,6 +788,11 @@ struct drm_i915_private {
>  		const struct intel_cdclk_vals *table;
>  
>  		struct intel_global_obj obj;
> +
> +		struct cdclk_steps {
> +			enum cdclk_actions action;
> +			u32 cdclk;
> +		} steps[CDCLK_ACTIONS];
>  	} cdclk;
>  
>  	struct {

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [RFC] drm/i915/display: Move cdclk checks to atomic check

[Srivatsa, Anusha]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Friday, December 10, 2021 4:17 PM
> To: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel-
> gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [RFC] drm/i915/display: Move cdclk checks to atomic
> check
> 
> On Thu, 09 Dec 2021, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
> > i915 has squashing for DG2 and crawling for ADLP.
> > Moving the checks to atomic check phase so at a later phase we know
> > how the cdclk changes.
> 
> Just some high level comments:
> 
> - Functions named intel_cdclk_can_foo() must *not* change the state,
>   that's unexpected and surprising.
> 
> - There's a bunch of state handling already for cdclk, please don't just
>   dump new state in drm_i915_private, outside of the existing states. In
>   particular, storing yet another copy of cdclk is suspicious.
> 
> - Please don't add short stuff like CRAWL and SQUASH to our module
>   namespace.
> 
Will keep in mind for hopefully a better non-RFC version. Thanks for the feedback.

Anusha
> BR,
> Jani.
> 
> 
> >
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cdclk.c | 49 +++++++++++++---------
> >  drivers/gpu/drm/i915/i915_drv.h            | 11 +++++
> >  2 files changed, 41 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 639a64733f61..9382dd24d889 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1707,9 +1707,27 @@ static void bxt_set_cdclk(struct
> drm_i915_private *dev_priv,
> >  		return;
> >  	}
> >
> > -	if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 &&
> vco > 0) {
> > -		if (dev_priv->cdclk.hw.vco != vco)
> > -			adlp_cdclk_pll_crawl(dev_priv, vco);
> > +	if (DISPLAY_VER(dev_priv) >= 12) {
> > +		int i = 0;
> > +		u32 squash_ctl = 0;
> > +		struct cdclk_steps *cdclk_steps = dev_priv->cdclk.steps;
> > +
> > +		for (i = 0; i < CDCLK_ACTIONS; i++) {
> > +			switch (cdclk_steps[i].action) {
> > +			case CRAWL:
> > +				adlp_cdclk_pll_crawl(dev_priv, vco);
> > +				break;
> > +			case SQUASH:
> > +				waveform =
> cdclk_squash_waveform(dev_priv, cdclk_steps[i].cdclk);
> > +				clock = vco / 2;
> > +				squash_ctl = CDCLK_SQUASH_ENABLE |
> > +				CDCLK_SQUASH_WINDOW_SIZE(0xf) |
> waveform;
> > +				intel_de_write(dev_priv,
> CDCLK_SQUASH_CTL, squash_ctl);
> > +				break;
> > +			default:
> > +				break;
> > +			}
> > +		}
> >  	} else if (DISPLAY_VER(dev_priv) >= 11) {
> >  		if (dev_priv->cdclk.hw.vco != 0 &&
> >  		    dev_priv->cdclk.hw.vco != vco)
> > @@ -1726,22 +1744,7 @@ static void bxt_set_cdclk(struct
> drm_i915_private *dev_priv,
> >  			bxt_de_pll_enable(dev_priv, vco);
> >  	}
> >
> > -	waveform = cdclk_squash_waveform(dev_priv, cdclk);
> > -
> > -	if (waveform)
> > -		clock = vco / 2;
> > -	else
> > -		clock = cdclk;
> > -
> > -	if (has_cdclk_squasher(dev_priv)) {
> > -		u32 squash_ctl = 0;
> > -
> > -		if (waveform)
> > -			squash_ctl = CDCLK_SQUASH_ENABLE |
> > -				CDCLK_SQUASH_WINDOW_SIZE(0xf) |
> waveform;
> > -
> > -		intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
> > -	}
> > +	clock = cdclk;
> >
> >  	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
> >  		bxt_cdclk_cd2x_pipe(dev_priv, pipe) | @@ -1934,6 +1937,7
> @@ static
> > bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
> >  				  const struct intel_cdclk_config *a,
> >  				  const struct intel_cdclk_config *b)  {
> > +	struct cdclk_steps *cdclk_transition = dev_priv->cdclk.steps;
> >  	int a_div, b_div;
> >
> >  	if (!HAS_CDCLK_CRAWL(dev_priv))
> > @@ -1946,6 +1950,9 @@ static bool intel_cdclk_can_crawl(struct
> drm_i915_private *dev_priv,
> >  	a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
> >  	b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
> >
> > +	cdclk_transition[0].action = CRAWL;
> > +	cdclk_transition[0].cdclk = b->cdclk;
> > +
> >  	return a->vco != 0 && b->vco != 0 &&
> >  		a->vco != b->vco &&
> >  		a_div == b_div &&
> > @@ -1956,6 +1963,7 @@ static bool intel_cdclk_can_squash(struct
> drm_i915_private *dev_priv,
> >  				   const struct intel_cdclk_config *a,
> >  				   const struct intel_cdclk_config *b)  {
> > +	struct cdclk_steps *cdclk_transition = dev_priv->cdclk.steps;
> >  	/*
> >  	 * FIXME should store a bit more state in intel_cdclk_config
> >  	 * to differentiate squasher vs. cd2x divider properly. For @@
> > -1965,6 +1973,9 @@ static bool intel_cdclk_can_squash(struct
> drm_i915_private *dev_priv,
> >  	if (!has_cdclk_squasher(dev_priv))
> >  		return false;
> >
> > +	cdclk_transition[0].action = SQUASH;
> > +	cdclk_transition[0].cdclk = b->cdclk;
> > +
> >  	return a->cdclk != b->cdclk &&
> >  		a->vco != 0 &&
> >  		a->vco == b->vco &&
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index ae7dc7862b5d..c03299253b81
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -117,6 +117,12 @@
> >
> >  struct drm_i915_gem_object;
> >
> > +enum cdclk_actions {
> > +	SQUASH = 0,
> > +	CRAWL,
> > +	CDCLK_ACTIONS
> > +};
> > +
> >  /* Threshold == 5 for long IRQs, 50 for short */  #define
> > HPD_STORM_DEFAULT_THRESHOLD 50
> >
> > @@ -782,6 +788,11 @@ struct drm_i915_private {
> >  		const struct intel_cdclk_vals *table;
> >
> >  		struct intel_global_obj obj;
> > +
> > +		struct cdclk_steps {
> > +			enum cdclk_actions action;
> > +			u32 cdclk;
> > +		} steps[CDCLK_ACTIONS];
> >  	} cdclk;
> >
> >  	struct {
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: Move cdclk checks to atomic check

[Patchwork]

== Series Details ==

Series: drm/i915/display: Move cdclk checks to atomic check
URL   : https://patchwork.freedesktop.org/series/97850/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Move cdclk checks to atomic check

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4129 bytes --]

== Series Details ==

Series: drm/i915/display: Move cdclk checks to atomic check
URL   : https://patchwork.freedesktop.org/series/97850/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10988 -> Patchwork_21819
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_21819 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_21819, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21819/index.html

Participating hosts (45 -> 34)
------------------------------

  Missing    (11): fi-ilk-m540 bat-dg1-6 fi-tgl-u2 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 bat-jsl-2 fi-bdw-samus 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_21819:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_suspend@basic-s0:
    - fi-rkl-guc:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/fi-rkl-guc/igt@gem_exec_suspend@basic-s0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21819/fi-rkl-guc/igt@gem_exec_suspend@basic-s0.html

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-guc:         [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21819/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html

  * igt@runner@aborted:
    - fi-rkl-11600:       NOTRUN -> [FAIL][5]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21819/fi-rkl-11600/igt@runner@aborted.html

  
Known issues
------------

  Here are the changes found in Patchwork_21819 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_flink_basic@bad-flink:
    - fi-skl-6600u:       [PASS][6] -> [FAIL][7] ([i915#4547])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21819/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-cml-u2:          [PASS][8] -> [DMESG-WARN][9] ([i915#4269])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21819/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html

  * igt@runner@aborted:
    - fi-tgl-1115g4:      NOTRUN -> [FAIL][10] ([i915#4679])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21819/fi-tgl-1115g4/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
  [i915#4679]: https://gitlab.freedesktop.org/drm/intel/issues/4679


Build changes
-------------

  * Linux: CI_DRM_10988 -> Patchwork_21819

  CI-20190529: 20190529
  CI_DRM_10988: 24a4093e85c578905d39ebe14225dbeb5b6f07d5 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6305: 136258e86a093fdb50a7a341de1c09ac9a076fea @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21819: 4af753732c4bfd99be3945b5dd2a48e8d0df5f09 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4af753732c4b drm/i915/display: Move cdclk checks to atomic check

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21819/index.html

[-- Attachment #2: Type: text/html, Size: 4639 bytes --]