From: "Michal Wajdeczko" <michal.wajdeczko@intel.com>
To: intel-gfx@lists.freedesktop.org,
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Subject: Re: [PATCH v2 1/2] drm/i915/guc: fix GuC suspend/resume
Date: Wed, 17 Oct 2018 18:40:50 +0200 [thread overview]
Message-ID: <op.zq1factixaggs7@mwajdecz-mobl1.ger.corp.intel.com> (raw)
In-Reply-To: <20181016224648.2326-1-daniele.ceraolospurio@intel.com>
On Wed, 17 Oct 2018 00:46:47 +0200, Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
> The ENTER/EXIT_S_STATE actions queue the save/restore operation in GuC
> FW and then return, so waiting on the H2G is not enough to guarantee
> GuC is done.
> When all the processing is done, GuC writes 0 to scratch register 14,
> so we can poll on that. Note that GuC does not ensure that the value
> in the register is different from 0 while the action is in progress
> so we need to take care of that ourselves as well.
>
> v2: improve comment, return early on GuC error and improve error
> message (Michal)
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Michal
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next prev parent reply other threads:[~2018-10-17 16:40 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-16 22:46 [PATCH v2 1/2] drm/i915/guc: fix GuC suspend/resume Daniele Ceraolo Spurio
2018-10-16 22:46 ` [PATCH v2 2/2] HAX enable GuC for CI Daniele Ceraolo Spurio
2018-10-16 23:28 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/guc: fix GuC suspend/resume Patchwork
2018-10-16 23:53 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-10-17 16:40 ` Michal Wajdeczko [this message]
2018-10-17 20:32 ` [PATCH v2 1/2] " Chris Wilson
2018-11-26 14:51 ` Michal Wajdeczko
2018-11-27 19:34 ` Daniele Ceraolo Spurio
2018-11-28 19:55 ` Daniele Ceraolo Spurio
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