[PATCH] drm/i915/psr: ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR not valid for eDP

[PATCH] drm/i915/psr: ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR not valid for eDP

[Jouni Högander]

EDP1.5 specification says:

"Although defined for the PR function in DP Standard, the
ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR and DSC_DECODE_NOT_SUPPORTED_IN_PR
bits (DPCD 000B1h[3, 2], respectively) are DP-specific and are therefore
not used in eDP."

Stop using SYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR on eDP.

Cc: Jake Steinman <j@metarealtyinc.ca>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 00d0146b26002..c2bb2c4071527 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1698,8 +1698,11 @@ static inline bool compute_link_off_after_as_sdp_when_pr_active(struct intel_con
 
 static inline bool compute_disable_as_sdp_when_pr_active(struct intel_connector *connector)
 {
-	return !(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
-		 DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR);
+	struct intel_dp *intel_dp = intel_attached_dp(connector);
+
+	return intel_dp_is_edp(intel_dp) ? false :
+		!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
+		  DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR);
 }
 
 static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state,
-- 
2.43.0

Re: [PATCH] drm/i915/psr: ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR not valid for eDP

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/psr: Incomplete bypass of DP-specific PR bits for eDP
--

commit ec05ee2ea4b73ad11b56cabf344de75a2dc66b32
Author: Jouni Högander <jouni.hogander@intel.com>

drm/i915/psr: ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR not valid for eDP

This commit stops using the ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR bit for
eDP panels when computing AS SDP disablement. The eDP 1.5 specification
states that this bit and the DSC_DECODE_NOT_SUPPORTED_IN_PR bit are
DP-specific and not used in eDP.

> EDP1.5 specification says:
> 
> "Although defined for the PR function in DP Standard, the
> ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR and DSC_DECODE_NOT_SUPPORTED_IN_PR
> bits (DPCD 000B1h[3, 2], respectively) are DP-specific and are therefore
> not used in eDP."
> 
> Stop using SYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR on eDP.

[Severity: Medium]
Since the DSC decode capability bits are not used in eDP either, does
compute_pr_dsc_support() need to be updated to ignore them? Currently, it
reads the DP_PANEL_REPLAY_CAP_CAPABILITY register and extracts the DSC mode
which includes these DP-specific bits:

drivers/gpu/drm/i915/display/intel_psr.c:
compute_pr_dsc_support() {
	val = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)];
	pr_dsc_mode = REG_FIELD_GET8(DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK, val);
	...
}

Also, does intel_psr_pr_async_video_timing_supported() need the same eDP
bypass that is being added in this patch? It still unconditionally checks
the DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR bit:

drivers/gpu/drm/i915/display/intel_psr.c:
intel_psr_pr_async_video_timing_supported() {
	...
	u8 pr_cap = dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)];

	return (pr_support & DP_PANEL_REPLAY_SUPPORT) &&
		!(pr_cap & DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR);
}

Could this lead to incorrect capability detection on eDP panels if these
unused bits contain non-zero garbage values?

> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 872e253db1786..338a8dab75945 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1694,8 +1694,11 @@ static inline bool compute_link_off_after_as_sdp_when_pr_active(struct intel_con
>  
>  static inline bool compute_disable_as_sdp_when_pr_active(struct intel_connector *connector)
>  {
> -	return !(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> -		 DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR);
> +	struct intel_dp *intel_dp = intel_attached_dp(connector);
> +
> +	return intel_dp_is_edp(intel_dp) ? false :
> +		!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
> +		  DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR);
>  }
[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261007083443.647649-1-jouni.hogander@intel.com?part=1

✗ i915.CI.BAT: failure for drm/i915/psr: ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR not valid for eDP

[Patchwork]

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== Series Details ==

Series: drm/i915/psr: ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR not valid for eDP
URL   : https://patchwork.freedesktop.org/series/175652/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_19291 -> Patchwork_175652v1
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_175652v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_175652v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_175652v1/index.html

Participating hosts (39 -> 38)
------------------------------

  Missing    (1): bat-dg2-13 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_175652v1:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@coherency:
    - bat-arlh-3:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19291/bat-arlh-3/igt@i915_selftest@live@coherency.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_175652v1/bat-arlh-3/igt@i915_selftest@live@coherency.html

  
Known issues
------------

  Here are the changes found in Patchwork_175652v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live:
    - bat-arlh-3:         [PASS][3] -> [INCOMPLETE][4] ([i915#16547])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19291/bat-arlh-3/igt@i915_selftest@live.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_175652v1/bat-arlh-3/igt@i915_selftest@live.html

  
#### Possible fixes ####

  * igt@core_auth@basic-auth:
    - fi-bsw-n3050:       [DMESG-WARN][5] ([i915#17305]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19291/fi-bsw-n3050/igt@core_auth@basic-auth.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_175652v1/fi-bsw-n3050/igt@core_auth@basic-auth.html

  
  [i915#16547]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16547
  [i915#17305]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/17305


Build changes
-------------

  * Linux: CI_DRM_19291 -> Patchwork_175652v1

  CI-20190529: 20190529
  CI_DRM_19291: daeb062fc40f727fafefed080c6d12a5ad1d0d12 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_9131: 5e43e9df3a1581074f0de2bbeddd939ebd950b93 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_175652v1: daeb062fc40f727fafefed080c6d12a5ad1d0d12 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_175652v1/index.html

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Re: [PATCH] drm/i915/psr: ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR not valid for eDP

[Jake Steinman]

Hi Jouni,

Tested on the XPS 16 DA16260 (PTL, xe, 7.3-rc5, DA16260 PR quirk
removed, no other changes): Panel Replay SU is smooth with this patch.

Tested-by: Jake Steinman <j@metarealtyinc.ca>

Two things it leaves:

- The panel still judders for a few seconds after panel power-on
  (DPMS on). Holding PR inactive after power-on fixes that here; 8 s
  is clean, 3 s is not quite enough.

- No DC5 on a static screen while PR is active: 0 entries against 550
  on a static VT with the AS SDP suspended.

Since this panel needs a specific change for the first one anyway,
could the AS SDP also be suspended while vblank is disabled on panels
that handle it, as in the RFC? That keeps DC5/DC6 on a static screen.
https://lore.kernel.org/r/20261006220500.3417572-1-j@metarealtyinc.ca

If you respin, a Reported-by would be appreciated.

Thanks,
Jake

Re: [PATCH] drm/i915/psr: ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR not valid for eDP

[Hogander, Jouni]

On Thu, 2026-10-08 at 23:47 -0400, Jake Steinman wrote:
> Hi Jouni,
> 
> Tested on the XPS 16 DA16260 (PTL, xe, 7.3-rc5, DA16260 PR quirk
> removed, no other changes): Panel Replay SU is smooth with this
> patch.
> 
> Tested-by: Jake Steinman <j@metarealtyinc.ca>
> 
> Two things it leaves:
> 
> - The panel still judders for a few seconds after panel power-on
>   (DPMS on). Holding PR inactive after power-on fixes that here; 8 s
>   is clean, 3 s is not quite enough.
> 
> - No DC5 on a static screen while PR is active: 0 entries against 550
>   on a static VT with the AS SDP suspended.
> 
> Since this panel needs a specific change for the first one anyway,
> could the AS SDP also be suspended while vblank is disabled on panels
> that handle it, as in the RFC? That keeps DC5/DC6 on a static screen.
> https://lore.kernel.org/r/20261006220500.3417572-1-j@metarealtyinc.ca

I don't really see why we should bind it to vblank. I think vblank is
also disabled most of the times anyways where we could benefit from
having AS SDP disabled.
> 
> If you respin, a Reported-by would be appreciated.

Of course. I already added it, but my checkpatch complained about
missing Closes tag. I wasn't sure if this patch is closing any gitlab
ticket. I was thinking adding them both when tested.

I still need to modify also the commit message and consider even using
the change. eDP spec is saying that AS SDP can be disabled:

"The Source device may disable the Adaptive-Sync SDP transmission by
setting its Adaptive Sync SDP Transmission Disable in PR Active State
bit (DB0[2] = 1) in the Adaptive-Sync SDP. DPCD 00107h[6] shall remain
set (DPCD 00107h[6] = 1)."

Even if "crtc_state->disable_as_sdp_when_pr_active == 1" it should be
ok to disable AS SDP sending (referring you RFC patch). I'll guess
having inverse logic in ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR means
eDP sink should always support it.


BR,
Jouni Högander

> 
> Thanks,
> Jake