Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: sashiko-bot@kernel.org
To: "Animesh Manna" <animesh.manna@intel.com>,
	intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
	dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v7 10/20] drm/i915/alpm: Half LFPS cycle calculation
Date: Mon, 26 Oct 2026 07:06:00 +0000	[thread overview]
Message-ID: <sashiko-outbox-184650@kernel.org> (raw)
In-Reply-To: <20261026054001.799894-11-animesh.manna@intel.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/i915/alpm: uninitialized variables in get_lfps_cycle_time()
--

commit 5c47cf246b743bb16ee9903923cc22a473083617
Author: Animesh Manna <animesh.manna@intel.com>

drm/i915/alpm: Half LFPS cycle calculation

This patch updates the LFPS cycle period minimum and maximum calculation for
DP2.1 ALPM by splitting it into HAS_LT_PHY() and non-LT-PHY helpers that check
whether the output type is eDP.

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 2bf2ca9564391..b6de938990ddb 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -81,24 +81,49 @@ static int get_silence_period_symbols(const struct intel_crtc_state *crtc_state)
>  		1000 / 1000;
>  }
>  
> -static void get_lfps_cycle_min_max_time(const struct intel_crtc_state *crtc_state,
> -					int *min, int *max)
> +static void lnl_get_lfps_period_min_max_time(const struct intel_crtc_state *crtc_state,
> +					     int *min, int *max)
>  {
> -	if (crtc_state->port_clock < 540000) {
> -		*min = 65 * LFPS_CYCLE_COUNT;
> -		*max = 75 * LFPS_CYCLE_COUNT;
> -	} else {
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
> +		if (crtc_state->port_clock < 540000) {
> +			*min = 65 * LFPS_CYCLE_COUNT;
> +			*max = 75 * LFPS_CYCLE_COUNT;
> +		} else {
> +			*min = 140;
> +			*max = 800;
> +		}
> +	}
> +}
> +
> +static void lt_get_lfps_period_min_max_time(const struct intel_crtc_state *crtc_state,
> +					    int *min, int *max)
> +{
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
>  		*min = 140;
>  		*max = 800;
> +	} else {
> +		*min = 320;
> +		*max = 1600;
>  	}
>  }
>  
> +static void get_lfps_period_min_max_time(const struct intel_crtc_state *crtc_state,
> +					int *min, int *max)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	if (HAS_LT_PHY(display))
> +		lt_get_lfps_period_min_max_time(crtc_state, min, max);
> +	else
> +		lnl_get_lfps_period_min_max_time(crtc_state, min, max);
> +}
> +
>  static int get_lfps_cycle_time(const struct intel_crtc_state *crtc_state)
>  {
>  	int tlfps_cycle_min, tlfps_cycle_max;
>  
> -	get_lfps_cycle_min_max_time(crtc_state, &tlfps_cycle_min,
> -				    &tlfps_cycle_max);
> +	get_lfps_period_min_max_time(crtc_state, &tlfps_cycle_min,
> +				     &tlfps_cycle_max);
>  
>  	return tlfps_cycle_min +  (tlfps_cycle_max - tlfps_cycle_min) / 2;
>  }

[Severity: High]
Can tlfps_cycle_min and tlfps_cycle_max be used uninitialized in
get_lfps_cycle_time()?

In get_lfps_cycle_time(), tlfps_cycle_min and tlfps_cycle_max are declared
without initialization and passed to get_lfps_period_min_max_time(). When
HAS_LT_PHY(display) is false, get_lfps_period_min_max_time() calls
lnl_get_lfps_period_min_max_time(), which only assigns *min and *max when
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) is true.

For non-eDP outputs on !HAS_LT_PHY(display) platforms, *min and *max are
never written before get_lfps_cycle_time() computes:

	return tlfps_cycle_min +  (tlfps_cycle_max - tlfps_cycle_min) / 2;

In particular, get_establishment_period() calls get_lfps_cycle_time() when
lttpr_count > 0, which only occurs in the !intel_crtc_has_type(crtc_state,
INTEL_OUTPUT_EDP) branch:

drivers/gpu/drm/i915/display/intel_alpm.c:get_establishment_period() {
	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
		num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
	} else {
		num_ml_phy_lock = 7;

		lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
		...
	}
	...
	if (lttpr_count > 0) {
		/* tlw and tcs values are taken from DP2.1 spec */
		int tlw = 13000;
		int tcs = 10000;
		int tlfps_period = get_lfps_cycle_time(crtc_state);
		...
	}
}

Would this leave tlfps_cycle_min and tlfps_cycle_max uninitialized at
runtime for non-eDP DP outputs and trigger -Wmaybe-uninitialized or
-Wsometimes-uninitialized warnings during the build?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261026054001.799894-1-animesh.manna@intel.com?part=10

  reply	other threads:[~2026-10-26  7:06 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-26  5:39 [PATCH v7 00/20] Enable DP2.1 alpm Animesh Manna
2026-10-26  5:39 ` [PATCH v7 01/20] drm/i915/alpm: Program zero-based LFPS half cycle duration Animesh Manna
2026-10-27 15:33   ` Jani Nikula
2026-10-28  5:42     ` Manna, Animesh
2026-10-26  5:39 ` [PATCH v7 02/20] drm/dp: Add DPCD definitions for DP2.1 ALPM capability Animesh Manna
2026-10-26  5:39 ` [PATCH v7 03/20] drm/i915/alpm: Move alpm sink capability readout into a separate function Animesh Manna
2026-10-26  5:39 ` [PATCH v7 04/20] drm/i915/alpm: alpm_init() for DP2.1 Animesh Manna
2026-10-26  7:11   ` sashiko-bot
2026-10-26  5:39 ` [PATCH v7 05/20] drm/i915/alpm: Enable debugfs " Animesh Manna
2026-10-26  5:39 ` [PATCH v7 06/20] drm/i915/alpm: Refactor Auxless wake time calculation Animesh Manna
2026-10-26  5:39 ` [PATCH v7 07/20] drm/i915/alpm: Auxless wake time calculation for Xe3p Animesh Manna
2026-10-26  5:39 ` [PATCH v7 08/20] drm/i915/alpm: Modify AUX_LESS_WAKE_TIME bitfield for xe3lpd Animesh Manna
2026-10-26  5:39 ` [PATCH v7 09/20] drm/i915/alpm: table based establishment period Animesh Manna
2026-10-26  5:39 ` [PATCH v7 10/20] drm/i915/alpm: Half LFPS cycle calculation Animesh Manna
2026-10-26  7:06   ` sashiko-bot [this message]
2026-10-26  5:39 ` [PATCH v7 11/20] drm/i915/alpm: Modify LFPS cycle count for DP ALPM Animesh Manna
2026-10-26  5:39 ` [PATCH v7 12/20] drm/i915/alpm: Modify LFPS_CYCLE_COUNT bitfield for xe3lpd Animesh Manna
2026-10-26  5:39 ` [PATCH v7 13/20] drm/i915/alpm: Program LTTPR count for DP 2.1 ALPM Animesh Manna
2026-10-26  5:39 ` [PATCH v7 14/20] drm/i915/alpm: Enable MAC Transmitting LFPS for LT PHY Animesh Manna
2026-10-26  5:39 ` [PATCH v7 15/20] drm/i915/alpm: Compute and program switch to active latency Animesh Manna
2026-10-26  5:39 ` [PATCH v7 16/20] drm/i915/alpm: Replace is_edp() with alpm_is_possible() Animesh Manna
2026-10-26  7:16   ` sashiko-bot
2026-10-26  5:39 ` [PATCH v7 17/20] drm/i915/alpm: Disallow ALPM for UHBR link rate Animesh Manna
2026-10-26  5:39 ` [PATCH v7 18/20] drm/i915/alpm: Compute ALPM config before PSR config Animesh Manna
2026-10-26  5:39 ` [PATCH v7 19/20] drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf Animesh Manna
2026-10-26  7:23   ` sashiko-bot
2026-10-26  5:39 ` [PATCH v7 20/20] drm/i915/dp: Enable AS SDP for DP Panel Replay with AUX-less ALPM Animesh Manna
2026-10-26  6:43 ` ✗ i915.CI.BAT: failure for Enable DP2.1 alpm (rev7) Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=sashiko-outbox-184650@kernel.org \
    --to=sashiko-bot@kernel.org \
    --cc=animesh.manna@intel.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=sashiko-reviews@lists.linux.dev \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox