[PATCH v7 00/20] Enable DP2.1 alpm

[PATCH v7 00/20] Enable DP2.1 alpm

[Animesh Manna]

ALPM support added on DP2.1 and xe3p will support DP2.1 alpm.
This patch series extending alpm supoort for DP2.1.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>

Animesh Manna (20):
  drm/i915/alpm: Program zero-based LFPS half cycle duration
  drm/dp: Add DPCD definitions for DP2.1 ALPM capability
  drm/i915/alpm: Move alpm sink capability readout into a separate
    function
  drm/i915/alpm: alpm_init() for DP2.1
  drm/i915/alpm: Enable debugfs for DP2.1
  drm/i915/alpm: Refactor Auxless wake time calculation
  drm/i915/alpm: Auxless wake time calculation for Xe3p
  drm/i915/alpm: Modify AUX_LESS_WAKE_TIME bitfield for xe3lpd
  drm/i915/alpm: table based establishment period
  drm/i915/alpm: Half LFPS cycle calculation
  drm/i915/alpm: Modify LFPS cycle count for DP ALPM
  drm/i915/alpm: Modify LFPS_CYCLE_COUNT bitfield for xe3lpd
  drm/i915/alpm: Program LTTPR count for DP 2.1 ALPM
  drm/i915/alpm: Enable MAC Transmitting LFPS for LT PHY
  drm/i915/alpm: Compute and program switch to active latency
  drm/i915/alpm: Replace is_edp() with alpm_is_possible()
  drm/i915/alpm: Disallow ALPM for UHBR link rate
  drm/i915/alpm: Compute ALPM config before PSR config
  drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf
  drm/i915/dp: Enable AS SDP for DP Panel Replay with AUX-less ALPM

 drivers/gpu/drm/i915/display/intel_alpm.c     | 443 +++++++++++++++---
 drivers/gpu/drm/i915/display/intel_alpm.h     |  17 +-
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |   2 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |   5 +-
 .../drm/i915/display/intel_display_types.h    |   6 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  22 +-
 .../drm/i915/display/intel_dp_link_training.c |  22 +-
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |  27 ++
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |   2 +
 .../gpu/drm/i915/display/intel_lt_phy_regs.h  |   3 +
 drivers/gpu/drm/i915/display/intel_psr.c      |  23 +-
 drivers/gpu/drm/i915/display/intel_psr.h      |   5 +-
 drivers/gpu/drm/i915/display/intel_psr_regs.h |  16 +-
 include/drm/display/drm_dp.h                  |   5 +-
 14 files changed, 490 insertions(+), 108 deletions(-)

-- 
2.43.0

[PATCH v7 01/20] drm/i915/alpm: Program zero-based LFPS half cycle duration

[Animesh Manna]

The LFPS Half Cycle Duration field, as well as the First and Last LFPS
Half Cycle Duration fields, in PORT_ALPM_LFPS_CTL are zero-based: per
Bspec the value programmed must be N_Symbol - 1. The number of symbols
was programmed directly, making each half cycle one symbol clock too
long.

Subtract one in the PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION,
PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION and
PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION field macros so the
programmed value matches the zero-based field encoding.

Since the fields now encode 1 to 32 symbols, update the bounds check
in _lnl_compute_aux_less_alpm_params() to accept a half cycle of 32
symbols and reject 0, which cannot be encoded.

v2: Adjust half cycle bounds check for zero-based encoding. [sashiko]

Bspec: 71632
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     |  3 ++-
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 12 +++++++++---
 2 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index f54b29e193ee..8542bd9c9666 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -134,7 +134,8 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
 
 	if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK ||
 	    silence_period > PORT_ALPM_CTL_SILENCE_PERIOD_MASK ||
-	    lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK)
+	    lfps_half_cycle < 1 ||
+	    lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK + 1)
 		return false;
 
 	if (display->params.psr_safest_params)
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index a57bc111290d..78a05387eab5 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -335,11 +335,17 @@
 #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK		REG_GENMASK(27, 24)
 #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN		7
 #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(val)		REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK, (val) - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN)
+/*
+ * The LFPS half cycle duration fields (including the first and last half
+ * cycle) are zero-based, i.e. the value programmed is N_Symbol - 1.
+ *
+ * Bspec: 71632
+ */
 #define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(20, 16)
-#define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val)
+#define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, (val) - 1)
 #define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(12, 8)
-#define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK, val)
+#define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK, (val) - 1)
 #define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(4, 0)
-#define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK, val)
+#define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK, (val) - 1)
 
 #endif /* __INTEL_PSR_REGS_H__ */
-- 
2.43.0

Re: [PATCH v7 01/20] drm/i915/alpm: Program zero-based LFPS half cycle duration

[Jani Nikula]

On Mon, 26 Oct 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> The LFPS Half Cycle Duration field, as well as the First and Last LFPS
> Half Cycle Duration fields, in PORT_ALPM_LFPS_CTL are zero-based: per
> Bspec the value programmed must be N_Symbol - 1. The number of symbols
> was programmed directly, making each half cycle one symbol clock too
> long.
>
> Subtract one in the PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION,
> PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION and
> PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION field macros so the
> programmed value matches the zero-based field encoding.
>
> Since the fields now encode 1 to 32 symbols, update the bounds check
> in _lnl_compute_aux_less_alpm_params() to accept a half cycle of 32
> symbols and reject 0, which cannot be encoded.
>
> v2: Adjust half cycle bounds check for zero-based encoding. [sashiko]
>
> Bspec: 71632
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c     |  3 ++-
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 12 +++++++++---
>  2 files changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index f54b29e193ee..8542bd9c9666 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -134,7 +134,8 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
>  
>  	if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK ||
>  	    silence_period > PORT_ALPM_CTL_SILENCE_PERIOD_MASK ||
> -	    lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK)
> +	    lfps_half_cycle < 1 ||
> +	    lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK + 1)
>  		return false;
>  
>  	if (display->params.psr_safest_params)
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index a57bc111290d..78a05387eab5 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -335,11 +335,17 @@
>  #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK		REG_GENMASK(27, 24)
>  #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN		7
>  #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(val)		REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK, (val) - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN)
> +/*
> + * The LFPS half cycle duration fields (including the first and last half
> + * cycle) are zero-based, i.e. the value programmed is N_Symbol - 1.
> + *
> + * Bspec: 71632
> + */

Please let's not normalize adding bspec references to code comments.

>  #define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(20, 16)
> -#define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val)
> +#define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, (val) - 1)
>  #define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(12, 8)
> -#define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK, val)
> +#define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK, (val) - 1)
>  #define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(4, 0)
> -#define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK, val)
> +#define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK, (val) - 1)
>  
>  #endif /* __INTEL_PSR_REGS_H__ */

-- 
Jani Nikula, Intel

RE: [PATCH v7 01/20] drm/i915/alpm: Program zero-based LFPS half cycle duration

[Manna, Animesh]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, October 27, 2026 9:04 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org; dri-
> devel@lists.freedesktop.org
> Cc: Hogander, Jouni <jouni.hogander@intel.com>; Kandpal, Suraj
> <suraj.kandpal@intel.com>; Manna, Animesh <animesh.manna@intel.com>
> Subject: Re: [PATCH v7 01/20] drm/i915/alpm: Program zero-based LFPS half
> cycle duration
> 
> On Mon, 26 Oct 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> > The LFPS Half Cycle Duration field, as well as the First and Last LFPS
> > Half Cycle Duration fields, in PORT_ALPM_LFPS_CTL are zero-based: per
> > Bspec the value programmed must be N_Symbol - 1. The number of
> symbols
> > was programmed directly, making each half cycle one symbol clock too
> > long.
> >
> > Subtract one in the PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION,
> > PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION and
> > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION field macros so
> the
> > programmed value matches the zero-based field encoding.
> >
> > Since the fields now encode 1 to 32 symbols, update the bounds check
> > in _lnl_compute_aux_less_alpm_params() to accept a half cycle of 32
> > symbols and reject 0, which cannot be encoded.
> >
> > v2: Adjust half cycle bounds check for zero-based encoding. [sashiko]
> >
> > Bspec: 71632
> > Cc: Jouni Högander <jouni.hogander@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_alpm.c     |  3 ++-
> >  drivers/gpu/drm/i915/display/intel_psr_regs.h | 12 +++++++++---
> >  2 files changed, 11 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index f54b29e193ee..8542bd9c9666 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -134,7 +134,8 @@ _lnl_compute_aux_less_alpm_params(struct
> intel_dp
> > *intel_dp,
> >
> >  	if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK
> ||
> >  	    silence_period > PORT_ALPM_CTL_SILENCE_PERIOD_MASK ||
> > -	    lfps_half_cycle >
> PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK)
> > +	    lfps_half_cycle < 1 ||
> > +	    lfps_half_cycle >
> > +PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK + 1)
> >  		return false;
> >
> >  	if (display->params.psr_safest_params)
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > index a57bc111290d..78a05387eab5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > @@ -335,11 +335,17 @@
> >  #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK
> 	REG_GENMASK(27, 24)
> >  #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN		7
> >  #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(val)
> 	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK,
> (val) - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN)
> > +/*
> > + * The LFPS half cycle duration fields (including the first and last
> > +half
> > + * cycle) are zero-based, i.e. the value programmed is N_Symbol - 1.
> > + *
> > + * Bspec: 71632
> > + */
> 
> Please let's not normalize adding bspec references to code comments.

Sure, will drop in next version.

Regards,
Animesh

> 
> >  #define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK
> 	REG_GENMASK(20, 16)
> > -#define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val)
> 	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATIO
> N_MASK, val)
> > +#define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val)
> 	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATIO
> N_MASK, (val) - 1)
> >  #define
> PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK
> 	REG_GENMASK(12, 8)
> > -#define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val)
> 	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_D
> URATION_MASK, val)
> > +#define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val)
> 	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_D
> URATION_MASK, (val) - 1)
> >  #define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK
> 	REG_GENMASK(4, 0)
> > -#define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val)
> 	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DU
> RATION_MASK, val)
> > +#define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val)
> 	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DU
> RATION_MASK, (val) - 1)
> >
> >  #endif /* __INTEL_PSR_REGS_H__ */
> 
> --
> Jani Nikula, Intel

[PATCH v7 02/20] drm/dp: Add DPCD definitions for DP2.1 ALPM capability

[Animesh Manna]

Add the LTTPR ALPM capabilities register (0xf0009) with the AUX-less
ALPM supported bit, and the total LTTPR count register (0xf000a), both
added in DP2.1. They are needed to enable DP2.1 ALPM with LTTPRs.

Extend DP_LTTPR_COMMON_CAP_SIZE from 8 to 10 so that the LTTPR ALPM
capability is read as part of the LTTPR common capabilities. This makes
drm_dp_read_lttpr_common_caps() read two more bytes for all its users,
DP_PHY_REPEATER_EQ_DONE (0xf0008) and DP_LTTPR_ALPM_CAPABILITIES
(0xf0009). The existing helpers don't use these bytes.

v2: Add DP_LTTPR_AUX_LESS_ALPM_SUPPORTED bit definition.
v3: Use drm/dp prefix and describe the DP_LTTPR_COMMON_CAP_SIZE change.

Cc: Jouni Högander <jouni.hogander@intel.com>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 include/drm/display/drm_dp.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index e63c7f075f54..ea8cd497b658 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1541,6 +1541,9 @@
 /* See DP_128B132B_SUPPORTED_LINK_RATES for values */
 #define DP_PHY_REPEATER_128B132B_RATES			    0xf0007 /* 2.0 */
 #define DP_PHY_REPEATER_EQ_DONE                             0xf0008 /* 2.0 E11 */
+#define DP_LTTPR_ALPM_CAPABILITIES                          0xf0009 /* 2.1 */
+# define DP_LTTPR_AUX_LESS_ALPM_SUPPORTED                   (1 << 0)
+#define DP_TOTAL_LTTPR_CNT                                  0xf000a /* 2.1 */
 
 enum drm_dp_phy {
 	DP_PHY_DPRX,
@@ -1720,7 +1723,7 @@ enum drm_dp_phy {
 #define DP_DSC_BRANCH_CAP_SIZE		3
 #define EDP_PSR_RECEIVER_CAP_SIZE	2
 #define EDP_DISPLAY_CTL_CAP_SIZE	5
-#define DP_LTTPR_COMMON_CAP_SIZE	8
+#define DP_LTTPR_COMMON_CAP_SIZE	10
 #define DP_LTTPR_PHY_CAP_SIZE		3
 
 #define DP_SDP_AUDIO_TIMESTAMP		0x01
-- 
2.43.0

[PATCH v7 03/20] drm/i915/alpm: Move alpm sink capability readout into a separate function

[Animesh Manna]

Abstract ALPM DPCD initialization into its own function.

v2:
- Improve commit description. [Suraj, Jouni]
- Handle error value of intel_alpm_init_dpcd() with an early exit
  in intel_edp_init_dpcd(). [Jouni]
v3:
- Return int and propagate the original error instead of
  flattening it to bool. [Jani]

Cc: Jouni Högander <jouni.hogander@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 14 ++++++++++++++
 drivers/gpu/drm/i915/display/intel_alpm.h |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c   |  5 +----
 3 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 8542bd9c9666..cb1d68fef198 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -43,6 +43,20 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
 		(crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));
 }
 
+int intel_alpm_init_dpcd(struct intel_dp *intel_dp)
+{
+	u8 dpcd;
+	int ret;
+
+	ret = drm_dp_dpcd_read_byte(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &dpcd);
+	if (ret < 0)
+		return ret;
+
+	intel_dp->alpm_dpcd = dpcd;
+
+	return 0;
+}
+
 void intel_alpm_init(struct intel_dp *intel_dp)
 {
 	mutex_init(&intel_dp->alpm.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index f8f605d94f96..1cb226bc342a 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -15,6 +15,7 @@ struct intel_connector;
 struct intel_atomic_state;
 struct intel_crtc;
 
+int intel_alpm_init_dpcd(struct intel_dp *intel_dp);
 void intel_alpm_init(struct intel_dp *intel_dp);
 bool intel_alpm_compute_params(struct intel_dp *intel_dp,
 			       struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index bf5e87a72108..816337efeb91 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5057,10 +5057,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
 	 */
 	intel_dp_init_source_oui(intel_dp);
 
-	/* Read the ALPM DPCD caps */
-	ret = drm_dp_dpcd_read_byte(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
-				    &intel_dp->alpm_dpcd);
-	if (ret < 0)
+	if (intel_alpm_init_dpcd(intel_dp))
 		return false;
 
 	/*
-- 
2.43.0

[PATCH v7 04/20] drm/i915/alpm: alpm_init() for DP2.1

[Animesh Manna]

Initialize ALPM for DP2.1 and separate out ALPM mutex-init
from alpm-init.

v2: Separate out mutex-init. [Jani]
v3: Refactor further to avoid DISPLAY_VER check in multiple places. [Jani]
v4: Cosmetic changes. [Suraj]
v5: Reset alpm_dpcd and simplify source-supported check.
v6: Drop display-version check for eDP for backward compatible.
v7:
- Read ALPM DPCD in detect only for DP, eDP already does it. [Jouni]
- Move source-supported check into intel_alpm_init/_dpcd(). [Jouni]
- Check source support instead of sink caps in intel_alpm_disable()
  as alpm_dpcd is reset on disconnect before the CRTC is disabled.
  [Sashiko]

Cc: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 19 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.c   |  9 ++++++---
 2 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index cb1d68fef198..b6307862b756 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -43,11 +43,21 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
 		(crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));
 }
 
+static bool intel_alpm_source_supported(struct intel_dp *intel_dp)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	return intel_dp_is_edp(intel_dp) || DISPLAY_VER(display) >= 35;
+}
+
 int intel_alpm_init_dpcd(struct intel_dp *intel_dp)
 {
 	u8 dpcd;
 	int ret;
 
+	if (!intel_alpm_source_supported(intel_dp))
+		return 0;
+
 	ret = drm_dp_dpcd_read_byte(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &dpcd);
 	if (ret < 0)
 		return ret;
@@ -59,6 +69,9 @@ int intel_alpm_init_dpcd(struct intel_dp *intel_dp)
 
 void intel_alpm_init(struct intel_dp *intel_dp)
 {
+	if (!intel_alpm_source_supported(intel_dp))
+		return;
+
 	mutex_init(&intel_dp->alpm.lock);
 }
 
@@ -750,7 +763,11 @@ void intel_alpm_disable(struct intel_dp *intel_dp)
 	struct intel_display *display = to_intel_display(intel_dp);
 	enum transcoder cpu_transcoder = intel_dp->alpm.transcoder;
 
-	if (DISPLAY_VER(display) < 20 || !intel_dp->alpm_dpcd)
+	/*
+	 * Don't check sink ALPM caps here, they are reset on disconnect
+	 * before the CRTC is disabled.
+	 */
+	if (DISPLAY_VER(display) < 20 || !intel_alpm_source_supported(intel_dp))
 		return;
 
 	mutex_lock(&intel_dp->alpm.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 816337efeb91..c543fe551eb8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6607,6 +6607,7 @@ intel_dp_detect(struct drm_connector *_connector,
 		connector->dp.panel_replay_caps.su_support = false;
 		connector->dp.panel_replay_caps.dsc_support =
 			INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
+		intel_dp->alpm_dpcd = 0;
 
 		intel_dp_mst_disconnect(intel_dp);
 
@@ -6629,8 +6630,10 @@ intel_dp_detect(struct drm_connector *_connector,
 	if (ret == 1)
 		connector->base.epoch_counter++;
 
-	if (!intel_dp_is_edp(intel_dp))
+	if (!intel_dp_is_edp(intel_dp)) {
+		intel_alpm_init_dpcd(intel_dp);
 		intel_psr_init_dpcd(intel_dp, connector);
+	}
 
 	intel_dp_detect_dsc_caps(intel_dp, connector);
 
@@ -7272,8 +7275,6 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 	 */
 	intel_hpd_enable_detection(encoder);
 
-	intel_alpm_init(intel_dp);
-
 	/* Cache DPCD and EDID for edp. */
 	has_dpcd = intel_edp_init_dpcd(intel_dp, connector);
 
@@ -7488,6 +7489,8 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
 
 	intel_psr_init(intel_dp);
 
+	intel_alpm_init(intel_dp);
+
 	return true;
 
 fail:
-- 
2.43.0

Re: [PATCH v7 04/20] drm/i915/alpm: alpm_init() for DP2.1

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/i915/alpm: wrong transcoder ALPM_CTL access in intel_alpm_disable()
--

commit 16555494a05a6a62d73ca6ad3e0999793ea5b8b4
Author: Animesh Manna <animesh.manna@intel.com>

drm/i915/alpm: alpm_init() for DP2.1

This commit initializes ALPM for DP 2.1 on display version 35 and newer,
separating the ALPM mutex initialization from DPCD capability initialization
and checking source support instead of sink capabilities in
intel_alpm_disable().

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index cb1d68fef1986..b6307862b7560 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
[ ... ]
> @@ -750,7 +763,11 @@ void intel_alpm_disable(struct intel_dp *intel_dp)
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	enum transcoder cpu_transcoder = intel_dp->alpm.transcoder;
>  
> -	if (DISPLAY_VER(display) < 20 || !intel_dp->alpm_dpcd)
> +	/*
> +	 * Don't check sink ALPM caps here, they are reset on disconnect
> +	 * before the CRTC is disabled.
> +	 */
> +	if (DISPLAY_VER(display) < 20 || !intel_alpm_source_supported(intel_dp))
>  		return;

[Severity: High]
Can replacing the intel_dp->alpm_dpcd check with
intel_alpm_source_supported(intel_dp) here cause intel_alpm_disable() to
modify ALPM_CTL on the wrong transcoder when ALPM was never configured on
intel_dp?

Because struct intel_digital_port is zero-allocated,
intel_dp->alpm.transcoder starts at 0 (TRANSCODER_A, rather than
INVALID_TRANSCODER), and intel_alpm_init() does not initialize it. Across
the driver, intel_dp->alpm.transcoder is only set in
intel_alpm_configure():

drivers/gpu/drm/i915/display/intel_alpm.c:intel_alpm_configure() {
	lnl_alpm_configure(intel_dp, crtc_state);
	intel_dp->alpm.transcoder = crtc_state->cpu_transcoder;
}

which is only called from intel_psr_enable_source() when
crtc_state->has_psr is true or from intel_alpm_lobf_enable() when
new_crtc_state->has_lobf is true.

However, intel_ddi_disable_dp() unconditionally calls
intel_alpm_disable(intel_dp) whenever any DP or eDP encoder is disabled:

drivers/gpu/drm/i915/display/intel_ddi.c:intel_ddi_disable_dp() {
	...
	intel_panel_unprepare(old_conn_state);
	intel_psr_disable(intel_dp, old_crtc_state);
	intel_alpm_disable(intel_dp);
	...
}

And intel_dp_short_pulse() also calls intel_alpm_disable(intel_dp) if
reading DP_RECEIVER_ALPM_STATUS fails or reports an error:

drivers/gpu/drm/i915/display/intel_dp.c:intel_dp_short_pulse() {
	...
	if (intel_alpm_get_error(intel_dp)) {
		intel_alpm_disable(intel_dp);
		intel_dp->alpm.sink_alpm_error = true;
	}
	...
}

Previously, !intel_dp->alpm_dpcd caused intel_alpm_disable() to return
early for external DP connectors and eDP panels without ALPM support. With
this change, if an external DP connector on DISPLAY_VER(display) >= 35 (or
an eDP connector on DISPLAY_VER(display) >= 20) is enabled on
TRANSCODER_B/C/D without PSR, Panel Replay, or LOBF, intel_alpm_configure()
is never called and intel_dp->alpm.transcoder remains TRANSCODER_A (or a
stale transcoder from a previous modeset).

When that connector is later disabled or hits the short HPD pulse error
path, intel_alpm_disable() will lock that connector's intel_dp->alpm.lock
and clear ALPM_CTL_ALPM_ENABLE | ALPM_CTL_LOBF_ENABLE in
ALPM_CTL(display, TRANSCODER_A). If TRANSCODER_A is active on another
connector (such as eDP on Pipe A), this races with Pipe A and disables its
active ALPM/LOBF state; if TRANSCODER_A's power well is off, it triggers an
unclaimed MMIO register access.

Should intel_dp->alpm.transcoder be initialized to INVALID_TRANSCODER in
intel_alpm_init(), reset to INVALID_TRANSCODER in intel_alpm_disable(), and
checked for INVALID_TRANSCODER before accessing ALPM_CTL()?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261026054001.799894-1-animesh.manna@intel.com?part=4

[PATCH v7 05/20] drm/i915/alpm: Enable debugfs for DP2.1

[Animesh Manna]

Enable ALPM debug info through lobf debug info.

As LOBF debugfs entries are now created for both DP and eDP connectors,
rename i915_edp_lobf_debug/i915_edp_lobf_info to i915_lobf_debug/
i915_lobf_info. The connector type is already part of the debugfs path.

v2: cosmetic change. [Suraj]
v3: Use common api instead of DISPLAY_VER check in multiple places. [Jani]
v4: Add display-version check as it dropped for EDP.
v5:
- Rename debugfs entries to i915_lobf_debug/i915_lobf_info. [Jouni]
- Rebase on intel_alpm_source_supported() taking intel_dp and skip
  MST connectors as they have no fixed encoder.

Cc: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 31 ++++++++++++++---------
 1 file changed, 19 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index b6307862b756..12dc79198494 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -680,7 +680,7 @@ void intel_alpm_lobf_enable(const struct intel_crtc_state *new_crtc_state)
 	}
 }
 
-static int i915_edp_lobf_info_show(struct seq_file *m, void *data)
+static int i915_lobf_info_show(struct seq_file *m, void *data)
 {
 	struct intel_connector *connector = m->private;
 	struct intel_display *display = to_intel_display(connector);
@@ -714,10 +714,10 @@ static int i915_edp_lobf_info_show(struct seq_file *m, void *data)
 	return ret;
 }
 
-DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_info);
+DEFINE_SHOW_ATTRIBUTE(i915_lobf_info);
 
 static int
-i915_edp_lobf_debug_get(void *data, u64 *val)
+i915_lobf_debug_get(void *data, u64 *val)
 {
 	struct intel_connector *connector = data;
 	struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
@@ -728,7 +728,7 @@ i915_edp_lobf_debug_get(void *data, u64 *val)
 }
 
 static int
-i915_edp_lobf_debug_set(void *data, u64 val)
+i915_lobf_debug_set(void *data, u64 val)
 {
 	struct intel_connector *connector = data;
 	struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
@@ -738,8 +738,8 @@ i915_edp_lobf_debug_set(void *data, u64 val)
 	return 0;
 }
 
-DEFINE_SIMPLE_ATTRIBUTE(i915_edp_lobf_debug_fops,
-			i915_edp_lobf_debug_get, i915_edp_lobf_debug_set,
+DEFINE_SIMPLE_ATTRIBUTE(i915_lobf_debug_fops,
+			i915_lobf_debug_get, i915_lobf_debug_set,
 			"%llu\n");
 
 void intel_alpm_lobf_debugfs_add(struct intel_connector *connector)
@@ -747,15 +747,22 @@ void intel_alpm_lobf_debugfs_add(struct intel_connector *connector)
 	struct intel_display *display = to_intel_display(connector);
 	struct dentry *root = connector->base.debugfs_entry;
 
-	if (DISPLAY_VER(display) < 20 ||
-	    connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
+	if (DISPLAY_VER(display) < 20)
+		return;
+
+	if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP &&
+	    connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort)
+		return;
+
+	if (connector->mst.dp ||
+	    !intel_alpm_source_supported(intel_attached_dp(connector)))
 		return;
 
-	debugfs_create_file("i915_edp_lobf_debug", 0644, root,
-			    connector, &i915_edp_lobf_debug_fops);
+	debugfs_create_file("i915_lobf_debug", 0644, root,
+			    connector, &i915_lobf_debug_fops);
 
-	debugfs_create_file("i915_edp_lobf_info", 0444, root,
-			    connector, &i915_edp_lobf_info_fops);
+	debugfs_create_file("i915_lobf_info", 0444, root,
+			    connector, &i915_lobf_info_fops);
 }
 
 void intel_alpm_disable(struct intel_dp *intel_dp)
-- 
2.43.0

[PATCH v7 06/20] drm/i915/alpm: Refactor Auxless wake time calculation

[Animesh Manna]

Divide the auxless wake time calculation in parts which will
help later to add Xe3p related modification.

v2: Refactor first existing calculation. [Jani]
v3: Cosmetic changes. [Jani, Suraj]
v4: Keep num_ml_phy_lock for readability and return the
    establishment period directly. [Jouni]

Bspec: 71477
Cc: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 31 ++++++++++++++++-------
 1 file changed, 22 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 12dc79198494..ab6612b4506e 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -109,6 +109,25 @@ static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
 		1000 / (2 * LFPS_CYCLE_COUNT);
 }
 
+static int get_tphy2_p2_to_p0(const struct intel_crtc_state *crtc_state)
+{
+	return 12 * 1000;
+}
+
+static int get_establishment_period(const struct intel_crtc_state *crtc_state)
+{
+	int t1 = 50 * 1000;
+	int tps4 = 252;
+	/* port_clock is link rate in 10kbit/s units */
+	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;
+	int num_ml_phy_lock, tcds;
+
+	num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
+	tcds = num_ml_phy_lock * tml_phy_lock;
+
+	return SILENCE_PERIOD_TIME + t1 + tcds;
+}
+
 /*
  * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+
  * tSilence, Max+ tPHY Establishment + tCDS) / tline)
@@ -130,17 +149,11 @@ static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
  */
 static int _lnl_compute_aux_less_wake_time(const struct intel_crtc_state *crtc_state)
 {
-	int tphy2_p2_to_p0 = 12 * 1000;
-	int t1 = 50 * 1000;
-	int tps4 = 252;
-	/* port_clock is link rate in 10kbit/s units */
-	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;
-	int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
-	int t2 = num_ml_phy_lock * tml_phy_lock;
-	int tcds = 1 * t2;
+	int tphy2_p2_to_p0 = get_tphy2_p2_to_p0(crtc_state);
+	int establishment_period = get_establishment_period(crtc_state);
 
 	return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(crtc_state) +
-			    SILENCE_PERIOD_TIME + t1 + tcds, 1000);
+			    establishment_period, 1000);
 }
 
 static int
-- 
2.43.0

[PATCH v7 07/20] drm/i915/alpm: Auxless wake time calculation for Xe3p

[Animesh Manna]

Add support for auxless waketime calculation for DP2.1 ALPM
as dependent parameter got changed.

v1: Initial version.
v2: Use intel_dp_is_uhbr(). [Jani]
v3:
- Separate out switch to active latency calculation.
- Use macro definition for ML_PHY_LOCK length. [Suraj]
v4:
- Fix 32-bit signed integer overflow. [sashiko]
- Fix negative return of drm_dp_lttpr_count(). [sashiko]
- Introduce get_ml_phy_lock_len() and get_dp_link_symbol_size(). [Jouni]
- Align variable naming with bpec formula of establishment_period. [Jouni]
v5:
- Use HAS_LT_PHY() for PHY P2 to P0 latency. [Jouni]
- Use existing intel_dp_link_symbol_size() instead of a duplicate. [Jouni]
- Fix tML_PHY_LOCK comments to use Rate Div. [Jouni]
- Check drm_dp_lttpr_count() return value. [Jouni]
- Keep num_ml_phy_lock and return establishment period directly. [Jouni]

Bspec: 71477
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 70 +++++++++++++++++++----
 1 file changed, 59 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index ab6612b4506e..b9e31c29ab96 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -109,22 +109,68 @@ static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
 		1000 / (2 * LFPS_CYCLE_COUNT);
 }
 
+#define ML_PHY_LOCK_LEN		252
+#define ML_PHY_LOCK_LEN_UHBR	396
+
 static int get_tphy2_p2_to_p0(const struct intel_crtc_state *crtc_state)
 {
-	return 12 * 1000;
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	return HAS_LT_PHY(display) ? 20 * 1000 : 12 * 1000;
+}
+
+static int get_ml_phy_lock_len(const struct intel_crtc_state *crtc_state)
+{
+	return intel_dp_is_uhbr(crtc_state) ? ML_PHY_LOCK_LEN_UHBR : ML_PHY_LOCK_LEN;
 }
 
-static int get_establishment_period(const struct intel_crtc_state *crtc_state)
+static int get_establishment_period(struct intel_dp *intel_dp,
+				    const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(intel_dp);
 	int t1 = 50 * 1000;
-	int tps4 = 252;
-	/* port_clock is link rate in 10kbit/s units */
-	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;
+	/*
+	 * port_clock is link rate in 10kbit/s units, so tML_PHY_LOCK in ns is
+	 * ML_PHY_LOCK Length * Rate Div * 100000 / port_clock
+	 */
+	int tml_phy_lock = get_ml_phy_lock_len(crtc_state) *
+		intel_dp_link_symbol_size(crtc_state->port_clock) * 100000 /
+		crtc_state->port_clock;
+	int lttpr_count = 0;
 	int num_ml_phy_lock, tcds;
 
-	num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
+		num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
+	} else {
+		num_ml_phy_lock = 7;
+
+		lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
+		if (lttpr_count < 0) {
+			drm_dbg_kms(display->drm,
+				    "Invalid LTTPR count (%pe), assuming no LTTPR\n",
+				    ERR_PTR(lttpr_count));
+			lttpr_count = 0;
+		}
+	}
+
 	tcds = num_ml_phy_lock * tml_phy_lock;
 
+	if (lttpr_count > 0) {
+		/* tlw and tcs values are taken from DP2.1 spec */
+		int tlw = 13000;
+		int tcs = 10000;
+		int tlfps_period = get_lfps_cycle_time(crtc_state);
+		int tdcs = SILENCE_PERIOD_TIME + t1 + tcs +
+			   (lttpr_count - 1) * (tlw + tlfps_period);
+		int tacds = 70000;
+		int tds = 7 * tml_phy_lock;
+
+		/* tdrl is same as tcds */
+		return tlw + tlfps_period + tdcs + tacds +
+		       (lttpr_count - 1) * tds + tcds;
+	}
+
+	/* TODO: Add a check for data realign by DPCD 0x116[3] */
 	return SILENCE_PERIOD_TIME + t1 + tcds;
 }
 
@@ -144,13 +190,15 @@ static int get_establishment_period(const struct intel_crtc_state *crtc_state)
  * adding the "+ 1" term ensures all ML_PHY_LOCK sequences that start
  * within the CDS period complete within the CDS period regardless of
  * entry into the period
- * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )
- * TPS4 Length = 252 Symbols
+ * tML_PHY_LOCK = ML_PHY_LOCK Length * ( Rate Div / (Link Rate in Mbps) )
+ * ML_PHY_LOCK Length = 252 symbols for 8b/10b, 396 super symbols for 128b/132b
+ * Rate Div = 10 for 8b/10b, 32 for 128b/132b
  */
-static int _lnl_compute_aux_less_wake_time(const struct intel_crtc_state *crtc_state)
+static int _lnl_compute_aux_less_wake_time(struct intel_dp *intel_dp,
+					   const struct intel_crtc_state *crtc_state)
 {
 	int tphy2_p2_to_p0 = get_tphy2_p2_to_p0(crtc_state);
-	int establishment_period = get_establishment_period(crtc_state);
+	int establishment_period = get_establishment_period(intel_dp, crtc_state);
 
 	return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(crtc_state) +
 			    establishment_period, 1000);
@@ -165,7 +213,7 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
 		lfps_half_cycle;
 
 	aux_less_wake_time =
-		_lnl_compute_aux_less_wake_time(crtc_state);
+		_lnl_compute_aux_less_wake_time(intel_dp, crtc_state);
 	aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
 						       aux_less_wake_time);
 	silence_period = get_silence_period_symbols(crtc_state);
-- 
2.43.0

[PATCH v7 08/20] drm/i915/alpm: Modify AUX_LESS_WAKE_TIME bitfield for xe3lpd

[Animesh Manna]

The AUX_LESS_WAKE_TIME bitfield in ALPM_CTL is widened from 6 bits to
8 bits starting from xe3lpd (display version 35). Add the register mask
and field macro for the wider bitfield and program the wake time using
the appropriate macro based on the display version. Also use the wider
limit when validating the computed wake lines and for the safest params
fallback.

v2: Modify AUX_LESS_WAKE_TIME bitfield for xe3lpd. [Suraj]
v3: Separate out AUX_LESS_WAKE_TIME bitfield change into its own
patch. [Jouni]
v4: Use the wider bitfield limit in aux-less wake time computation
and safest params. [Jouni, sashiko]

Bspec: 71477
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     | 20 +++++++++++++++----
 drivers/gpu/drm/i915/display/intel_psr_regs.h |  2 ++
 2 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index b9e31c29ab96..0083752d94f0 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -204,6 +204,12 @@ static int _lnl_compute_aux_less_wake_time(struct intel_dp *intel_dp,
 			    establishment_period, 1000);
 }
 
+static int get_aux_less_wake_lines_max(struct intel_display *display)
+{
+	return DISPLAY_VER(display) >= 35 ? ALPM_CTL_AUX_LESS_WAKE_TIME_MASK_XE3LPD :
+					    ALPM_CTL_AUX_LESS_WAKE_TIME_MASK;
+}
+
 static int
 _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
 				  struct intel_crtc_state *crtc_state)
@@ -220,14 +226,14 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
 
 	lfps_half_cycle = get_lfps_half_cycle_clocks(crtc_state);
 
-	if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK ||
+	if (aux_less_wake_lines > get_aux_less_wake_lines_max(display) ||
 	    silence_period > PORT_ALPM_CTL_SILENCE_PERIOD_MASK ||
 	    lfps_half_cycle < 1 ||
 	    lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK + 1)
 		return false;
 
 	if (display->params.psr_safest_params)
-		aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK;
+		aux_less_wake_lines = get_aux_less_wake_lines_max(display);
 
 	crtc_state->alpm_state.aux_less_wake_lines = aux_less_wake_lines;
 	crtc_state->alpm_state.silence_period_sym_clocks = silence_period;
@@ -617,10 +623,16 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 	 * check panel support at this point.
 	 */
 	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
+		int wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
+
 		alpm_ctl = ALPM_CTL_ALPM_ENABLE |
 			ALPM_CTL_ALPM_AUX_LESS_ENABLE |
-			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |
-			ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
+			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS;
+
+		if (DISPLAY_VER(display) < 35)
+			alpm_ctl |= ALPM_CTL_AUX_LESS_WAKE_TIME(wake_lines);
+		else
+			alpm_ctl |= ALPM_CTL_AUX_LESS_WAKE_TIME_XE3LPD(wake_lines);
 
 		if (intel_dp->as_sdp_supported)
 			intel_alpm_configure_pr_as_sdp(intel_dp, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 78a05387eab5..124aa74e1dbb 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -301,7 +301,9 @@
 #define  ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES		5
 #define  ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines)	REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK, (lines) - ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES)
 #define  ALPM_CTL_AUX_LESS_WAKE_TIME_MASK		REG_GENMASK(5, 0)
+#define  ALPM_CTL_AUX_LESS_WAKE_TIME_MASK_XE3LPD	REG_GENMASK(7, 0)
 #define  ALPM_CTL_AUX_LESS_WAKE_TIME(val)		REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val)
+#define  ALPM_CTL_AUX_LESS_WAKE_TIME_XE3LPD(val)	REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK_XE3LPD, val)
 
 #define _ALPM_CTL2_A	0x60954
 #define ALPM_CTL2(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A)
-- 
2.43.0

[PATCH v7 09/20] drm/i915/alpm: table based establishment period

[Animesh Manna]

With LTTPRs present, the establishment period calculated by the formula
is shorter than the values tabulated in the DP2.1 VESA spec by roughly
one LFPS period per LTTPR, even when max silence and LFPS periods are
used. This has been observed to cause flip done timeouts during ALPM
testing on a setup with LTTPRs.

Use the establishment period from the VESA spec table for the listed
link rates with 1 to 6 LTTPRs. Fall back to the calculated value for
link rates not in the table, LTTPR counts beyond the table and when no
LTTPR is present, where the formula already matches the spec.

v2: Add check for negative error codes from drm_dp_lttpr_count(). [sashiko]
v3:
- Explain why the spec table is used instead of the formula. [Jouni]
- Drop the no-LTTPR row as the formula matches the spec there.
- Drop link rates without tabulated values and replace the link rate
  enum and switch with a port_clock based lookup table.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 43 ++++++++++++++++++++++-
 1 file changed, 42 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 0083752d94f0..2bf2ca956439 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -124,6 +124,42 @@ static int get_ml_phy_lock_len(const struct intel_crtc_state *crtc_state)
 	return intel_dp_is_uhbr(crtc_state) ? ML_PHY_LOCK_LEN_UHBR : ML_PHY_LOCK_LEN;
 }
 
+/*
+ * Establishment period in ns with LTTPRs, taken from the DP2.1 VESA spec.
+ * The spec values are computed with the max silence and LFPS periods and
+ * are longer than what the formula gives with LTTPRs present. Using the
+ * formula result has been seen to cause flip done timeouts, so prefer the
+ * spec values for the listed link rates.
+ */
+static const struct {
+	int port_clock;
+	int period[6];	/* indexed by LTTPR count - 1 */
+} lttpr_establishment_periods[] = {
+	{  162000, { 155670, 181160, 206650, 232140, 257620, 283110 } },	/* RBR */
+	{  270000, { 151310, 172450, 193580, 214710, 235850, 256980 } },	/* HBR */
+	{  540000, { 148050, 165910, 183780, 201650, 219510, 237380 } },	/* HBR2 */
+	{  810000, { 146960, 163740, 180510, 197290, 214070, 230850 } },	/* HBR3 */
+	{ 1000000, { 153650, 177120, 200590, 224060, 247530, 271000 } },	/* UHBR10 */
+	{ 1350000, { 151350, 172520, 193690, 214860, 236030, 257200 } },	/* UHBR13.5 */
+	{ 2000000, { 149220, 168220, 187290, 206320, 225360, 244390 } },	/* UHBR20 */
+};
+
+static int get_lttpr_establishment_period(int port_clock, int lttpr_count)
+{
+	int i;
+
+	if (lttpr_count < 1 ||
+	    lttpr_count > ARRAY_SIZE(lttpr_establishment_periods[0].period))
+		return 0;
+
+	for (i = 0; i < ARRAY_SIZE(lttpr_establishment_periods); i++) {
+		if (lttpr_establishment_periods[i].port_clock == port_clock)
+			return lttpr_establishment_periods[i].period[lttpr_count - 1];
+	}
+
+	return 0;
+}
+
 static int get_establishment_period(struct intel_dp *intel_dp,
 				    const struct intel_crtc_state *crtc_state)
 {
@@ -137,7 +173,7 @@ static int get_establishment_period(struct intel_dp *intel_dp,
 		intel_dp_link_symbol_size(crtc_state->port_clock) * 100000 /
 		crtc_state->port_clock;
 	int lttpr_count = 0;
-	int num_ml_phy_lock, tcds;
+	int num_ml_phy_lock, tcds, period;
 
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
 		num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
@@ -155,6 +191,11 @@ static int get_establishment_period(struct intel_dp *intel_dp,
 
 	tcds = num_ml_phy_lock * tml_phy_lock;
 
+	period = get_lttpr_establishment_period(crtc_state->port_clock,
+						lttpr_count);
+	if (period)
+		return period;
+
 	if (lttpr_count > 0) {
 		/* tlw and tcs values are taken from DP2.1 spec */
 		int tlw = 13000;
-- 
2.43.0

[PATCH v7 10/20] drm/i915/alpm: Half LFPS cycle calculation

[Animesh Manna]

Add support for half LFPS cycle calculation for DP2.1 ALPM as dependent
parameters got changed.

v1: Initial version.
v2: Avoid returning early. [Jani]
v3: Use intel_crtc_has_type(). [Suraj]
v4: Split in separate function based on HAS_LT_PHY() check. [Jouni]
v5: Use lt_ prefix for the HAS_LT_PHY() specific helper. [Jouni]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 41 ++++++++++++++++++-----
 1 file changed, 33 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 2bf2ca956439..b6de938990dd 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -81,24 +81,49 @@ static int get_silence_period_symbols(const struct intel_crtc_state *crtc_state)
 		1000 / 1000;
 }
 
-static void get_lfps_cycle_min_max_time(const struct intel_crtc_state *crtc_state,
-					int *min, int *max)
+static void lnl_get_lfps_period_min_max_time(const struct intel_crtc_state *crtc_state,
+					     int *min, int *max)
 {
-	if (crtc_state->port_clock < 540000) {
-		*min = 65 * LFPS_CYCLE_COUNT;
-		*max = 75 * LFPS_CYCLE_COUNT;
-	} else {
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
+		if (crtc_state->port_clock < 540000) {
+			*min = 65 * LFPS_CYCLE_COUNT;
+			*max = 75 * LFPS_CYCLE_COUNT;
+		} else {
+			*min = 140;
+			*max = 800;
+		}
+	}
+}
+
+static void lt_get_lfps_period_min_max_time(const struct intel_crtc_state *crtc_state,
+					    int *min, int *max)
+{
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
 		*min = 140;
 		*max = 800;
+	} else {
+		*min = 320;
+		*max = 1600;
 	}
 }
 
+static void get_lfps_period_min_max_time(const struct intel_crtc_state *crtc_state,
+					int *min, int *max)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (HAS_LT_PHY(display))
+		lt_get_lfps_period_min_max_time(crtc_state, min, max);
+	else
+		lnl_get_lfps_period_min_max_time(crtc_state, min, max);
+}
+
 static int get_lfps_cycle_time(const struct intel_crtc_state *crtc_state)
 {
 	int tlfps_cycle_min, tlfps_cycle_max;
 
-	get_lfps_cycle_min_max_time(crtc_state, &tlfps_cycle_min,
-				    &tlfps_cycle_max);
+	get_lfps_period_min_max_time(crtc_state, &tlfps_cycle_min,
+				     &tlfps_cycle_max);
 
 	return tlfps_cycle_min +  (tlfps_cycle_max - tlfps_cycle_min) / 2;
 }
-- 
2.43.0

Re: [PATCH v7 10/20] drm/i915/alpm: Half LFPS cycle calculation

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/i915/alpm: uninitialized variables in get_lfps_cycle_time()
--

commit 5c47cf246b743bb16ee9903923cc22a473083617
Author: Animesh Manna <animesh.manna@intel.com>

drm/i915/alpm: Half LFPS cycle calculation

This patch updates the LFPS cycle period minimum and maximum calculation for
DP2.1 ALPM by splitting it into HAS_LT_PHY() and non-LT-PHY helpers that check
whether the output type is eDP.

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 2bf2ca9564391..b6de938990ddb 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -81,24 +81,49 @@ static int get_silence_period_symbols(const struct intel_crtc_state *crtc_state)
>  		1000 / 1000;
>  }
>  
> -static void get_lfps_cycle_min_max_time(const struct intel_crtc_state *crtc_state,
> -					int *min, int *max)
> +static void lnl_get_lfps_period_min_max_time(const struct intel_crtc_state *crtc_state,
> +					     int *min, int *max)
>  {
> -	if (crtc_state->port_clock < 540000) {
> -		*min = 65 * LFPS_CYCLE_COUNT;
> -		*max = 75 * LFPS_CYCLE_COUNT;
> -	} else {
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
> +		if (crtc_state->port_clock < 540000) {
> +			*min = 65 * LFPS_CYCLE_COUNT;
> +			*max = 75 * LFPS_CYCLE_COUNT;
> +		} else {
> +			*min = 140;
> +			*max = 800;
> +		}
> +	}
> +}
> +
> +static void lt_get_lfps_period_min_max_time(const struct intel_crtc_state *crtc_state,
> +					    int *min, int *max)
> +{
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
>  		*min = 140;
>  		*max = 800;
> +	} else {
> +		*min = 320;
> +		*max = 1600;
>  	}
>  }
>  
> +static void get_lfps_period_min_max_time(const struct intel_crtc_state *crtc_state,
> +					int *min, int *max)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	if (HAS_LT_PHY(display))
> +		lt_get_lfps_period_min_max_time(crtc_state, min, max);
> +	else
> +		lnl_get_lfps_period_min_max_time(crtc_state, min, max);
> +}
> +
>  static int get_lfps_cycle_time(const struct intel_crtc_state *crtc_state)
>  {
>  	int tlfps_cycle_min, tlfps_cycle_max;
>  
> -	get_lfps_cycle_min_max_time(crtc_state, &tlfps_cycle_min,
> -				    &tlfps_cycle_max);
> +	get_lfps_period_min_max_time(crtc_state, &tlfps_cycle_min,
> +				     &tlfps_cycle_max);
>  
>  	return tlfps_cycle_min +  (tlfps_cycle_max - tlfps_cycle_min) / 2;
>  }

[Severity: High]
Can tlfps_cycle_min and tlfps_cycle_max be used uninitialized in
get_lfps_cycle_time()?

In get_lfps_cycle_time(), tlfps_cycle_min and tlfps_cycle_max are declared
without initialization and passed to get_lfps_period_min_max_time(). When
HAS_LT_PHY(display) is false, get_lfps_period_min_max_time() calls
lnl_get_lfps_period_min_max_time(), which only assigns *min and *max when
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) is true.

For non-eDP outputs on !HAS_LT_PHY(display) platforms, *min and *max are
never written before get_lfps_cycle_time() computes:

	return tlfps_cycle_min +  (tlfps_cycle_max - tlfps_cycle_min) / 2;

In particular, get_establishment_period() calls get_lfps_cycle_time() when
lttpr_count > 0, which only occurs in the !intel_crtc_has_type(crtc_state,
INTEL_OUTPUT_EDP) branch:

drivers/gpu/drm/i915/display/intel_alpm.c:get_establishment_period() {
	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
		num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
	} else {
		num_ml_phy_lock = 7;

		lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
		...
	}
	...
	if (lttpr_count > 0) {
		/* tlw and tcs values are taken from DP2.1 spec */
		int tlw = 13000;
		int tcs = 10000;
		int tlfps_period = get_lfps_cycle_time(crtc_state);
		...
	}
}

Would this leave tlfps_cycle_min and tlfps_cycle_max uninitialized at
runtime for non-eDP DP outputs and trigger -Wmaybe-uninitialized or
-Wsometimes-uninitialized warnings during the build?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261026054001.799894-1-animesh.manna@intel.com?part=10

[PATCH v7 11/20] drm/i915/alpm: Modify LFPS cycle count for DP ALPM

[Animesh Manna]

For DP minimum LFPS count is set to minimum 16.

Also use the link symbol clock instead of the link rate when computing
the half LFPS cycle in symbols. Both are the same for 8b/10b, which was
the only case so far with eDP, but they differ for 128b/132b.

v2:
- Drop unneeded comment. [Jouni]
- Use intel_dp_link_symbol_clock() for half LFPS cycle calculation. [Jouni]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index b6de938990dd..1fd528cb7fe6 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -24,7 +24,8 @@
 				(SILENCE_PERIOD_MAX_TIME -	\
 				 SILENCE_PERIOD_MIN_TIME) / 2)
 
-#define LFPS_CYCLE_COUNT 10
+#define LFPS_CYCLE_COUNT	10
+#define LFPS_CYCLE_COUNT_DP	16
 
 bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp)
 {
@@ -128,10 +129,19 @@ static int get_lfps_cycle_time(const struct intel_crtc_state *crtc_state)
 	return tlfps_cycle_min +  (tlfps_cycle_max - tlfps_cycle_min) / 2;
 }
 
+static int get_lfps_cycle_count(const struct intel_crtc_state *crtc_state)
+{
+	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+		return LFPS_CYCLE_COUNT_DP;
+
+	return LFPS_CYCLE_COUNT;
+}
+
 static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
 {
-	return get_lfps_cycle_time(crtc_state) * crtc_state->port_clock / 1000 /
-		1000 / (2 * LFPS_CYCLE_COUNT);
+	return get_lfps_cycle_time(crtc_state) *
+		intel_dp_link_symbol_clock(crtc_state->port_clock) / 1000 /
+		1000 / (2 * get_lfps_cycle_count(crtc_state));
 }
 
 #define ML_PHY_LOCK_LEN		252
@@ -742,7 +752,7 @@ void intel_alpm_port_configure(struct intel_dp *intel_dp,
 			PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
 			PORT_ALPM_CTL_SILENCE_PERIOD(
 				crtc_state->alpm_state.silence_period_sym_clocks);
-		lfps_ctl_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(LFPS_CYCLE_COUNT) |
+		lfps_ctl_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(get_lfps_cycle_count(crtc_state)) |
 			PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
 				crtc_state->alpm_state.lfps_half_cycle_num_of_syms) |
 			PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
-- 
2.43.0

[PATCH v7 12/20] drm/i915/alpm: Modify LFPS_CYCLE_COUNT bitfield for xe3lpd

[Animesh Manna]

The LFPS_CYCLE_COUNT bitfield in PORT_ALPM_LFPS_CTL is widened from
4 bits (27:24) to 7 bits (30:24) starting from xe3lpd. Add the wider
register mask and field macro, and program the cycle count using the
appropriate macro based on the display version.

v2: Split in a separate patch. [Jouni]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     | 11 ++++++++++-
 drivers/gpu/drm/i915/display/intel_psr_regs.h |  2 ++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 1fd528cb7fe6..f3c0884989ce 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -747,12 +747,21 @@ void intel_alpm_port_configure(struct intel_dp *intel_dp,
 		return;
 
 	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
+		int lfps_cycle = get_lfps_cycle_count(crtc_state);
+		u32 lfps_cycle_val;
+
+		if (DISPLAY_VER(display) >= 35)
+			lfps_cycle_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_XE3LPD(lfps_cycle);
+		else
+			lfps_cycle_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(lfps_cycle);
+
 		alpm_ctl_val = PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
 			PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
 			PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
 			PORT_ALPM_CTL_SILENCE_PERIOD(
 				crtc_state->alpm_state.silence_period_sym_clocks);
-		lfps_ctl_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(get_lfps_cycle_count(crtc_state)) |
+
+		lfps_ctl_val = lfps_cycle_val |
 			PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
 				crtc_state->alpm_state.lfps_half_cycle_num_of_syms) |
 			PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 124aa74e1dbb..aee4f2592302 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -335,8 +335,10 @@
 #define PORT_ALPM_LFPS_CTL(port)				_MMIO_PORT(port, _PORT_ALPM_LFPS_CTL_A, _PORT_ALPM_LFPS_CTL_B)
 #define  PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY			REG_BIT(31)
 #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK		REG_GENMASK(27, 24)
+#define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK_XE3LPD	REG_GENMASK(30, 24)
 #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN		7
 #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(val)		REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK, (val) - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN)
+#define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_XE3LPD(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK_XE3LPD, (val) - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN)
 /*
  * The LFPS half cycle duration fields (including the first and last half
  * cycle) are zero-based, i.e. the value programmed is N_Symbol - 1.
-- 
2.43.0

[PATCH v7 13/20] drm/i915/alpm: Program LTTPR count for DP 2.1 ALPM

[Animesh Manna]

Issue a AUX write transaction to DPCD DP_TOTAL_LTTPR_CNT (0xf000a)
with total number of LTTPR before link training.

v2: Cosmetic changes. [Suraj]
v3:
- Use same encoding format for lttpr_count. [Jouni]
- Avoid reading alpm_ctl2 register. [Jouni]
v4:
- Program DP_TOTAL_LTTPR_CNT only for DP, not eDP. [Jouni, sashiko]
- Drop redundant lttpr_count check. [Jouni, sashiko]
- Check drm_dp_lttpr_count() return value before programming
  ALPM_CTL2. [Jouni, sashiko]
- Fix LTTPR revision check to match the comment. [sashiko]
- Use drm_dp_dpcd_write_byte(). [Jani]

Cc: Jouni Högander <jouni.hogander@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     | 10 +++++++++-
 .../drm/i915/display/intel_dp_link_training.c | 20 +++++++++++++++++++
 2 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index f3c0884989ce..831dfa5e677b 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -687,7 +687,8 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-	u32 alpm_ctl;
+	u32 alpm_ctl, alpm_ctl2;
+	int lttpr_count;
 
 	if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
 					  !crtc_state->has_lobf))
@@ -725,6 +726,13 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 
 	alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(crtc_state->alpm_state.check_entry_lines);
 
+	lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
+	if (lttpr_count < 0)
+		lttpr_count = 0;
+
+	alpm_ctl2 = ALPM_CTL2_NUMBER_OF_LTTPR(lttpr_count);
+
+	intel_de_write(display, ALPM_CTL2(display, cpu_transcoder), alpm_ctl2);
 	intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl);
 	mutex_unlock(&intel_dp->alpm.lock);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index ac1aff6edf05..0dbc6174c402 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -2271,6 +2271,24 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
 	return passed;
 }
 
+static void intel_dp_update_lttpr_count(struct intel_dp *intel_dp)
+{
+	u8 val;
+
+	/*
+	 * Program only for DP and return if LTTPR revision is less than 0x20
+	 * where 0:3 represents minor rev and 4:7 represent major rev
+	 */
+	if (intel_dp_is_edp(intel_dp) ||
+	    intel_dp->lttpr_common_caps[0] < 0x20)
+		return;
+
+	val = intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT -
+					  DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
+	if (drm_dp_dpcd_write_byte(&intel_dp->aux, DP_TOTAL_LTTPR_CNT, val) < 0)
+		lt_dbg(intel_dp, DP_PHY_DPRX, "Failed to write total LTTPR count\n");
+}
+
 /**
  * intel_dp_start_link_train - start link training
  * @state: Atomic state
@@ -2310,6 +2328,8 @@ void intel_dp_start_link_train(struct intel_atomic_state *state,
 
 	intel_dp_prepare_link_train(intel_dp, crtc_state);
 
+	intel_dp_update_lttpr_count(intel_dp);
+
 	if (intel_dp_is_uhbr(crtc_state))
 		passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count);
 	else
-- 
2.43.0

[PATCH v7 14/20] drm/i915/alpm: Enable MAC Transmitting LFPS for LT PHY

[Animesh Manna]

Enable MAC to transmit LFPS via LT PHY during aux-less alpm.

v2:
- Correct commit description. [Suraj]
- Remove loop as no dependency on the transmitter LT_PHY_CMN_CTL0. [Suraj]
v3: Cosmetic changes. [Suraj]
v4:
- Add Bspec reference. [Jouni]
- Rename intel_xe3plpd_mac_transmit_lfps() to
  intel_lt_mac_transmit_lfps(). [Jouni]
- Rename LT_PHY_CMN_LFPS_ENABLE to LT_PHY_CMN_MAC_TRANSMIT_LFPS to
  follow Bspec. [Jouni]

Bspec: 74500
Cc: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      |  5 +++-
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 27 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |  2 ++
 .../gpu/drm/i915/display/intel_lt_phy_regs.h  |  3 +++
 4 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a46ab5d3d70f..6a196df2691e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3808,7 +3808,10 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
 	 *     ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE
 	 *         register
 	 */
-	intel_lnl_mac_transmit_lfps(encoder, crtc_state);
+	if (HAS_LT_PHY(display))
+		intel_lt_mac_transmit_lfps(encoder, crtc_state);
+	else
+		intel_lnl_mac_transmit_lfps(encoder, crtc_state);
 }
 
 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 86492651b01d..5b26957d7fb9 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -5,6 +5,7 @@
 
 #include <drm/drm_print.h>
 
+#include "intel_alpm.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_ddi.h"
@@ -2357,3 +2358,29 @@ void intel_lt_phy_verify_plls(struct intel_display *display)
 	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_edp_tables);
 	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_hdmi_tables);
 }
+
+/*
+ * According to HAS we need to enable MAC Transmitting LFPS in the "PHY Common
+ * Control 0" PIPE register in case of AUX Less ALPM is going to be used. This
+ * function is doing that and is called by link retrain sequence.
+ */
+void intel_lt_mac_transmit_lfps(struct intel_encoder *encoder,
+				const struct intel_crtc_state *crtc_state)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	struct ref_tracker *wakeref;
+	u8 owned_lane_mask;
+
+	if (!intel_alpm_is_alpm_aux_less(intel_dp, crtc_state))
+		return;
+
+	wakeref = intel_lt_phy_transaction_begin(encoder);
+
+	owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
+
+	intel_lt_phy_rmw(encoder, owned_lane_mask, LT_PHY_CMN_CTL_0,
+			 LT_PHY_CMN_MAC_TRANSMIT_LFPS,
+			 LT_PHY_CMN_MAC_TRANSMIT_LFPS, MB_WRITE_COMMITTED);
+
+	intel_lt_phy_transaction_end(encoder, wakeref);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 16de39484779..1c3e9e200749 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -49,5 +49,7 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_dpll_hw_state *dpll_hw_state);
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
 void intel_lt_phy_verify_plls(struct intel_display *display);
+void intel_lt_mac_transmit_lfps(struct intel_encoder *encoder,
+				const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_LT_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
index ff6d7829dbb9..a48da8315413 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
@@ -35,6 +35,9 @@
 #define LT_PHY_TXY_CTL10_MAC(idx)	_MMIO(LT_PHY_TXY_CTL10(idx))
 #define  LT_PHY_TX_LANE_ENABLE		REG_BIT8(0)
 
+#define LT_PHY_CMN_CTL_0		(0x800)
+#define  LT_PHY_CMN_MAC_TRANSMIT_LFPS	REG_BIT8(1)
+
 /* LT Phy Vendor Register */
 #define LT_PHY_VDR_0_CONFIG	0xC02
 #define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)
-- 
2.43.0

[PATCH v7 15/20] drm/i915/alpm: Compute and program switch to active latency

[Animesh Manna]

Program the ALPM switch to active latency into ALPM_CTL2. For UHBR link
rates the latency is derived from the link symbol clock and converted to
scanlines, for non-UHBR rates it is zero.

v2: Use macro instead of magic number wherever possible. [Jouni]
v3:
- Use intel_dp_link_symbol_clock(). [Jouni]
- Fix switch to active time which was 32 times too long as the symbol
  clock already accounts for the 32 bits per symbol. [sashiko]
- Round the switch to active time up to microseconds. [sashiko]
- Check the switch to active latency fits into ALPM_CTL2. [sashiko]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     | 35 +++++++++++++++++--
 .../drm/i915/display/intel_display_types.h    |  1 +
 2 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 831dfa5e677b..4e761022485d 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -250,6 +250,31 @@ static int get_establishment_period(struct intel_dp *intel_dp,
 	return SILENCE_PERIOD_TIME + t1 + tcds;
 }
 
+static int get_switch_to_active(const struct intel_crtc_state *crtc_state)
+{
+	int switch_to_active;
+
+	if (intel_dp_is_uhbr(crtc_state)) {
+		/* link symbol clock (fLink / 32) in kHz */
+		int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock);
+
+		/*
+		 * tSwitch to Active = 32 * (ML_PHY_LOCK Length + 3 + 64) / fLink
+		 *		     = (ML_PHY_LOCK Length + 3 + 64) / symbol clock
+		 *
+		 * The "+ 3" term is the trailing zero padding after the
+		 * POST_LT_SCRAMBLER_RESET, the "+ 64" term represents the MTP
+		 * time slots. The result is rounded up to microseconds.
+		 */
+		switch_to_active = DIV_ROUND_UP((ML_PHY_LOCK_LEN_UHBR + 3 + 64) * 1000,
+						symbol_clock);
+	} else {
+		switch_to_active = 0;
+	}
+
+	return switch_to_active;
+}
+
 /*
  * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+
  * tSilence, Max+ tPHY Establishment + tCDS) / tline)
@@ -292,7 +317,7 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	int aux_less_wake_time, aux_less_wake_lines, silence_period,
-		lfps_half_cycle;
+		lfps_half_cycle, switch_to_active_lines;
 
 	aux_less_wake_time =
 		_lnl_compute_aux_less_wake_time(intel_dp, crtc_state);
@@ -302,10 +327,14 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
 
 	lfps_half_cycle = get_lfps_half_cycle_clocks(crtc_state);
 
+	switch_to_active_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
+							  get_switch_to_active(crtc_state));
+
 	if (aux_less_wake_lines > get_aux_less_wake_lines_max(display) ||
 	    silence_period > PORT_ALPM_CTL_SILENCE_PERIOD_MASK ||
 	    lfps_half_cycle < 1 ||
-	    lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK + 1)
+	    lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK + 1 ||
+	    switch_to_active_lines > REG_FIELD_MAX(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK))
 		return false;
 
 	if (display->params.psr_safest_params)
@@ -314,6 +343,7 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
 	crtc_state->alpm_state.aux_less_wake_lines = aux_less_wake_lines;
 	crtc_state->alpm_state.silence_period_sym_clocks = silence_period;
 	crtc_state->alpm_state.lfps_half_cycle_num_of_syms = lfps_half_cycle;
+	crtc_state->alpm_state.switch_to_active = switch_to_active_lines;
 
 	return true;
 }
@@ -731,6 +761,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 		lttpr_count = 0;
 
 	alpm_ctl2 = ALPM_CTL2_NUMBER_OF_LTTPR(lttpr_count);
+	alpm_ctl2 |= ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(crtc_state->alpm_state.switch_to_active);
 
 	intel_de_write(display, ALPM_CTL2(display, cpu_transcoder), alpm_ctl2);
 	intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d0748837ce97..82a63a2e7fa3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1469,6 +1469,7 @@ struct intel_crtc_state {
 		u8 aux_less_wake_lines;
 		u8 silence_period_sym_clocks;
 		u8 lfps_half_cycle_num_of_syms;
+		int switch_to_active;
 	} alpm_state;
 
 	/* to track changes in plane color blocks */
-- 
2.43.0

[PATCH v7 16/20] drm/i915/alpm: Replace is_edp() with alpm_is_possible()

[Animesh Manna]

Add a separate alpm_is_possible() which will check for alpm
capability from dpcd info.

ALPM is possible if the sink supports AUX-wake or AUX-less ALPM. With
LTTPRs present only AUX-less ALPM is possible, so both the sink and the
LTTPRs must support AUX-less ALPM.

LOBF enable/disable are only called based on has_lobf in the crtc state,
which is computed using alpm_is_possible(), so drop the capability check
from there. This also avoids leaving ALPM_CTL enabled on hot-unplug, as
the sink capabilities are reset before LOBF is disabled.

v2: Drop DISPLAY_VER() check as intel_alpm_source_supported
already checking and populating dpcd info. [Jouni]
v3:
- Check ALPM capability bits of sink and LTTPR. [sashiko]
- Drop alpm_is_possible() check from LOBF enable/disable. [Jouni, sashiko]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 30 +++++++++++++++++------
 drivers/gpu/drm/i915/display/intel_alpm.h |  1 +
 2 files changed, 23 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 4e761022485d..205f1ae10d43 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -76,6 +76,25 @@ void intel_alpm_init(struct intel_dp *intel_dp)
 	mutex_init(&intel_dp->alpm.lock);
 }
 
+bool intel_alpm_is_possible(struct intel_dp *intel_dp)
+{
+	u8 lttpr_alpm_caps;
+
+	if (!(intel_dp->alpm_dpcd & (DP_ALPM_CAP | DP_ALPM_AUX_LESS_CAP)))
+		return false;
+
+	if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps) <= 0)
+		return true;
+
+	/* With LTTPRs only AUX-less ALPM is possible and LTTPRs must support it */
+	lttpr_alpm_caps =
+		intel_dp->lttpr_common_caps[DP_LTTPR_ALPM_CAPABILITIES -
+					    DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
+
+	return intel_alpm_aux_less_wake_supported(intel_dp) &&
+	       lttpr_alpm_caps & DP_LTTPR_AUX_LESS_ALPM_SUPPORTED;
+}
+
 static int get_silence_period_symbols(const struct intel_crtc_state *crtc_state)
 {
 	return SILENCE_PERIOD_TIME * intel_dp_link_symbol_clock(crtc_state->port_clock) /
@@ -537,7 +556,7 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
 	if (intel_dp->alpm.sink_alpm_error)
 		return;
 
-	if (!intel_dp_is_edp(intel_dp))
+	if (!intel_alpm_is_possible(intel_dp))
 		return;
 
 	if (DISPLAY_VER(display) < 20)
@@ -829,9 +848,6 @@ void intel_alpm_lobf_disable(const struct intel_crtc_state *new_crtc_state)
 
 		intel_dp = enc_to_intel_dp(encoder);
 
-		if (!intel_dp_is_edp(intel_dp))
-			continue;
-
 		mutex_lock(&intel_dp->alpm.lock);
 		intel_de_write(display, ALPM_CTL(display, cpu_transcoder), 0);
 		drm_dbg_kms(display->drm, "Link off between frames (LOBF) disabled\n");
@@ -870,10 +886,8 @@ void intel_alpm_lobf_enable(const struct intel_crtc_state *new_crtc_state)
 
 		intel_dp = enc_to_intel_dp(encoder);
 
-		if (intel_dp_is_edp(intel_dp)) {
-			intel_alpm_enable_sink(intel_dp, new_crtc_state);
-			intel_alpm_configure(intel_dp, new_crtc_state);
-		}
+		intel_alpm_enable_sink(intel_dp, new_crtc_state);
+		intel_alpm_configure(intel_dp, new_crtc_state);
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index 1cb226bc342a..9319572c221e 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -17,6 +17,7 @@ struct intel_crtc;
 
 int intel_alpm_init_dpcd(struct intel_dp *intel_dp);
 void intel_alpm_init(struct intel_dp *intel_dp);
+bool intel_alpm_is_possible(struct intel_dp *intel_dp);
 bool intel_alpm_compute_params(struct intel_dp *intel_dp,
 			       struct intel_crtc_state *crtc_state);
 void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
-- 
2.43.0

Re: [PATCH v7 16/20] drm/i915/alpm: Replace is_edp() with alpm_is_possible()

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/i915/alpm: uninitialized mutex lock in intel_alpm_lobf_disable()
--

commit 3691f816d97c5d3f84209f1900c4bc02406c352b
Author: Animesh Manna <animesh.manna@intel.com>

drm/i915/alpm: Replace is_edp() with alpm_is_possible()

This commit introduces intel_alpm_is_possible() to check ALPM capability
from DPCD and LTTPR info instead of checking intel_dp_is_edp() in
intel_alpm_lobf_compute_config(). It also removes the intel_dp_is_edp()
checks from intel_alpm_lobf_enable() and intel_alpm_lobf_disable().

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 4e761022485d7..205f1ae10d431 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c

[ ... ]

> @@ -829,9 +848,6 @@ void intel_alpm_lobf_disable(const struct intel_crtc_state *new_crtc_state)
>  
>  		intel_dp = enc_to_intel_dp(encoder);
>  
> -		if (!intel_dp_is_edp(intel_dp))
> -			continue;
> -
>  		mutex_lock(&intel_dp->alpm.lock);
>  		intel_de_write(display, ALPM_CTL(display, cpu_transcoder), 0);
>  		drm_dbg_kms(display->drm, "Link off between frames (LOBF) disabled\n");

[Severity: High]
Can removing the intel_dp_is_edp() check in intel_alpm_lobf_disable() cause
mutex_lock(&intel_dp->alpm.lock) to be called on an uninitialized mutex?

In drivers/gpu/drm/i915/display/intel_alpm.c, intel_alpm_init() only
initializes alpm.lock when intel_alpm_source_supported(intel_dp) is true:

void intel_alpm_init(struct intel_dp *intel_dp)
{
	if (!intel_alpm_source_supported(intel_dp))
		return;

	mutex_init(&intel_dp->alpm.lock);
}

On platforms with DISPLAY_VER between 20 and 34, intel_alpm_source_supported()
is only true for eDP encoders, so non-eDP DP encoders leave alpm.lock
uninitialized.

In drivers/gpu/drm/i915/display/intel_display.c, intel_pre_plane_update()
checks whether LOBF is being disabled via intel_crtc_lobf_disabling(), which
inspects old_crtc_state->has_lobf, but then passes new_crtc_state to
intel_alpm_lobf_disable():

	if (intel_crtc_lobf_disabling(old_crtc_state, new_crtc_state))
		intel_alpm_lobf_disable(new_crtc_state);

If a CRTC with LOBF active on an eDP encoder (old_crtc_state->has_lobf is
true) is switched in an atomic modeset to a non-eDP DP encoder
(new_crtc_state->has_lobf is false), intel_alpm_lobf_disable() iterates over
new_crtc_state->uapi.encoder_mask and calls mutex_lock(&intel_dp->alpm.lock)
on the non-eDP encoder whose mutex was never initialized.

Additionally, because intel_alpm_lobf_disable() inspects new_crtc_state
rather than old_crtc_state, disabling a CRTC by detaching its connector
(leaving new_crtc_state->uapi.encoder_mask empty) skips the loop and leaves
ALPM_CTL enabled, or on DISPLAY_VER >= 35 locks the new encoder's alpm.lock
instead of the old encoder's.

Should intel_pre_plane_update() pass old_crtc_state to
intel_alpm_lobf_disable(const struct intel_crtc_state *old_crtc_state) so it
operates on the encoder and transcoder where LOBF was previously enabled?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261026054001.799894-1-animesh.manna@intel.com?part=16

[PATCH v7 17/20] drm/i915/alpm: Disallow ALPM for UHBR link rate

[Animesh Manna]

DP2.1 ALPM is not supported on UHBR (128b/132b) link rates on the NVL
platform. Report ALPM as not possible in intel_alpm_is_possible() for
external DP running at a UHBR rate on display version 35, so that ALPM
and the features relying on it are not enabled in that case. eDP is
excluded so eDP ALPM keeps working at any link rate.

v2:
- Move the check into intel_alpm_is_possible(). [Jouni]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 11 +++++++++--
 drivers/gpu/drm/i915/display/intel_alpm.h |  3 ++-
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 205f1ae10d43..3123296df6b2 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -76,13 +76,20 @@ void intel_alpm_init(struct intel_dp *intel_dp)
 	mutex_init(&intel_dp->alpm.lock);
 }
 
-bool intel_alpm_is_possible(struct intel_dp *intel_dp)
+bool intel_alpm_is_possible(struct intel_dp *intel_dp,
+			    const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(intel_dp);
 	u8 lttpr_alpm_caps;
 
 	if (!(intel_dp->alpm_dpcd & (DP_ALPM_CAP | DP_ALPM_AUX_LESS_CAP)))
 		return false;
 
+	/* DP2.1 ALPM is not supported on UHBR (128b/132b) link rates on NVL. */
+	if (DISPLAY_VER(display) == 35 && !intel_dp_is_edp(intel_dp) &&
+	    intel_dp_is_uhbr(crtc_state))
+		return false;
+
 	if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps) <= 0)
 		return true;
 
@@ -556,7 +563,7 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
 	if (intel_dp->alpm.sink_alpm_error)
 		return;
 
-	if (!intel_alpm_is_possible(intel_dp))
+	if (!intel_alpm_is_possible(intel_dp, crtc_state))
 		return;
 
 	if (DISPLAY_VER(display) < 20)
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index 9319572c221e..24c319bc5eff 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -17,7 +17,8 @@ struct intel_crtc;
 
 int intel_alpm_init_dpcd(struct intel_dp *intel_dp);
 void intel_alpm_init(struct intel_dp *intel_dp);
-bool intel_alpm_is_possible(struct intel_dp *intel_dp);
+bool intel_alpm_is_possible(struct intel_dp *intel_dp,
+			    const struct intel_crtc_state *crtc_state);
 bool intel_alpm_compute_params(struct intel_dp *intel_dp,
 			       struct intel_crtc_state *crtc_state);
 void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
-- 
2.43.0

[PATCH v7 18/20] drm/i915/alpm: Compute ALPM config before PSR config

[Animesh Manna]

The ALPM params are computed by alpm_config_valid() while computing the
PSR config and again by intel_alpm_lobf_compute_config() for LOBF.

Add intel_alpm_compute_config() which computes the ALPM params once
before the PSR config and records whether AUX wake and AUX-less ALPM
are possible in alpm_state.aux_wake_possible and
alpm_state.aux_less_possible. Do the LOBF compute from there as well.
alpm_config_valid() now uses these flags to choose between PSR, PSR2
and Panel Replay.

No functional change intended.

Suggested-by: Jouni Högander <jouni.hogander@intel.com>
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     | 33 +++++++++++++++----
 drivers/gpu/drm/i915/display/intel_alpm.h     |  6 +---
 .../drm/i915/display/intel_display_types.h    |  4 +++
 drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |  8 +++--
 5 files changed, 38 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 3123296df6b2..65d06e8ebbe0 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -426,8 +426,8 @@ static int io_buffer_wake_time(const struct intel_crtc_state *crtc_state)
 		return skl_io_buffer_wake_time();
 }
 
-bool intel_alpm_compute_params(struct intel_dp *intel_dp,
-			       struct intel_crtc_state *crtc_state)
+static bool intel_alpm_compute_params(struct intel_dp *intel_dp,
+				      struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	int io_wake_lines, io_wake_time, fast_wake_lines, fast_wake_time;
@@ -549,9 +549,8 @@ void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
 			       (first_sdp_position + waketime_in_lines);
 }
 
-void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
-				    struct intel_crtc_state *crtc_state,
-				    struct drm_connector_state *conn_state)
+static void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
+					   struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 
@@ -579,10 +578,32 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
 	      intel_alpm_aux_less_wake_supported(intel_dp)))
 		return;
 
+	crtc_state->has_lobf = true;
+}
+
+/*
+ * Compute the ALPM params and whether AUX wake / AUX-less ALPM is possible for
+ * the mode and the sink. PSR and Panel Replay use these to choose the feature.
+ */
+void intel_alpm_compute_config(struct intel_dp *intel_dp,
+			       struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	if (!intel_dp_is_edp(intel_dp) && !intel_alpm_is_possible(intel_dp, crtc_state))
+		return;
+
 	if (!intel_alpm_compute_params(intel_dp, crtc_state))
 		return;
 
-	crtc_state->has_lobf = true;
+	crtc_state->alpm_state.aux_wake_possible = true;
+	crtc_state->alpm_state.aux_less_possible =
+		DISPLAY_VER(display) >= 20 &&
+		(intel_dp_is_edp(intel_dp) ||
+		 (intel_alpm_is_possible(intel_dp, crtc_state) &&
+		  intel_alpm_aux_less_wake_supported(intel_dp)));
+
+	intel_alpm_lobf_compute_config(intel_dp, crtc_state);
 }
 
 static u32 get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index 24c319bc5eff..be9b4d761c13 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -10,7 +10,6 @@
 
 struct intel_dp;
 struct intel_crtc_state;
-struct drm_connector_state;
 struct intel_connector;
 struct intel_atomic_state;
 struct intel_crtc;
@@ -19,11 +18,8 @@ int intel_alpm_init_dpcd(struct intel_dp *intel_dp);
 void intel_alpm_init(struct intel_dp *intel_dp);
 bool intel_alpm_is_possible(struct intel_dp *intel_dp,
 			    const struct intel_crtc_state *crtc_state);
-bool intel_alpm_compute_params(struct intel_dp *intel_dp,
+void intel_alpm_compute_config(struct intel_dp *intel_dp,
 			       struct intel_crtc_state *crtc_state);
-void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
-				    struct intel_crtc_state *crtc_state,
-				    struct drm_connector_state *conn_state);
 void intel_alpm_configure(struct intel_dp *intel_dp,
 			  const struct intel_crtc_state *crtc_state);
 void intel_alpm_enable_sink(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 82a63a2e7fa3..ce7dc3375f2e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1470,6 +1470,10 @@ struct intel_crtc_state {
 		u8 silence_period_sym_clocks;
 		u8 lfps_half_cycle_num_of_syms;
 		int switch_to_active;
+
+		/* ALPM params are valid for the mode and the sink */
+		bool aux_wake_possible;
+		bool aux_less_possible;
 	} alpm_state;
 
 	/* to track changes in plane color blocks */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c543fe551eb8..7827de39e826 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3822,9 +3822,9 @@ intel_dp_compute_config(struct intel_atomic_state *state,
 		pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
 
 	intel_vrr_compute_config(pipe_config, conn_state);
+	intel_alpm_compute_config(intel_dp, pipe_config);
 	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
 	intel_dp_compute_as_sdp(intel_dp, pipe_config);
-	intel_alpm_lobf_compute_config(intel_dp, pipe_config, conn_state);
 	intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
 	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
 	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 4ae47d33096a..c00ec3f64202 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1462,16 +1462,18 @@ static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
 }
 
 static bool alpm_config_valid(struct intel_dp *intel_dp,
-			      struct intel_crtc_state *crtc_state,
+			      const struct intel_crtc_state *crtc_state,
 			      bool aux_less,
 			      bool needs_panel_replay,
 			      bool needs_sel_update)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
+	bool alpm_possible = aux_less ? crtc_state->alpm_state.aux_less_possible :
+					crtc_state->alpm_state.aux_wake_possible;
 
-	if (!intel_alpm_compute_params(intel_dp, crtc_state)) {
+	if (!alpm_possible) {
 		drm_dbg_kms(display->drm,
-			    "PSR2/Panel Replay  not enabled, Unable to use long enough wake times\n");
+			    "PSR2/Panel Replay not enabled, ALPM not possible\n");
 		return false;
 	}
 
-- 
2.43.0

[PATCH v7 19/20] drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf

[Animesh Manna]

For DP2.1, ALPM (Advanced Link Power Management) is optional: Panel
Replay can be supported without ALPM. Until now ALPM enablement was
derived implicitly from other features - eDP Panel Replay and PSR2
always implied ALPM (intel_psr_needs_alpm()), while LOBF was tracked
separately via has_lobf - so this scattered, feature-coupled logic
cannot express "Panel Replay without ALPM".

Introduce a single crtc_state->has_alpm flag as the source of truth for
whether ALPM is enabled. It is set in one place, in the new
intel_alpm_compute_config_late(), once the final PSR, Panel Replay and
LOBF state is known:

 - eDP Panel Replay and PSR2 always use ALPM.
 - DP Panel Replay uses ALPM only if AUX-less ALPM is possible and its
   wake time fits, otherwise Panel Replay is used without ALPM.
 - Otherwise ALPM follows LOBF.

intel_alpm_compute_config_late() also does the late LOBF checks that
intel_alpm_lobf_compute_config_late() did before.

Use has_alpm in the ALPM configure and sink enable paths, and require
it in intel_alpm_is_aux_less() (renamed from
intel_alpm_is_alpm_aux_less()) so that AUX-less ALPM programming,
including the AS SDP part of PR_ALPM_CTL and the MAC transmit LFPS, is
skipped when ALPM is not used. Require the ALPM DPCD caps for AUX-less
ALPM on eDP as well.

v2:
- Set has_alpm in one place in intel_alpm_compute_config_late(). [Jouni]
- Don't let selective update overwrite has_alpm. [sashiko]
- Don't leave has_alpm set when PSR features are dropped late. [sashiko]
- Keep clearing the port ALPM registers when ALPM is not used. [sashiko]
- Require has_alpm for AUX-less ALPM programming. [sashiko]
- Keep ALPM enabled for PSR2 regardless of the ALPM DPCD caps.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     | 55 +++++++++++++------
 drivers/gpu/drm/i915/display/intel_alpm.h     |  8 +--
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  2 +-
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 11 +++-
 drivers/gpu/drm/i915/display/intel_psr.h      |  3 +-
 8 files changed, 57 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 65d06e8ebbe0..47263af0970c 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -37,11 +37,12 @@ bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp)
 	return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP;
 }
 
-bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
-				 const struct intel_crtc_state *crtc_state)
+bool intel_alpm_is_aux_less(struct intel_dp *intel_dp,
+			    const struct intel_crtc_state *crtc_state)
 {
-	return intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) ||
-		(crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));
+	return crtc_state->has_alpm &&
+	       (crtc_state->has_panel_replay ||
+		(crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp)));
 }
 
 static bool intel_alpm_source_supported(struct intel_dp *intel_dp)
@@ -509,8 +510,8 @@ static bool intel_alpm_lobf_is_window1_sufficient(struct intel_crtc_state *crtc_
 	return window1 > crtc_state->alpm_state.check_entry_lines;
 }
 
-void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
-					 struct intel_crtc_state *crtc_state)
+static void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
+						struct intel_crtc_state *crtc_state)
 {
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	int waketime_in_lines, first_sdp_position;
@@ -598,14 +599,34 @@ void intel_alpm_compute_config(struct intel_dp *intel_dp,
 
 	crtc_state->alpm_state.aux_wake_possible = true;
 	crtc_state->alpm_state.aux_less_possible =
-		DISPLAY_VER(display) >= 20 &&
-		(intel_dp_is_edp(intel_dp) ||
-		 (intel_alpm_is_possible(intel_dp, crtc_state) &&
-		  intel_alpm_aux_less_wake_supported(intel_dp)));
+		DISPLAY_VER(display) >= 20 && intel_alpm_is_possible(intel_dp, crtc_state) &&
+		(intel_dp_is_edp(intel_dp) || intel_alpm_aux_less_wake_supported(intel_dp));
 
 	intel_alpm_lobf_compute_config(intel_dp, crtc_state);
 }
 
+/*
+ * Decide whether ALPM is enabled once PSR, Panel Replay and LOBF have been
+ * finalized. eDP Panel Replay and PSR2 always use ALPM, for DP Panel Replay
+ * ALPM is optional and used only if the AUX-less wake time fits.
+ */
+void intel_alpm_compute_config_late(struct intel_dp *intel_dp,
+				    struct intel_crtc_state *crtc_state)
+{
+	int aux_less_wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
+
+	intel_alpm_lobf_compute_config_late(intel_dp, crtc_state);
+
+	if (crtc_state->has_psr && crtc_state->has_panel_replay)
+		crtc_state->has_alpm = intel_dp_is_edp(intel_dp) ||
+			(crtc_state->alpm_state.aux_less_possible &&
+			 intel_psr_wake_lines_fit_into_vblank(crtc_state, aux_less_wake_lines));
+	else if (crtc_state->has_psr && crtc_state->has_sel_update)
+		crtc_state->has_alpm = intel_dp_is_edp(intel_dp);
+	else
+		crtc_state->has_alpm = crtc_state->has_lobf;
+}
+
 static u32 get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *crtc_state)
 {
 	u8 as_sdp_setup_time = intel_dp_as_sdp_transmission_time();
@@ -750,7 +771,7 @@ void intel_alpm_pr_as_sdp_update(const struct intel_crtc_state *crtc_state)
 		intel_dp = enc_to_intel_dp(encoder);
 
 		if (!intel_dp->as_sdp_supported ||
-		    !intel_alpm_is_alpm_aux_less(intel_dp, crtc_state))
+		    !intel_alpm_is_aux_less(intel_dp, crtc_state))
 			continue;
 
 		mutex_lock(&intel_dp->alpm.lock);
@@ -767,8 +788,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 	u32 alpm_ctl, alpm_ctl2;
 	int lttpr_count;
 
-	if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
-					  !crtc_state->has_lobf))
+	if (DISPLAY_VER(display) < 20 || !crtc_state->has_alpm)
 		return;
 
 	mutex_lock(&intel_dp->alpm.lock);
@@ -776,7 +796,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 	 * Panel Replay on eDP is always using ALPM aux less. I.e. no need to
 	 * check panel support at this point.
 	 */
-	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
+	if (intel_alpm_is_aux_less(intel_dp, crtc_state)) {
 		int wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
 
 		alpm_ctl = ALPM_CTL_ALPM_ENABLE |
@@ -832,7 +852,7 @@ void intel_alpm_port_configure(struct intel_dp *intel_dp,
 	if (DISPLAY_VER(display) < 20)
 		return;
 
-	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
+	if (intel_alpm_is_aux_less(intel_dp, crtc_state)) {
 		int lfps_cycle = get_lfps_cycle_count(crtc_state);
 		u32 lfps_cycle_val;
 
@@ -888,13 +908,12 @@ void intel_alpm_enable_sink(struct intel_dp *intel_dp,
 {
 	u8 val;
 
-	if (!intel_psr_needs_alpm(intel_dp, crtc_state) && !crtc_state->has_lobf)
+	if (!crtc_state->has_alpm)
 		return;
 
 	val = DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE;
 
-	if (crtc_state->has_panel_replay || (crtc_state->has_lobf &&
-					     intel_alpm_aux_less_wake_supported(intel_dp)))
+	if (intel_alpm_is_aux_less(intel_dp, crtc_state))
 		val |= DP_ALPM_MODE_AUX_LESS;
 
 	drm_dp_dpcd_write_byte(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val);
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index be9b4d761c13..a35a98a55a8d 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -31,14 +31,14 @@ void intel_alpm_lobf_enable(const struct intel_crtc_state *new_crtc_state);
 void intel_alpm_lobf_debugfs_add(struct intel_connector *connector);
 bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp);
 bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp);
-bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
-				 const struct intel_crtc_state *crtc_state);
+bool intel_alpm_is_aux_less(struct intel_dp *intel_dp,
+			    const struct intel_crtc_state *crtc_state);
 bool intel_alpm_pr_as_sdp_skip_frames_enabled(struct intel_dp *intel_dp,
 					      const struct intel_crtc_state *crtc_state);
 void intel_alpm_pr_as_sdp_update(const struct intel_crtc_state *crtc_state);
 void intel_alpm_disable(struct intel_dp *intel_dp);
 bool intel_alpm_get_error(struct intel_dp *intel_dp);
-void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
-					 struct intel_crtc_state *crtc_state);
+void intel_alpm_compute_config_late(struct intel_dp *intel_dp,
+				    struct intel_crtc_state *crtc_state);
 int intel_alpm_lobf_min_guardband(struct intel_crtc_state *crtc_state);
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 814615fe9951..453526c4b3a9 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3453,7 +3453,7 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
 	u8 owned_lane_mask;
 
 	if (DISPLAY_VER(display) < 20 ||
-	    !intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder), crtc_state))
+	    !intel_alpm_is_aux_less(enc_to_intel_dp(encoder), crtc_state))
 		return;
 
 	owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ce7dc3375f2e..73d82df2ff92 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1475,6 +1475,7 @@ struct intel_crtc_state {
 		bool aux_wake_possible;
 		bool aux_less_possible;
 	} alpm_state;
+	bool has_alpm;
 
 	/* to track changes in plane color blocks */
 	bool plane_color_changed;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7827de39e826..43b17d2ed93f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7594,7 +7594,7 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder,
 	if (ret)
 		return ret;
 
-	intel_alpm_lobf_compute_config_late(intel_dp, crtc_state);
+	intel_alpm_compute_config_late(intel_dp, crtc_state);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 5b26957d7fb9..74ef0d29756c 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2371,7 +2371,7 @@ void intel_lt_mac_transmit_lfps(struct intel_encoder *encoder,
 	struct ref_tracker *wakeref;
 	u8 owned_lane_mask;
 
-	if (!intel_alpm_is_alpm_aux_less(intel_dp, crtc_state))
+	if (!intel_alpm_is_aux_less(intel_dp, crtc_state))
 		return;
 
 	wakeref = intel_lt_phy_transaction_begin(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index c00ec3f64202..4c429a14b50e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1426,6 +1426,14 @@ static bool _wake_lines_fit_into_vblank(const struct intel_crtc_state *crtc_stat
 	return true;
 }
 
+bool intel_psr_wake_lines_fit_into_vblank(const struct intel_crtc_state *crtc_state,
+					  int wake_lines)
+{
+	return _wake_lines_fit_into_vblank(crtc_state,
+					   intel_crtc_vblank_length(crtc_state),
+					   wake_lines);
+}
+
 static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
 				       const struct intel_crtc_state *crtc_state,
 				       bool aux_less,
@@ -4547,7 +4555,8 @@ void intel_psr_connector_debugfs_add(struct intel_connector *connector)
 				    connector, &i915_psr_status_fops);
 }
 
-bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state)
+static bool intel_psr_needs_alpm(struct intel_dp *intel_dp,
+				 const struct intel_crtc_state *crtc_state)
 {
 	/*
 	 * eDP Panel Replay uses always ALPM
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index d545fdaa0de7..2557776a402b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -79,9 +79,10 @@ void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
 int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state);
 void intel_psr_connector_debugfs_add(struct intel_connector *connector);
 void intel_psr_debugfs_register(struct intel_display *display);
-bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state);
 bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
 				   const struct intel_crtc_state *crtc_state);
+bool intel_psr_wake_lines_fit_into_vblank(const struct intel_crtc_state *crtc_state,
+					  int wake_lines);
 void intel_psr_compute_config_late(struct intel_dp *intel_dp,
 				   struct intel_crtc_state *crtc_state);
 int intel_psr_min_guardband(struct intel_crtc_state *crtc_state);
-- 
2.43.0

Re: [PATCH v7 19/20] drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] drm/i915/alpm: ALPM left enabled on DP Panel Replay disable or !has_alpm
- [Medium] drm/i915/alpm: intel_psr_min_guardband() skips DP Panel Replay ALPM wake lines
--

commit 599e7704f4924a7a5dd73754cb1a7ffd13dae956
Author: Animesh Manna <animesh.manna@intel.com>

drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf

This patch introduces crtc_state->has_alpm in intel_alpm_compute_config_late()
to decouple ALPM enablement from Panel Replay, PSR2, and LOBF so that DP 2.1
Panel Replay can operate with or without ALPM.

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 65d06e8ebbe06..47263af0970cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
[ ... ]
> @@ -598,14 +599,34 @@ void intel_alpm_compute_config(struct intel_dp *intel_dp,
>  
>  	crtc_state->alpm_state.aux_wake_possible = true;
>  	crtc_state->alpm_state.aux_less_possible =
> -		DISPLAY_VER(display) >= 20 &&
> -		(intel_dp_is_edp(intel_dp) ||
> -		 (intel_alpm_is_possible(intel_dp, crtc_state) &&
> -		  intel_alpm_aux_less_wake_supported(intel_dp)));
> +		DISPLAY_VER(display) >= 20 && intel_alpm_is_possible(intel_dp, crtc_state) &&
> +		(intel_dp_is_edp(intel_dp) || intel_alpm_aux_less_wake_supported(intel_dp));
>  
>  	intel_alpm_lobf_compute_config(intel_dp, crtc_state);
>  }
>  
> +/*
> + * Decide whether ALPM is enabled once PSR, Panel Replay and LOBF have been
> + * finalized. eDP Panel Replay and PSR2 always use ALPM, for DP Panel Replay
> + * ALPM is optional and used only if the AUX-less wake time fits.
> + */
> +void intel_alpm_compute_config_late(struct intel_dp *intel_dp,
> +				    struct intel_crtc_state *crtc_state)
> +{
> +	int aux_less_wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
> +
> +	intel_alpm_lobf_compute_config_late(intel_dp, crtc_state);
> +
> +	if (crtc_state->has_psr && crtc_state->has_panel_replay)
> +		crtc_state->has_alpm = intel_dp_is_edp(intel_dp) ||
> +			(crtc_state->alpm_state.aux_less_possible &&
> +			 intel_psr_wake_lines_fit_into_vblank(crtc_state, aux_less_wake_lines));

[Severity: Medium]
Can intel_psr_wake_lines_fit_into_vblank() fail to enable crtc_state->has_alpm
on external DP Panel Replay because intel_psr_min_guardband() does not reserve
aux_less_wake_lines for non-eDP outputs?

On DISPLAY_VER(display) >= 35, intel_vrr_always_use_vrr_tg() and
intel_vrr_use_optimized_guardband() are used, so before
intel_dp_compute_config_late() -> intel_alpm_compute_config_late() runs,
intel_crtc_compute_config() -> intel_vrr_compute_guardband() ->
intel_vrr_compute_optimized_guardband() computes crtc_state->vrr.guardband and
adjusts crtc_vblank_start:

drivers/gpu/drm/i915/display/intel_vrr.c:intel_vrr_compute_optimized_guardband() {
	...
	if (intel_crtc_has_dp_encoder(crtc_state)) {
		guardband = max(guardband, intel_psr_min_guardband(crtc_state));
		guardband = max(guardband, intel_dp_sdp_min_guardband(crtc_state, true));
		guardband = max(guardband, intel_alpm_lobf_min_guardband(crtc_state));
	}
	...
}

drivers/gpu/drm/i915/display/intel_vrr.c:intel_vrr_compute_guardband() {
	...
	if (intel_vrr_always_use_vrr_tg(display)) {
		adjusted_mode->crtc_vblank_start  =
			adjusted_mode->crtc_vtotal - crtc_state->vrr.guardband;
	...
}

However, intel_psr_min_guardband() in drivers/gpu/drm/i915/display/intel_psr.c
currently skips non-eDP encoders:

drivers/gpu/drm/i915/display/intel_psr.c:intel_psr_min_guardband() {
	...
	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
		return 0;

	if (crtc_state->has_panel_replay)
		wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
	...
}

When crtc_state->has_lobf is false (for example, when !intel_dp->as_sdp_supported,
intel_dp->alpm.lobf_disable_debug is set, or intel_dp->alpm.sink_alpm_error is
set), intel_alpm_lobf_min_guardband() also returns 0. That shrinks
crtc_state->vrr.guardband (and therefore intel_crtc_vblank_length(crtc_state))
to the prefill/SDP guardband, which can be smaller than aux_less_wake_lines
even when the mode's full vblank is large enough.

Should intel_psr_min_guardband() also reserve aux_less_wake_lines for external
DP Panel Replay when crtc_state->alpm_state.aux_less_possible is true?

> +	else if (crtc_state->has_psr && crtc_state->has_sel_update)
> +		crtc_state->has_alpm = intel_dp_is_edp(intel_dp);
> +	else
> +		crtc_state->has_alpm = crtc_state->has_lobf;
> +}
[ ... ]
> @@ -767,8 +788,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  	u32 alpm_ctl, alpm_ctl2;
>  	int lttpr_count;
>  
> -	if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
> -					  !crtc_state->has_lobf))
> +	if (DISPLAY_VER(display) < 20 || !crtc_state->has_alpm)
>  		return;
[ ... ]
> @@ -888,13 +908,12 @@ void intel_alpm_enable_sink(struct intel_dp *intel_dp,
>  {
>  	u8 val;
>  
> -	if (!intel_psr_needs_alpm(intel_dp, crtc_state) && !crtc_state->has_lobf)
> +	if (!crtc_state->has_alpm)
>  		return;
>  
>  	val = DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE;
>  
> -	if (crtc_state->has_panel_replay || (crtc_state->has_lobf &&
> -					     intel_alpm_aux_less_wake_supported(intel_dp)))
> +	if (intel_alpm_is_aux_less(intel_dp, crtc_state))
>  		val |= DP_ALPM_MODE_AUX_LESS;
>  
>  	drm_dp_dpcd_write_byte(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val);

[Severity: High]
With crtc_state->has_alpm now enabling ALPM in lnl_alpm_configure() and
intel_alpm_enable_sink() for non-eDP Panel Replay, can ALPM remain enabled on
both the source and sink when DP Panel Replay is later disabled or reconfigured
to !crtc_state->has_alpm?

In drivers/gpu/drm/i915/display/intel_psr.c, intel_psr_disable_locked() still
guards intel_alpm_disable() with intel_dp_is_edp() and only clears
DP_RECEIVER_ALPM_CONFIG when !intel_dp->psr.panel_replay_enabled:

drivers/gpu/drm/i915/display/intel_psr.c:intel_psr_disable_locked() {
	...
	if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp))
		intel_alpm_disable(intel_dp);

	/* Disable PSR on Sink */
	if (!intel_dp->psr.panel_replay_enabled) {
		drm_dp_dpcd_write_byte(&intel_dp->aux, DP_PSR_EN_CFG, 0);

		if (intel_dp->psr.sel_update_enabled)
			drm_dp_dpcd_write_byte(&intel_dp->aux,
					       DP_RECEIVER_ALPM_CONFIG, 0);
	}
}

When external DP Panel Replay (!intel_dp_is_edp(intel_dp)) with ALPM is
disabled without a full encoder disable (such as in
intel_psr_pre_plane_update() when all planes become inactive, during fastsets,
or on a sink error in intel_psr_short_pulse()), intel_alpm_disable() is skipped
and ALPM_CTL_ALPM_ENABLE stays set in ALPM_CTL. Subsequent re-enables in
intel_psr_post_plane_update() -> intel_psr_enable_locked() ->
intel_psr_enable_source() -> intel_alpm_configure() -> lnl_alpm_configure()
then rewrite ALPM_CTL, ALPM_CTL2, and PR_ALPM_CTL while ALPM is still enabled
in hardware.

Furthermore, because neither intel_psr_disable_locked() nor
intel_alpm_enable_sink() clears DP_RECEIVER_ALPM_CONFIG for Panel Replay when
transitioning to !crtc_state->has_alpm, won't DP_RECEIVER_ALPM_CONFIG remain
enabled on the sink (and ALPM_CTL remain enabled on the source across a
fastset) if a subsequent commit runs Panel Replay without ALPM?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261026054001.799894-1-animesh.manna@intel.com?part=19

[PATCH v7 20/20] drm/i915/dp: Enable AS SDP for DP Panel Replay with AUX-less ALPM

[Animesh Manna]

AS SDP for Panel Replay with AUX-less ALPM and the related
DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE setting are limited to eDP by
intel_psr_needs_alpm_aux_less(). DP Panel Replay can now use AUX-less
ALPM as well, so base these on the ALPM state instead.

has_alpm is decided only in the late compute config, after AS SDP has
been computed. Use alpm_state.aux_less_possible to decide whether AS
SDP is needed, and has_alpm for the link training DPCD setting, which
happens with the final state.

intel_psr_needs_alpm_aux_less() is now used only within intel_psr.c,
so make it static.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c               | 4 +++-
 drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
 drivers/gpu/drm/i915/display/intel_psr.c              | 4 ++--
 drivers/gpu/drm/i915/display/intel_psr.h              | 2 --
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 43b17d2ed93f..02ea3f2b00ac 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3274,7 +3274,9 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
 	if (drm_dp_is_branch(intel_dp->dpcd))
 		return false;
 
-	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) &&
+	/* has_alpm is not final yet, so check if AUX-less ALPM is possible */
+	if (crtc_state->has_panel_replay &&
+	    crtc_state->alpm_state.aux_less_possible &&
 	    !intel_psr_pr_async_video_timing_supported(intel_dp))
 		return true;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 0dbc6174c402..c7a3cfd29e37 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1124,7 +1124,7 @@ static bool
 intel_dp_pr_with_as_sdp_enabled(struct intel_dp *intel_dp,
 				const struct intel_crtc_state *crtc_state)
 {
-	return intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) &&
+	return crtc_state->has_panel_replay && crtc_state->has_alpm &&
 		(crtc_state->infoframes.enable &
 		 intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC));
 }
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 4c429a14b50e..0875de33f0da 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -4566,8 +4566,8 @@ static bool intel_psr_needs_alpm(struct intel_dp *intel_dp,
 					     crtc_state->has_panel_replay);
 }
 
-bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
-				   const struct intel_crtc_state *crtc_state)
+static bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
+					  const struct intel_crtc_state *crtc_state)
 {
 	return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 2557776a402b..8adb27c21408 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -79,8 +79,6 @@ void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
 int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state);
 void intel_psr_connector_debugfs_add(struct intel_connector *connector);
 void intel_psr_debugfs_register(struct intel_display *display);
-bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
-				   const struct intel_crtc_state *crtc_state);
 bool intel_psr_wake_lines_fit_into_vblank(const struct intel_crtc_state *crtc_state,
 					  int wake_lines);
 void intel_psr_compute_config_late(struct intel_dp *intel_dp,
-- 
2.43.0

✗ i915.CI.BAT: failure for Enable DP2.1 alpm (rev7)

[Patchwork]

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== Series Details ==

Series: Enable DP2.1 alpm (rev7)
URL   : https://patchwork.freedesktop.org/series/156417/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_19394 -> Patchwork_156417v7
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_156417v7 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_156417v7, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/index.html

Participating hosts (40 -> 39)
------------------------------

  Missing    (1): bat-dg2-13 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_156417v7:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live:
    - bat-rpls-4:         [PASS][1] -> [INCOMPLETE][2] +1 other test incomplete
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19394/bat-rpls-4/igt@i915_selftest@live.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/bat-rpls-4/igt@i915_selftest@live.html
    - fi-skl-6600u:       [PASS][3] -> [INCOMPLETE][4] +1 other test incomplete
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19394/fi-skl-6600u/igt@i915_selftest@live.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/fi-skl-6600u/igt@i915_selftest@live.html

  
Known issues
------------

  Here are the changes found in Patchwork_156417v7 that come from known issues:

### IGT changes ###

#### Warnings ####

  * igt@kms_flip@basic-flip-vs-dpms:
    - fi-kbl-x1275:       [SKIP][5] -> [SKIP][6] ([i915#3637]) +3 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19394/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-dpms.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-dpms.html

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - fi-bsw-nick:        [SKIP][7] -> [SKIP][8] ([i915#3637]) +3 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19394/fi-bsw-nick/igt@kms_flip@basic-flip-vs-wf_vblank.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/fi-bsw-nick/igt@kms_flip@basic-flip-vs-wf_vblank.html
    - bat-kbl-2:          [SKIP][9] -> [SKIP][10] ([i915#3637]) +3 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19394/bat-kbl-2/igt@kms_flip@basic-flip-vs-wf_vblank.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/bat-kbl-2/igt@kms_flip@basic-flip-vs-wf_vblank.html

  * igt@kms_flip@basic-plain-flip:
    - fi-kbl-8809g:       [SKIP][11] -> [SKIP][12] ([i915#3637]) +3 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19394/fi-kbl-8809g/igt@kms_flip@basic-plain-flip.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/fi-kbl-8809g/igt@kms_flip@basic-plain-flip.html

  * igt@kms_psr@psr-cursor-plane-move:
    - fi-cfl-guc:         [SKIP][13] -> [SKIP][14] ([i915#9732]) +3 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19394/fi-cfl-guc/igt@kms_psr@psr-cursor-plane-move.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/fi-cfl-guc/igt@kms_psr@psr-cursor-plane-move.html

  * igt@kms_psr@psr-primary-mmap-gtt:
    - fi-bsw-n3050:       [SKIP][15] -> [SKIP][16] ([i915#9732]) +3 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19394/fi-bsw-n3050/igt@kms_psr@psr-primary-mmap-gtt.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/fi-bsw-n3050/igt@kms_psr@psr-primary-mmap-gtt.html
    - fi-pnv-d510:        [SKIP][17] -> [SKIP][18] ([i915#9732]) +3 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19394/fi-pnv-d510/igt@kms_psr@psr-primary-mmap-gtt.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/fi-pnv-d510/igt@kms_psr@psr-primary-mmap-gtt.html

  * igt@kms_psr@psr-primary-page-flip:
    - fi-glk-j4005:       [SKIP][19] -> [SKIP][20] ([i915#9732]) +3 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19394/fi-glk-j4005/igt@kms_psr@psr-primary-page-flip.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/fi-glk-j4005/igt@kms_psr@psr-primary-page-flip.html
    - fi-kbl-7567u:       [SKIP][21] -> [SKIP][22] ([i915#9732]) +3 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19394/fi-kbl-7567u/igt@kms_psr@psr-primary-page-flip.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/fi-kbl-7567u/igt@kms_psr@psr-primary-page-flip.html
    - bat-apl-1:          [SKIP][23] -> [SKIP][24] ([i915#9732]) +3 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19394/bat-apl-1/igt@kms_psr@psr-primary-page-flip.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/bat-apl-1/igt@kms_psr@psr-primary-page-flip.html
    - fi-kbl-x1275:       [SKIP][25] -> [SKIP][26] ([i915#9732]) +3 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19394/fi-kbl-x1275/igt@kms_psr@psr-primary-page-flip.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/fi-kbl-x1275/igt@kms_psr@psr-primary-page-flip.html
    - fi-cfl-8109u:       [SKIP][27] -> [SKIP][28] ([i915#9732]) +3 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19394/fi-cfl-8109u/igt@kms_psr@psr-primary-page-flip.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/fi-cfl-8109u/igt@kms_psr@psr-primary-page-flip.html
    - fi-kbl-8809g:       [SKIP][29] -> [SKIP][30] ([i915#9732]) +3 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19394/fi-kbl-8809g/igt@kms_psr@psr-primary-page-flip.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/fi-kbl-8809g/igt@kms_psr@psr-primary-page-flip.html
    - fi-ilk-650:         [SKIP][31] -> [SKIP][32] ([i915#9732]) +3 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19394/fi-ilk-650/igt@kms_psr@psr-primary-page-flip.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/fi-ilk-650/igt@kms_psr@psr-primary-page-flip.html

  * igt@kms_psr@psr-sprite-plane-onoff:
    - fi-cfl-8700k:       [SKIP][33] -> [SKIP][34] ([i915#9732]) +3 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19394/fi-cfl-8700k/igt@kms_psr@psr-sprite-plane-onoff.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/fi-cfl-8700k/igt@kms_psr@psr-sprite-plane-onoff.html
    - fi-bsw-nick:        [SKIP][35] -> [SKIP][36] ([i915#9732]) +3 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19394/fi-bsw-nick/igt@kms_psr@psr-sprite-plane-onoff.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/fi-bsw-nick/igt@kms_psr@psr-sprite-plane-onoff.html
    - bat-kbl-2:          [SKIP][37] -> [SKIP][38] ([i915#9732]) +3 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19394/bat-kbl-2/igt@kms_psr@psr-sprite-plane-onoff.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/bat-kbl-2/igt@kms_psr@psr-sprite-plane-onoff.html
    - fi-ivb-3770:        [SKIP][39] -> [SKIP][40] ([i915#9732]) +3 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19394/fi-ivb-3770/igt@kms_psr@psr-sprite-plane-onoff.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/fi-ivb-3770/igt@kms_psr@psr-sprite-plane-onoff.html
    - fi-elk-e7500:       [SKIP][41] -> [SKIP][42] ([i915#9732]) +3 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19394/fi-elk-e7500/igt@kms_psr@psr-sprite-plane-onoff.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/fi-elk-e7500/igt@kms_psr@psr-sprite-plane-onoff.html

  
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732


Build changes
-------------

  * Linux: CI_DRM_19394 -> Patchwork_156417v7

  CI-20190529: 20190529
  CI_DRM_19394: d56ff005f0d16ec136ee31fe3238eb447fefdc1a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_9163: 9163
  Patchwork_156417v7: d56ff005f0d16ec136ee31fe3238eb447fefdc1a @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v7/index.html

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