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From: sashiko-bot@kernel.org
To: "Xiao Lu" <xiaolu.xie@intel.com>,
	intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/ltphy: Fix the HDMI PLL setup for a DCO below 11.85 GHz
Date: Wed, 11 Nov 2026 11:26:43 +0000	[thread overview]
Message-ID: <sashiko-outbox-208874@kernel.org> (raw)
In-Reply-To: <20261111111218.23625-1-xiaolu.xie@intel.com>

Thank you for your contribution! Sashiko AI review found no new issues
in this patch, but noticed 1 related pre-existing issue it does not
introduce:
- [Medium] drm/i915/display: stack info leak in
  intel_lt_phy_pll_verify_params() [1]
--

commit 9dffcca944ff63de33d8799f124267caa2f452f4
Author: Xiao Lu <xiaolu.xie@intel.com>

drm/i915/ltphy: Fix the HDMI PLL setup for a DCO below 11.85 GHz

This commit updates calculate_target_dco_and_loop_cnt() to return the lower
limit of the matched DCO range and compares the target DCO against that
limit in intel_lt_phy_calculate_hdmi_state().

> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 86492651b01d5..a6374b07aeac5 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c

[ ... ]

> @@ -1548,7 +1550,9 @@ intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
>  		(ndiv << 9) + (1 << 4);
>  	p.bias_trim.val = (csel2fo_ovrd_en << 30) + (csel2fo << 24);
>  	p.ssc_inj.val = 0;
> -	found = calculate_target_dco_and_loop_cnt(frequency_khz, &target_dco_mhz, &loop_cnt);
> +	/* dco_fmin becomes the lower limit of the DCO range the solution is in */
> +	found = calculate_target_dco_and_loop_cnt(frequency_khz, &target_dco_mhz, &loop_cnt,
> +						  &dco_fmin);
>  	if (!found)
>  		return -EINVAL;

[Severity: Medium]
This problem wasn't introduced by this patch, but can
intel_lt_phy_calculate_hdmi_state() leave parts of lt_state uninitialized
[1]?

intel_lt_phy_calculate_hdmi_state() does not write lt_state->config[2],
ssc_enabled, tbt_mode, or lane_count.  intel_lt_phy_pll_verify_params()
passes an uninitialized stack pll_state to it, and if a state mismatch
occurs, intel_lt_phy_pll_verify_clock() -> intel_lt_phy_dump_hw_state()
prints those uninitialized stack fields to dmesg.

[1] https://sashiko.dev/#/bug/linux-548b8df6-aa56-451e-bde9-6adc09def6f8

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261111111218.23625-1-xiaolu.xie@intel.com?part=1

  reply	other threads:[~2026-11-11 11:26 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-11 11:12 [PATCH] drm/i915/ltphy: Fix the HDMI PLL setup for a DCO below 11.85 GHz Xiao Lu
2026-11-11 11:26 ` sashiko-bot [this message]
2026-11-11 14:43 ` ✓ i915.CI.BAT: success for " Patchwork
2026-11-12  5:06 ` ✗ i915.CI.Full: failure " Patchwork

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