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* [PATCH] drm/i915/ltphy: Fix the HDMI PLL setup for a DCO below 11.85 GHz
@ 2026-11-11 11:12 Xiao Lu
  2026-11-11 11:26 ` sashiko-bot
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Xiao Lu @ 2026-11-11 11:12 UTC (permalink / raw)
  To: intel-gfx, intel-xe
  Cc: suraj.kandpal, ankit.k.nautiyal, mika.kahola, jani.nikula,
	rodrigo.vivi, Xiao Lu

The HDMI PLL algorithm looks for a DCO frequency in the 11850 - 16200 MHz
range first and, if there is no solution, in the 10000 - 12000 MHz range.
The result is then treated as a low ("12G") DCO if it is below the fixed
DCO_MIN_FREQ_MHZ (11850 MHz). That selects different loop filter and DCO
fine settings, and makes pll_type 0, so the PLL registers are written at
the USB PLL addresses.

For a port clock between about 540 and 592.5 MHz neither y = 4 nor y = 6
gives a DCO in the 11850 - 16200 MHz range, so the solution is always
found in the second range, with a DCO between 10000 and 11850 MHz.
2560x1440@144 (580.1 MHz, DCO 11602 MHz) is such a mode. On NVL, with the
sink connected through a DP dual mode adaptor (Parade PS8219), the sink
never locks at this mode: SCDC Status_Flags (0x40) never read 0x0f, the
sink drops HPD within about 10 seconds of the modeset, and the compositor
falls back to 2560x1440@120 (497.76 MHz, DCO 14932 MHz), which works. The
same sink works at 144 Hz on the same machine with the Windows driver,
which compares the DCO with the lower limit of the DCO range the solution
was found in (10000 MHz for the second range) instead.

Do the same here. Make calculate_target_dco_and_loop_cnt() return the
lower limit of the DCO range it used and compare the DCO with that, so
a DCO found in the second range is not treated as a 12G DCO anymore.
The PLL then uses pll_type 1 (DP PLL), prop_coeff 3, int_coeff 7,
ana_cfg 8 and the regular DCO fine settings, like for any other port
clock.

Port clocks outside of that 540 - 592.5 MHz window get the same result as
before. Tested on NVL with 2560x1440@144 only: the sink locks (SCDC
Status_Flags 0x0f) and there are no HPD drops.

Fixes: 6fedb7bf73d7 ("drm/i915/ltphy: Implement HDMI Algo for Pll state")
Bspec: 74667
Signed-off-by: Xiao Lu <xiaolu.xie@intel.com>
---

Notes:
    With this the 12G branches (prop_coeff 4, int_coeff 8, ana_cfg 6, dco_12g) are
    never taken any more, since a solution is by construction not below the
    lower limit of its own DCO range. I kept them to keep the fix small, and
    can drop them in a follow up if preferred.
    
    Only 2560x1440@144 (580.1 MHz) was tested on hardware. Other port clocks
    in the 540 - 592.5 MHz window, e.g. 3440x1440@100 (543.5 MHz) and
    1920x1080@240 (592 MHz), get the same change but were not tested.

 drivers/gpu/drm/i915/display/intel_lt_phy.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 86492651b0..a6374b07ae 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1360,7 +1360,8 @@ static u64 mul_q32_u32(u64 a_q32, u32 b)
 }
 
 static bool
-calculate_target_dco_and_loop_cnt(u32 frequency_khz, u64 *target_dco_mhz, u32 *loop_cnt)
+calculate_target_dco_and_loop_cnt(u32 frequency_khz, u64 *target_dco_mhz, u32 *loop_cnt,
+				  u32 *dco_min_freq_used)
 {
 	u32 ppm_value = 1;
 	u32 dco_min_freq = DCO_MIN_FREQ_MHZ;
@@ -1401,6 +1402,7 @@ calculate_target_dco_and_loop_cnt(u32 frequency_khz, u64 *target_dco_mhz, u32 *l
 								 scale);
 					*target_dco_mhz = temp0 * scale;
 					*loop_cnt = y;
+					*dco_min_freq_used = dco_min_freq;
 					return true;
 				}
 			}
@@ -1548,7 +1550,9 @@ intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
 		(ndiv << 9) + (1 << 4);
 	p.bias_trim.val = (csel2fo_ovrd_en << 30) + (csel2fo << 24);
 	p.ssc_inj.val = 0;
-	found = calculate_target_dco_and_loop_cnt(frequency_khz, &target_dco_mhz, &loop_cnt);
+	/* dco_fmin becomes the lower limit of the DCO range the solution is in */
+	found = calculate_target_dco_and_loop_cnt(frequency_khz, &target_dco_mhz, &loop_cnt,
+						  &dco_fmin);
 	if (!found)
 		return -EINVAL;
 
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2026-11-12  5:06 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2026-11-11 11:12 [PATCH] drm/i915/ltphy: Fix the HDMI PLL setup for a DCO below 11.85 GHz Xiao Lu
2026-11-11 11:26 ` sashiko-bot
2026-11-11 14:43 ` ✓ i915.CI.BAT: success for " Patchwork
2026-11-12  5:06 ` ✗ i915.CI.Full: failure " Patchwork

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