* [Intel-wired-lan] [PATCH iwl-net v2 1/1] e1000e: Workaround for sporadic MDI error on Meteor Lake systems
@ 2023-10-05 5:44 Vitaly Lifshits
2023-10-09 21:28 ` Jacob Keller
2023-10-10 20:50 ` Jacob Keller
0 siblings, 2 replies; 5+ messages in thread
From: Vitaly Lifshits @ 2023-10-05 5:44 UTC (permalink / raw)
To: intel-wired-lan; +Cc: Vitaly Lifshits, Nikolay Mushayev, Nir Efrati
On some Meteor Lake systems accessing the PHY via the MDIO interface may
result in an MDI error. This issue happens sporadically and in most cases
a second access to the PHY via the MDIO interface results in success.
As a workaround, introduce a retry counter which is set to 3 on Meteor
Lake systems. The driver will only return an error if 3 consecutive PHY
access attempts fail. The retry mechanism is disabled in specific flows,
where MDI errors are expected.
Fixes: cc23f4f0b6b9 ("e1000e: Add support for Meteor Lake")
Suggested-by: Nikolay Mushayev <nikolay.mushayev@intel.com>
Co-developed-by: Nir Efrati <nir.efrati@intel.com>
Signed-off-by: Nir Efrati <nir.efrati@intel.com>
Signed-off-by: Vitaly Lifshits <vitaly.lifshits@intel.com>
---
v2: fix checkpatch errors
v1: initial version
---
drivers/net/ethernet/intel/e1000e/hw.h | 2 +
drivers/net/ethernet/intel/e1000e/ich8lan.c | 33 ++++
drivers/net/ethernet/intel/e1000e/phy.c | 185 ++++++++++++--------
drivers/net/ethernet/intel/e1000e/phy.h | 2 +
4 files changed, 151 insertions(+), 71 deletions(-)
diff --git a/drivers/net/ethernet/intel/e1000e/hw.h b/drivers/net/ethernet/intel/e1000e/hw.h
index 29f9fae35f42..0eb7555e0168 100644
--- a/drivers/net/ethernet/intel/e1000e/hw.h
+++ b/drivers/net/ethernet/intel/e1000e/hw.h
@@ -625,6 +625,7 @@ struct e1000_phy_info {
u32 id;
u32 reset_delay_us; /* in usec */
u32 revision;
+ u32 retry_count;
enum e1000_media_type media_type;
@@ -641,6 +642,7 @@ struct e1000_phy_info {
bool polarity_correction;
bool speed_downgraded;
bool autoneg_wait_to_complete;
+ bool retry_enabled;
};
struct e1000_nvm_info {
diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.c b/drivers/net/ethernet/intel/e1000e/ich8lan.c
index 0c7fd10312c8..1d1a30e2a614 100644
--- a/drivers/net/ethernet/intel/e1000e/ich8lan.c
+++ b/drivers/net/ethernet/intel/e1000e/ich8lan.c
@@ -222,11 +222,18 @@ static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
if (hw->mac.type >= e1000_pch_lpt) {
/* Only unforce SMBus if ME is not active */
if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
+ /* Switching PHY interface always returns MDI error
+ * so disable retry mechanism to avoid wasting time
+ */
+ e1000e_disable_phy_retry(hw);
+
/* Unforce SMBus mode in PHY */
e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
+ e1000e_enable_phy_retry(hw);
+
/* Unforce SMBus mode in MAC */
mac_reg = er32(CTRL_EXT);
mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
@@ -310,6 +317,11 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
goto out;
}
+ /* There is no guarantee that the PHY is accessible at this time
+ * so disable retry mechanism to avoid wasting time
+ */
+ e1000e_disable_phy_retry(hw);
+
/* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
* inaccessible and resetting the PHY is not blocked, toggle the
* LANPHYPC Value bit to force the interconnect to PCIe mode.
@@ -379,6 +391,8 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
break;
}
+ e1000e_enable_phy_retry(hw);
+
hw->phy.ops.release(hw);
if (!ret_val) {
@@ -448,6 +462,11 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
phy->id = e1000_phy_unknown;
+ if (hw->mac.type == e1000_pch_mtp) {
+ phy->retry_count = 2;
+ e1000e_enable_phy_retry(hw);
+ }
+
ret_val = e1000_init_phy_workarounds_pchlan(hw);
if (ret_val)
return ret_val;
@@ -1145,6 +1164,11 @@ s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
if (ret_val)
goto out;
+ /* Switching PHY interface always returns MDI error
+ * so disable retry mechanism to avoid wasting time
+ */
+ e1000e_disable_phy_retry(hw);
+
/* Force SMBus mode in PHY */
ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
if (ret_val)
@@ -1152,6 +1176,8 @@ s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
+ e1000e_enable_phy_retry(hw);
+
/* Force SMBus mode in MAC */
mac_reg = er32(CTRL_EXT);
mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
@@ -1312,6 +1338,11 @@ static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
/* Toggle LANPHYPC Value bit */
e1000_toggle_lanphypc_pch_lpt(hw);
+ /* Switching PHY interface always returns MDI error
+ * so disable retry mechanism to avoid wasting time
+ */
+ e1000e_disable_phy_retry(hw);
+
/* Unforce SMBus mode in PHY */
ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
if (ret_val) {
@@ -1332,6 +1363,8 @@ static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
+ e1000e_enable_phy_retry(hw);
+
/* Unforce SMBus mode in MAC */
mac_reg = er32(CTRL_EXT);
mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
diff --git a/drivers/net/ethernet/intel/e1000e/phy.c b/drivers/net/ethernet/intel/e1000e/phy.c
index 08c3d477dd6f..18bec3d1e349 100644
--- a/drivers/net/ethernet/intel/e1000e/phy.c
+++ b/drivers/net/ethernet/intel/e1000e/phy.c
@@ -107,6 +107,16 @@ s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
}
+void e1000e_disable_phy_retry(struct e1000_hw *hw)
+{
+ hw->phy.retry_enabled = false;
+}
+
+void e1000e_enable_phy_retry(struct e1000_hw *hw)
+{
+ hw->phy.retry_enabled = true;
+}
+
/**
* e1000e_read_phy_reg_mdic - Read MDI control register
* @hw: pointer to the HW structure
@@ -118,57 +128,74 @@ s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
**/
s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
{
+ u32 i, mdic = 0, retry_counter, retry_max;
struct e1000_phy_info *phy = &hw->phy;
- u32 i, mdic = 0;
+ bool success;
if (offset > MAX_PHY_REG_ADDRESS) {
e_dbg("PHY Address %d is out of range\n", offset);
return -E1000_ERR_PARAM;
}
+ retry_max = phy->retry_enabled ? phy->retry_count : 0;
+
/* Set up Op-code, Phy Address, and register offset in the MDI
* Control register. The MAC will take care of interfacing with the
* PHY to retrieve the desired data.
*/
- mdic = ((offset << E1000_MDIC_REG_SHIFT) |
- (phy->addr << E1000_MDIC_PHY_SHIFT) |
- (E1000_MDIC_OP_READ));
+ for (retry_counter = 0; retry_counter <= retry_max; retry_counter++) {
+ success = true;
- ew32(MDIC, mdic);
+ mdic = ((offset << E1000_MDIC_REG_SHIFT) |
+ (phy->addr << E1000_MDIC_PHY_SHIFT) |
+ (E1000_MDIC_OP_READ));
- /* Poll the ready bit to see if the MDI read completed
- * Increasing the time out as testing showed failures with
- * the lower time out
- */
- for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
- udelay(50);
- mdic = er32(MDIC);
- if (mdic & E1000_MDIC_READY)
- break;
- }
- if (!(mdic & E1000_MDIC_READY)) {
- e_dbg("MDI Read PHY Reg Address %d did not complete\n", offset);
- return -E1000_ERR_PHY;
- }
- if (mdic & E1000_MDIC_ERROR) {
- e_dbg("MDI Read PHY Reg Address %d Error\n", offset);
- return -E1000_ERR_PHY;
- }
- if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
- e_dbg("MDI Read offset error - requested %d, returned %d\n",
- offset,
- (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
- return -E1000_ERR_PHY;
+ ew32(MDIC, mdic);
+
+ /* Poll the ready bit to see if the MDI read completed
+ * Increasing the time out as testing showed failures with
+ * the lower time out
+ */
+ for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
+ usleep_range(50, 60);
+ mdic = er32(MDIC);
+ if (mdic & E1000_MDIC_READY)
+ break;
+ }
+ if (!(mdic & E1000_MDIC_READY)) {
+ e_dbg("MDI Read PHY Reg Address %d did not complete\n", offset);
+ success = false;
+ }
+ if (mdic & E1000_MDIC_ERROR) {
+ e_dbg("MDI Read PHY Reg Address %d Error\n", offset);
+ success = false;
+ }
+ if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
+ e_dbg("MDI Read offset error - requested %d, returned %d\n",
+ offset,
+ (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
+ success = false;
+ }
+
+ /* Allow some time after each MDIC transaction to avoid
+ * reading duplicate data in the next MDIC transaction.
+ */
+ if (hw->mac.type == e1000_pch2lan)
+ usleep_range(100, 150);
+
+ if (success) {
+ *data = (u16)mdic;
+ return 0;
+ }
+
+ if (retry_counter != retry_max) {
+ e_dbg("Perform retry on PHY transaction...\n");
+ mdelay(10);
+ }
}
- *data = (u16)mdic;
- /* Allow some time after each MDIC transaction to avoid
- * reading duplicate data in the next MDIC transaction.
- */
- if (hw->mac.type == e1000_pch2lan)
- udelay(100);
- return 0;
+ return -E1000_ERR_PHY;
}
/**
@@ -181,57 +208,73 @@ s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
**/
s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
{
+ u32 i, mdic = 0, retry_counter, retry_max;
struct e1000_phy_info *phy = &hw->phy;
- u32 i, mdic = 0;
+ bool success;
if (offset > MAX_PHY_REG_ADDRESS) {
e_dbg("PHY Address %d is out of range\n", offset);
return -E1000_ERR_PARAM;
}
+ retry_max = phy->retry_enabled ? phy->retry_count : 0;
+
/* Set up Op-code, Phy Address, and register offset in the MDI
* Control register. The MAC will take care of interfacing with the
* PHY to retrieve the desired data.
*/
- mdic = (((u32)data) |
- (offset << E1000_MDIC_REG_SHIFT) |
- (phy->addr << E1000_MDIC_PHY_SHIFT) |
- (E1000_MDIC_OP_WRITE));
+ for (retry_counter = 0; retry_counter <= retry_max; retry_counter++) {
+ success = true;
- ew32(MDIC, mdic);
+ mdic = (((u32)data) |
+ (offset << E1000_MDIC_REG_SHIFT) |
+ (phy->addr << E1000_MDIC_PHY_SHIFT) |
+ (E1000_MDIC_OP_WRITE));
- /* Poll the ready bit to see if the MDI read completed
- * Increasing the time out as testing showed failures with
- * the lower time out
- */
- for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
- udelay(50);
- mdic = er32(MDIC);
- if (mdic & E1000_MDIC_READY)
- break;
- }
- if (!(mdic & E1000_MDIC_READY)) {
- e_dbg("MDI Write PHY Reg Address %d did not complete\n", offset);
- return -E1000_ERR_PHY;
- }
- if (mdic & E1000_MDIC_ERROR) {
- e_dbg("MDI Write PHY Red Address %d Error\n", offset);
- return -E1000_ERR_PHY;
- }
- if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
- e_dbg("MDI Write offset error - requested %d, returned %d\n",
- offset,
- (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
- return -E1000_ERR_PHY;
- }
- /* Allow some time after each MDIC transaction to avoid
- * reading duplicate data in the next MDIC transaction.
- */
- if (hw->mac.type == e1000_pch2lan)
- udelay(100);
+ ew32(MDIC, mdic);
- return 0;
+ /* Poll the ready bit to see if the MDI read completed
+ * Increasing the time out as testing showed failures with
+ * the lower time out
+ */
+ for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
+ usleep_range(50, 60);
+ mdic = er32(MDIC);
+ if (mdic & E1000_MDIC_READY)
+ break;
+ }
+ if (!(mdic & E1000_MDIC_READY)) {
+ e_dbg("MDI Write PHY Reg Address %d did not complete\n", offset);
+ success = false;
+ }
+ if (mdic & E1000_MDIC_ERROR) {
+ e_dbg("MDI Write PHY Red Address %d Error\n", offset);
+ success = false;
+ }
+ if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
+ e_dbg("MDI Write offset error - requested %d, returned %d\n",
+ offset,
+ (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
+ success = false;
+ }
+
+ /* Allow some time after each MDIC transaction to avoid
+ * reading duplicate data in the next MDIC transaction.
+ */
+ if (hw->mac.type == e1000_pch2lan)
+ usleep_range(100, 150);
+
+ if (success)
+ return 0;
+
+ if (retry_counter != retry_max) {
+ e_dbg("Perform retry on PHY transaction...\n");
+ mdelay(10);
+ }
+ }
+
+ return -E1000_ERR_PHY;
}
/**
diff --git a/drivers/net/ethernet/intel/e1000e/phy.h b/drivers/net/ethernet/intel/e1000e/phy.h
index c48777d09523..049bb325b4b1 100644
--- a/drivers/net/ethernet/intel/e1000e/phy.h
+++ b/drivers/net/ethernet/intel/e1000e/phy.h
@@ -51,6 +51,8 @@ s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
void e1000_power_up_phy_copper(struct e1000_hw *hw);
void e1000_power_down_phy_copper(struct e1000_hw *hw);
+void e1000e_disable_phy_retry(struct e1000_hw *hw);
+void e1000e_enable_phy_retry(struct e1000_hw *hw);
s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
--
2.25.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [Intel-wired-lan] [PATCH iwl-net v2 1/1] e1000e: Workaround for sporadic MDI error on Meteor Lake systems
2023-10-05 5:44 [Intel-wired-lan] [PATCH iwl-net v2 1/1] e1000e: Workaround for sporadic MDI error on Meteor Lake systems Vitaly Lifshits
@ 2023-10-09 21:28 ` Jacob Keller
2023-10-10 5:20 ` Neftin, Sasha
2023-10-10 20:50 ` Jacob Keller
1 sibling, 1 reply; 5+ messages in thread
From: Jacob Keller @ 2023-10-09 21:28 UTC (permalink / raw)
To: intel-wired-lan
On 10/4/2023 10:44 PM, Vitaly Lifshits wrote:
> On some Meteor Lake systems accessing the PHY via the MDIO interface may
> result in an MDI error. This issue happens sporadically and in most cases
> a second access to the PHY via the MDIO interface results in success.
>
> As a workaround, introduce a retry counter which is set to 3 on Meteor
> Lake systems. The driver will only return an error if 3 consecutive PHY
> access attempts fail. The retry mechanism is disabled in specific flows,
> where MDI errors are expected.
>
A bit ugly. I assume we don't have any idea of the root cause of MDI issues?
Especially having cases where we disable re-try which is a bit awkward.
I don't have any alternative suggestion tho...
Thanks,
Jake
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-wired-lan] [PATCH iwl-net v2 1/1] e1000e: Workaround for sporadic MDI error on Meteor Lake systems
2023-10-09 21:28 ` Jacob Keller
@ 2023-10-10 5:20 ` Neftin, Sasha
2023-10-10 20:16 ` Keller, Jacob E
0 siblings, 1 reply; 5+ messages in thread
From: Neftin, Sasha @ 2023-10-10 5:20 UTC (permalink / raw)
To: Jacob Keller, intel-wired-lan, Ruinskiy, Dima, Efrati, Nir,
Lifshits, Vitaly
Cc: Neftin, Sasha
On 10/10/2023 0:28, Jacob Keller wrote:
>
>
> On 10/4/2023 10:44 PM, Vitaly Lifshits wrote:
>> On some Meteor Lake systems accessing the PHY via the MDIO interface may
>> result in an MDI error. This issue happens sporadically and in most cases
>> a second access to the PHY via the MDIO interface results in success.
>>
>> As a workaround, introduce a retry counter which is set to 3 on Meteor
>> Lake systems. The driver will only return an error if 3 consecutive PHY
>> access attempts fail. The retry mechanism is disabled in specific flows,
>> where MDI errors are expected.
>>
>
> A bit ugly. I assume we don't have any idea of the root cause of MDI issues?
Agree.
We haven't a root cause yet. This problem is under debugging. We prefer
to keep it in the net-queue for widespread testing meanwhile.
>
> Especially having cases where we disable re-try which is a bit awkward.
> I don't have any alternative suggestion tho...
>
> Thanks,
> Jake
> _______________________________________________
> Intel-wired-lan mailing list
> Intel-wired-lan@osuosl.org
> https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
_______________________________________________
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-wired-lan] [PATCH iwl-net v2 1/1] e1000e: Workaround for sporadic MDI error on Meteor Lake systems
2023-10-10 5:20 ` Neftin, Sasha
@ 2023-10-10 20:16 ` Keller, Jacob E
0 siblings, 0 replies; 5+ messages in thread
From: Keller, Jacob E @ 2023-10-10 20:16 UTC (permalink / raw)
To: Neftin, Sasha, intel-wired-lan@osuosl.org, Ruinskiy, Dima,
Efrati, Nir, Lifshits, Vitaly
> -----Original Message-----
> From: Neftin, Sasha <sasha.neftin@intel.com>
> Sent: Monday, October 9, 2023 10:20 PM
> To: Keller, Jacob E <jacob.e.keller@intel.com>; intel-wired-lan@osuosl.org;
> Ruinskiy, Dima <dima.ruinskiy@intel.com>; Efrati, Nir <nir.efrati@intel.com>;
> Lifshits, Vitaly <vitaly.lifshits@intel.com>
> Cc: Neftin, Sasha <sasha.neftin@intel.com>
> Subject: Re: [Intel-wired-lan] [PATCH iwl-net v2 1/1] e1000e: Workaround for
> sporadic MDI error on Meteor Lake systems
>
> On 10/10/2023 0:28, Jacob Keller wrote:
> >
> >
> > On 10/4/2023 10:44 PM, Vitaly Lifshits wrote:
> >> On some Meteor Lake systems accessing the PHY via the MDIO interface may
> >> result in an MDI error. This issue happens sporadically and in most cases
> >> a second access to the PHY via the MDIO interface results in success.
> >>
> >> As a workaround, introduce a retry counter which is set to 3 on Meteor
> >> Lake systems. The driver will only return an error if 3 consecutive PHY
> >> access attempts fail. The retry mechanism is disabled in specific flows,
> >> where MDI errors are expected.
> >>
> >
> > A bit ugly. I assume we don't have any idea of the root cause of MDI issues?
>
> Agree.
> We haven't a root cause yet. This problem is under debugging. We prefer
> to keep it in the net-queue for widespread testing meanwhile.
>
Makes sense, thanks for the explanation.
> >
> > Especially having cases where we disable re-try which is a bit awkward.
> > I don't have any alternative suggestion tho...
> >
> > Thanks,
> > Jake
> > _______________________________________________
> > Intel-wired-lan mailing list
> > Intel-wired-lan@osuosl.org
> > https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
_______________________________________________
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https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-wired-lan] [PATCH iwl-net v2 1/1] e1000e: Workaround for sporadic MDI error on Meteor Lake systems
2023-10-05 5:44 [Intel-wired-lan] [PATCH iwl-net v2 1/1] e1000e: Workaround for sporadic MDI error on Meteor Lake systems Vitaly Lifshits
2023-10-09 21:28 ` Jacob Keller
@ 2023-10-10 20:50 ` Jacob Keller
1 sibling, 0 replies; 5+ messages in thread
From: Jacob Keller @ 2023-10-10 20:50 UTC (permalink / raw)
To: intel-wired-lan, Nir Efrati, Vitaly Lifshits
On 10/4/2023 10:44 PM, Vitaly Lifshits wrote:
> On some Meteor Lake systems accessing the PHY via the MDIO interface may
> result in an MDI error. This issue happens sporadically and in most cases
> a second access to the PHY via the MDIO interface results in success.
>
> As a workaround, introduce a retry counter which is set to 3 on Meteor
> Lake systems. The driver will only return an error if 3 consecutive PHY
> access attempts fail. The retry mechanism is disabled in specific flows,
> where MDI errors are expected.
>
> Fixes: cc23f4f0b6b9 ("e1000e: Add support for Meteor Lake")
> Suggested-by: Nikolay Mushayev <nikolay.mushayev@intel.com>
> Co-developed-by: Nir Efrati <nir.efrati@intel.com>
> Signed-off-by: Nir Efrati <nir.efrati@intel.com>
> Signed-off-by: Vitaly Lifshits <vitaly.lifshits@intel.com>
> ---
> v2: fix checkpatch errors
> v1: initial version
> ---
This still produces a few long lines (netdev still prefers 80 columns vs
the 100 that is now the default for checkpatch.pl), and there are a few
places where you have multiple sequential blank lines:
WARNING: line length of 88 exceeds 80 columns
#241: FILE: drivers/net/ethernet/intel/e1000e/phy.c:166:
+ e_dbg("MDI Read PHY Reg Address %d did not
complete\n", offset);
WARNING: line length of 87 exceeds 80 columns
#248: FILE: drivers/net/ethernet/intel/e1000e/phy.c:173:
+ if (((mdic & E1000_MDIC_REG_MASK) >>
E1000_MDIC_REG_SHIFT) != offset) {
WARNING: line length of 84 exceeds 80 columns
#251: FILE: drivers/net/ethernet/intel/e1000e/phy.c:176:
+ (mdic & E1000_MDIC_REG_MASK) >>
E1000_MDIC_REG_SHIFT);
CHECK: Please don't use multiple blank lines
#273: FILE: drivers/net/ethernet/intel/e1000e/phy.c:197:
+
+
CHECK: Please don't use multiple blank lines
#334: FILE: drivers/net/ethernet/intel/e1000e/phy.c:234:
+
WARNING: line length of 89 exceeds 80 columns
#348: FILE: drivers/net/ethernet/intel/e1000e/phy.c:248:
+ e_dbg("MDI Write PHY Reg Address %d did not
complete\n", offset);
WARNING: line length of 87 exceeds 80 columns
#355: FILE: drivers/net/ethernet/intel/e1000e/phy.c:255:
+ if (((mdic & E1000_MDIC_REG_MASK) >>
E1000_MDIC_REG_SHIFT) != offset) {
WARNING: line length of 84 exceeds 80 columns
#358: FILE: drivers/net/ethernet/intel/e1000e/phy.c:258:
+ (mdic & E1000_MDIC_REG_MASK) >>
E1000_MDIC_REG_SHIFT);
total: 0 errors, 6 warnings, 2 checks, 343 lines checked
NOTE: For some of the reported defects, checkpatch may be able to
mechanically convert to the typical style using --fix or
--fix-inplace.
Commit 5aa593aaf659 ("e1000e: Workaround for sporadic MDI error on
Meteor Lake systems") has style problems, please review.
NOTE: If any of the errors are false positives, please report
them to the maintainer, see CHECKPATCH in MAINTAINERS.
(you can check this with ./scripts/checkpatch.pl --strict
--max-line-length=80)
Thanks,
Jake
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Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-10-10 20:50 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-10-05 5:44 [Intel-wired-lan] [PATCH iwl-net v2 1/1] e1000e: Workaround for sporadic MDI error on Meteor Lake systems Vitaly Lifshits
2023-10-09 21:28 ` Jacob Keller
2023-10-10 5:20 ` Neftin, Sasha
2023-10-10 20:16 ` Keller, Jacob E
2023-10-10 20:50 ` Jacob Keller
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