* [Intel-wired-lan] [PATCH net v1] ice: Fix DSCP PFC TLV creation
@ 2023-01-25 16:01 Karen Ostrowska
2023-01-25 23:36 ` Tony Nguyen
2023-01-26 8:18 ` Paul Menzel
0 siblings, 2 replies; 7+ messages in thread
From: Karen Ostrowska @ 2023-01-25 16:01 UTC (permalink / raw)
To: intel-wired-lan; +Cc: Karen Ostrowska
From: Dave Ertman <david.m.ertman@intel.com>
When creating the TLV to send to the FW for configuring DSCP
mode PFC, the PFCENABLE field was being masked with a 4 bit
mask (0xF), but this is an 8 bit bitmask for enabled classes
for PFC. This means that traffic classes 4-7 could not be
enabled for PFC.
Remove the mask completely, as it is not necessary, as we are
assigning 8bits to an 8 bit field.
Fixes: 2a87bd73e50d("ice: Add DSCP support")
Signed-off-by: Dave Ertman <david.m.ertman@intel.com>
Signed-off-by: Karen Ostrowska <karen.ostrowska@intel.com>
---
drivers/net/ethernet/intel/ice/ice_dcb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_dcb.c b/drivers/net/ethernet/intel/ice/ice_dcb.c
index 6be02f9b0b8c..789b99963910 100644
--- a/drivers/net/ethernet/intel/ice/ice_dcb.c
+++ b/drivers/net/ethernet/intel/ice/ice_dcb.c
@@ -1372,7 +1372,7 @@ ice_add_dscp_pfc_tlv(struct ice_lldp_org_tlv *tlv, struct ice_dcbx_cfg *dcbcfg)
tlv->ouisubtype = htonl(ouisubtype);
buf[0] = dcbcfg->pfc.pfccap & 0xF;
- buf[1] = dcbcfg->pfc.pfcena & 0xF;
+ buf[1] = dcbcfg->pfc.pfcena;
}
/**
--
2.31.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Intel-wired-lan] [PATCH net v1] ice: Fix DSCP PFC TLV creation
2023-01-25 16:01 Karen Ostrowska
@ 2023-01-25 23:36 ` Tony Nguyen
2023-01-27 17:57 ` Ertman, David M
2023-01-26 8:18 ` Paul Menzel
1 sibling, 1 reply; 7+ messages in thread
From: Tony Nguyen @ 2023-01-25 23:36 UTC (permalink / raw)
To: Karen Ostrowska, intel-wired-lan, michal.swiatkowski
[-- Attachment #1.1: Type: text/plain, Size: 1492 bytes --]
On 1/25/2023 8:01 AM, Karen Ostrowska wrote:
> From: Dave Ertman<david.m.ertman@intel.com>
>
> When creating the TLV to send to the FW for configuring DSCP
> mode PFC, the PFCENABLE field was being masked with a 4 bit
> mask (0xF), but this is an 8 bit bitmask for enabled classes
> for PFC. This means that traffic classes 4-7 could not be
> enabled for PFC.
>
> Remove the mask completely, as it is not necessary, as we are
> assigning 8bits to an 8 bit field.
>
> Fixes: 2a87bd73e50d("ice: Add DSCP support")
Fixes tag: Fixes: 2a87bd73e50d("ice: Add DSCP support")
Has these problem(s):
- missing space between the SHA1 and the subject
> Signed-off-by: Dave Ertman<david.m.ertman@intel.com>
> Signed-off-by: Karen Ostrowska<karen.ostrowska@intel.com>
> ---
> drivers/net/ethernet/intel/ice/ice_dcb.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/intel/ice/ice_dcb.c b/drivers/net/ethernet/intel/ice/ice_dcb.c
> index 6be02f9b0b8c..789b99963910 100644
> --- a/drivers/net/ethernet/intel/ice/ice_dcb.c
> +++ b/drivers/net/ethernet/intel/ice/ice_dcb.c
> @@ -1372,7 +1372,7 @@ ice_add_dscp_pfc_tlv(struct ice_lldp_org_tlv *tlv, struct ice_dcbx_cfg *dcbcfg)
> tlv->ouisubtype = htonl(ouisubtype);
>
> buf[0] = dcbcfg->pfc.pfccap & 0xF;
> - buf[1] = dcbcfg->pfc.pfcena & 0xF;
> + buf[1] = dcbcfg->pfc.pfcena;
Also, I don't believe I saw a response to Michal's question:
What about pfc.pfccap? Shouldn't we also remove the mask?
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-wired-lan] [PATCH net v1] ice: Fix DSCP PFC TLV creation
2023-01-25 16:01 Karen Ostrowska
2023-01-25 23:36 ` Tony Nguyen
@ 2023-01-26 8:18 ` Paul Menzel
1 sibling, 0 replies; 7+ messages in thread
From: Paul Menzel @ 2023-01-26 8:18 UTC (permalink / raw)
To: Karen Ostrowska; +Cc: intel-wired-lan
Dear Karen,
Thank you for the patch.
Am 25.01.23 um 17:01 schrieb Karen Ostrowska:
> From: Dave Ertman <david.m.ertman@intel.com>
>
> When creating the TLV to send to the FW for configuring DSCP
> mode PFC, the PFCENABLE field was being masked with a 4 bit
> mask (0xF), but this is an 8 bit bitmask for enabled classes
> for PFC. This means that traffic classes 4-7 could not be
> enabled for PFC.
>
> Remove the mask completely, as it is not necessary, as we are
> assigning 8bits to an 8 bit field.
Please reflow the text to use the full 75 characters of allowed text width.
Please add a space in “8 bits”.
> Fixes: 2a87bd73e50d("ice: Add DSCP support")
Please add a space after the commit hash before the (.
> Signed-off-by: Dave Ertman <david.m.ertman@intel.com>
> Signed-off-by: Karen Ostrowska <karen.ostrowska@intel.com>
> ---
> drivers/net/ethernet/intel/ice/ice_dcb.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/intel/ice/ice_dcb.c b/drivers/net/ethernet/intel/ice/ice_dcb.c
> index 6be02f9b0b8c..789b99963910 100644
> --- a/drivers/net/ethernet/intel/ice/ice_dcb.c
> +++ b/drivers/net/ethernet/intel/ice/ice_dcb.c
> @@ -1372,7 +1372,7 @@ ice_add_dscp_pfc_tlv(struct ice_lldp_org_tlv *tlv, struct ice_dcbx_cfg *dcbcfg)
> tlv->ouisubtype = htonl(ouisubtype);
>
> buf[0] = dcbcfg->pfc.pfccap & 0xF;
> - buf[1] = dcbcfg->pfc.pfcena & 0xF;
> + buf[1] = dcbcfg->pfc.pfcena;
> }
>
> /**
Kind regards,
Paul
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^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-wired-lan] [PATCH net v1] ice: Fix DSCP PFC TLV creation
@ 2023-01-27 13:24 Karen Ostrowska
2023-01-31 21:40 ` Tony Nguyen
2023-03-06 11:21 ` G, GurucharanX
0 siblings, 2 replies; 7+ messages in thread
From: Karen Ostrowska @ 2023-01-27 13:24 UTC (permalink / raw)
To: intel-wired-lan; +Cc: Karen Ostrowska
From: Dave Ertman <david.m.ertman@intel.com>
When creating the TLV to send to the FW for configuring DSCP mode PFC,the
PFCENABLE field was being masked with a 4 bit mask (0xF), but this is an 8
bit bitmask for enabled classes for PFC. This means that traffic classes
4-7 could not be enabled for PFC.
Remove the mask completely, as it is not necessary, as we are assigning 8
bits to an 8 bit field.
Fixes: 2a87bd73e50d ("ice: Add DSCP support")
Signed-off-by: Dave Ertman <david.m.ertman@intel.com>
Signed-off-by: Karen Ostrowska <karen.ostrowska@intel.com>
---
drivers/net/ethernet/intel/ice/ice_dcb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_dcb.c b/drivers/net/ethernet/intel/ice/ice_dcb.c
index 6be02f9b0b8c..789b99963910 100644
--- a/drivers/net/ethernet/intel/ice/ice_dcb.c
+++ b/drivers/net/ethernet/intel/ice/ice_dcb.c
@@ -1372,7 +1372,7 @@ ice_add_dscp_pfc_tlv(struct ice_lldp_org_tlv *tlv, struct ice_dcbx_cfg *dcbcfg)
tlv->ouisubtype = htonl(ouisubtype);
buf[0] = dcbcfg->pfc.pfccap & 0xF;
- buf[1] = dcbcfg->pfc.pfcena & 0xF;
+ buf[1] = dcbcfg->pfc.pfcena;
}
/**
--
2.31.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Intel-wired-lan] [PATCH net v1] ice: Fix DSCP PFC TLV creation
2023-01-25 23:36 ` Tony Nguyen
@ 2023-01-27 17:57 ` Ertman, David M
0 siblings, 0 replies; 7+ messages in thread
From: Ertman, David M @ 2023-01-27 17:57 UTC (permalink / raw)
To: Nguyen, Anthony L, Ostrowska, Karen,
intel-wired-lan@lists.osuosl.org,
michal.swiatkowski@linux.intel.com
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of Tony Nguyen
> Sent: Wednesday, January 25, 2023 3:36 PM
> To: Ostrowska, Karen <karen.ostrowska@intel.com>; intel-wired-lan@lists.osuosl.org; michal.swiatkowski@linux.intel.com
> Subject: Re: [Intel-wired-lan] [PATCH net v1] ice: Fix DSCP PFC TLV creation
...
> > buf[0] = dcbcfg->pfc.pfccap & 0xF;
> > - buf[1] = dcbcfg->pfc.pfcena & 0xF;
> > + buf[1] = dcbcfg->pfc.pfcena;
> Also, I don't believe I saw a response to Michal's question:
> What about pfc.pfccap? Shouldn't we also remove the mask?
pfc.pfccap is not a bitmap like pfc.pfcena is. pfc.pfccap is a count value 0-8, so any
value in the upper 4 bits is not desirable.
DaveE
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-wired-lan] [PATCH net v1] ice: Fix DSCP PFC TLV creation
2023-01-27 13:24 [Intel-wired-lan] [PATCH net v1] ice: Fix DSCP PFC TLV creation Karen Ostrowska
@ 2023-01-31 21:40 ` Tony Nguyen
2023-03-06 11:21 ` G, GurucharanX
1 sibling, 0 replies; 7+ messages in thread
From: Tony Nguyen @ 2023-01-31 21:40 UTC (permalink / raw)
To: Karen Ostrowska, intel-wired-lan
On 1/27/2023 5:24 AM, Karen Ostrowska wrote:
> From: Dave Ertman <david.m.ertman@intel.com>
>
> When creating the TLV to send to the FW for configuring DSCP mode PFC,the
> PFCENABLE field was being masked with a 4 bit mask (0xF), but this is an 8
> bit bitmask for enabled classes for PFC. This means that traffic classes
> 4-7 could not be enabled for PFC.
>
> Remove the mask completely, as it is not necessary, as we are assigning 8
> bits to an 8 bit field.
>
> Fixes: 2a87bd73e50d ("ice: Add DSCP support")
> Signed-off-by: Dave Ertman <david.m.ertman@intel.com>
> Signed-off-by: Karen Ostrowska <karen.ostrowska@intel.com>
> ---
Applied, however, this should be a v2 (with changelog)
> drivers/net/ethernet/intel/ice/ice_dcb.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/intel/ice/ice_dcb.c b/drivers/net/ethernet/intel/ice/ice_dcb.c
> index 6be02f9b0b8c..789b99963910 100644
> --- a/drivers/net/ethernet/intel/ice/ice_dcb.c
> +++ b/drivers/net/ethernet/intel/ice/ice_dcb.c
> @@ -1372,7 +1372,7 @@ ice_add_dscp_pfc_tlv(struct ice_lldp_org_tlv *tlv, struct ice_dcbx_cfg *dcbcfg)
> tlv->ouisubtype = htonl(ouisubtype);
>
> buf[0] = dcbcfg->pfc.pfccap & 0xF;
> - buf[1] = dcbcfg->pfc.pfcena & 0xF;
> + buf[1] = dcbcfg->pfc.pfcena;
> }
>
> /**
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-wired-lan] [PATCH net v1] ice: Fix DSCP PFC TLV creation
2023-01-27 13:24 [Intel-wired-lan] [PATCH net v1] ice: Fix DSCP PFC TLV creation Karen Ostrowska
2023-01-31 21:40 ` Tony Nguyen
@ 2023-03-06 11:21 ` G, GurucharanX
1 sibling, 0 replies; 7+ messages in thread
From: G, GurucharanX @ 2023-03-06 11:21 UTC (permalink / raw)
To: Ostrowska, Karen, intel-wired-lan@lists.osuosl.org; +Cc: Ostrowska, Karen
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
> Karen Ostrowska
> Sent: Friday, January 27, 2023 6:54 PM
> To: intel-wired-lan@lists.osuosl.org
> Cc: Ostrowska, Karen <karen.ostrowska@intel.com>
> Subject: [Intel-wired-lan] [PATCH net v1] ice: Fix DSCP PFC TLV creation
>
> From: Dave Ertman <david.m.ertman@intel.com>
>
> When creating the TLV to send to the FW for configuring DSCP mode PFC,the
> PFCENABLE field was being masked with a 4 bit mask (0xF), but this is an 8 bit
> bitmask for enabled classes for PFC. This means that traffic classes
> 4-7 could not be enabled for PFC.
>
> Remove the mask completely, as it is not necessary, as we are assigning 8 bits
> to an 8 bit field.
>
> Fixes: 2a87bd73e50d ("ice: Add DSCP support")
> Signed-off-by: Dave Ertman <david.m.ertman@intel.com>
> Signed-off-by: Karen Ostrowska <karen.ostrowska@intel.com>
> ---
> drivers/net/ethernet/intel/ice/ice_dcb.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Tested-by: Gurucharan G <gurucharanx.g@intel.com> (A Contingent worker at Intel)
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2023-01-27 13:24 [Intel-wired-lan] [PATCH net v1] ice: Fix DSCP PFC TLV creation Karen Ostrowska
2023-01-31 21:40 ` Tony Nguyen
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