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From: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
To: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>,
	 intel-xe@lists.freedesktop.org
Subject: Re: [Intel-xe] [RFC v2 4/6] drm/xe/xe2: Updates on XY_CTRL_SURF_COPY_BLT
Date: Fri, 24 Nov 2023 12:11:22 +0100	[thread overview]
Message-ID: <07b47a67234eeef5208214c9ea60272771aaaa5c.camel@linux.intel.com> (raw)
In-Reply-To: <20231121100906.3587649-5-himal.prasad.ghimiray@intel.com>

On Tue, 2023-11-21 at 15:39 +0530, Himal Prasad Ghimiray wrote:
> - The XY_CTRL_SURF_COPY_BLT instruction operationg on ccs data
> expects
> size in pages of main memory for which CCS data should be copied.
> - The bitfield representing copy size in XY_CTRL_SURF_COPY_BLT has
> shifted one bit higher in the instruction.
> 
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Signed-off-by: Himal Prasad Ghimiray
> <himal.prasad.ghimiray@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gpu_commands.h |  1 +
>  drivers/gpu/drm/xe/xe_migrate.c           | 23 +++++++++++++++++----
> --
>  2 files changed, 18 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
> b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
> index 7f74592f99ce..47459841aa69 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
> @@ -13,6 +13,7 @@
>  #define   DST_ACCESS_TYPE_SHIFT                20
>  #define   CCS_SIZE_MASK                        0x3FF
>  #define   CCS_SIZE_SHIFT               8
> +#define   XE2_CCS_SIZE_SHIFT           9
>  #define   XY_CTRL_SURF_MOCS_MASK       GENMASK(31, 26)
>  #define   XE2_XY_CTRL_SURF_MOCS_INDEX_MASK     GENMASK(31, 28)
>  #define   NUM_CCS_BYTES_PER_BLOCK      256
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c
> b/drivers/gpu/drm/xe/xe_migrate.c
> index ed2f3f5109f3..06706fad67aa 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -523,21 +523,31 @@ static void emit_copy_ccs(struct xe_gt *gt,
> struct xe_bb *bb,
>         struct xe_device *xe = gt_to_xe(gt);
>         u32 *cs = bb->cs + bb->len;
>         u32 num_ccs_blks;
> +       u32 num_ccs_pages;
> +       u32 ccs_copy_size;
>         u32 mocs;
>  
> -       num_ccs_blks = DIV_ROUND_UP(xe_device_ccs_bytes(gt_to_xe(gt),
> size),
> -                                   NUM_CCS_BYTES_PER_BLOCK);
> -       xe_gt_assert(gt, num_ccs_blks <= NUM_CCS_BLKS_PER_XFER);
> +       if (GRAPHICS_VERx100(xe) >= 2000) {
> +               num_ccs_pages =
> DIV_ROUND_UP(xe_device_ccs_bytes(gt_to_xe(gt), size),
> +                                            XE_PAGE_SIZE);
> +               xe_gt_assert(gt, num_ccs_pages <= 1024);
>  
> -       if (GRAPHICS_VERx100(xe) >= 2000)
> +               ccs_copy_size = ((num_ccs_pages - 1) & CCS_SIZE_MASK)
> << XE2_CCS_SIZE_SHIFT;
>                 mocs = FIELD_PREP(XE2_XY_CTRL_SURF_MOCS_INDEX_MASK,
> gt->mocs.uc_index);
> -       else
> +
> +       } else {
> +               num_ccs_blks =
> DIV_ROUND_UP(xe_device_ccs_bytes(gt_to_xe(gt), size),
> +                                           NUM_CCS_BYTES_PER_BLOCK);
> +               xe_gt_assert(gt, num_ccs_blks <=
> NUM_CCS_BLKS_PER_XFER);
> +
> +               ccs_copy_size = ((num_ccs_blks - 1) & CCS_SIZE_MASK)
> << CCS_SIZE_SHIFT;
>                 mocs = FIELD_PREP(XY_CTRL_SURF_MOCS_MASK, gt-
> >mocs.uc_index);
> +       }
>  
>         *cs++ = XY_CTRL_SURF_COPY_BLT |
>                 (src_is_indirect ? 0x0 : 0x1) <<
> SRC_ACCESS_TYPE_SHIFT |
>                 (dst_is_indirect ? 0x0 : 0x1) <<
> DST_ACCESS_TYPE_SHIFT |
> -               ((num_ccs_blks - 1) & CCS_SIZE_MASK) <<
> CCS_SIZE_SHIFT;
> +               ccs_copy_size;
>         *cs++ = lower_32_bits(src_ofs);
>         *cs++ = upper_32_bits(src_ofs) | mocs;
>         *cs++ = lower_32_bits(dst_ofs);
> @@ -992,6 +1002,7 @@ struct dma_fence *xe_migrate_clear(struct
> xe_migrate *m,
>  
>                 emit_clear(gt, bb, clear_L0_ofs, clear_L0,
> XE_PAGE_SIZE,
>                            clear_vram);
> +

Unrelated change. Please remove, Otherwise LGTM.
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>


>                 if (xe_device_has_flat_ccs(xe) && clear_vram) {
>                         emit_copy_ccs(gt, bb, clear_L0_ofs, true,
>                                       m->cleared_vram_ofs, false,
> clear_L0);


  reply	other threads:[~2023-11-24 11:11 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-21 10:09 [Intel-xe] [RFC v2 0/6] Enable compression handling on LNL Himal Prasad Ghimiray
2023-11-21 10:09 ` [Intel-xe] [RFC v2 1/6] drm/xe/xe2: Support flat ccs Himal Prasad Ghimiray
2023-11-23 16:28   ` Matthew Auld
2023-11-27  3:04     ` Ghimiray, Himal Prasad
2023-11-24 11:02   ` Thomas Hellström
2023-11-27  3:05     ` Ghimiray, Himal Prasad
2023-11-21 10:09 ` [Intel-xe] [RFC v2 2/6] drm/xe/xe2: Determine bios enablement for flat ccs on igfx Himal Prasad Ghimiray
2023-11-23 16:37   ` Matthew Auld
2023-11-23 17:01     ` Matthew Auld
2023-11-27  3:11       ` Ghimiray, Himal Prasad
2023-11-24 11:05   ` Thomas Hellström
2023-11-27  3:12     ` Ghimiray, Himal Prasad
2023-11-21 10:09 ` [Intel-xe] [RFC v2 3/6] drm/xe/xe2: Allocate extra pages for ccs during bo create Himal Prasad Ghimiray
2023-11-24 11:09   ` Thomas Hellström
2023-11-27  3:19     ` Ghimiray, Himal Prasad
2023-11-27  9:41       ` Thomas Hellström
2023-11-29  4:53         ` Ghimiray, Himal Prasad
2023-11-21 10:09 ` [Intel-xe] [RFC v2 4/6] drm/xe/xe2: Updates on XY_CTRL_SURF_COPY_BLT Himal Prasad Ghimiray
2023-11-24 11:11   ` Thomas Hellström [this message]
2023-11-27  3:21     ` Ghimiray, Himal Prasad
2023-11-21 10:09 ` [Intel-xe] [RFC v2 5/6] drm/xe/xe_migrate.c: Use NULL 1G PTE mapped at 255GiB VA for ccs clear Himal Prasad Ghimiray
2023-11-24 11:19   ` Thomas Hellström
2023-11-27  3:23     ` Ghimiray, Himal Prasad
2023-11-21 10:09 ` [Intel-xe] [RFC v2 6/6] drm/xe/xe2: Handle flat ccs move for igfx Himal Prasad Ghimiray
2023-11-24 15:48   ` Thomas Hellström
2023-11-27  3:25     ` Ghimiray, Himal Prasad
2023-11-28 13:36 ` [Intel-xe] [RFC v2 0/6] Enable compression handling on LNL Thomas Hellström
2023-11-29  4:49   ` Ghimiray, Himal Prasad

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