* [PATCH] drm/i915/display: Skip unavailable power wells based on pipe mask
@ 2025-07-17 5:16 Chaitanya Kumar Borah
2025-07-17 5:39 ` ✗ CI.checkpatch: warning for " Patchwork
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: Chaitanya Kumar Borah @ 2025-07-17 5:16 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: gustavo.sousa, dnyaneshwar.bhadane, dibin.moolakadan.subrahmanian,
imre.deak
Some power wells are only relevant for certain display pipes. Add a check
to ensure we only allocate and initialize power wells whose associated
pipes are available on the platform.
This avoids unnecessary mapping of power wells, particularly when platforms
support a subset of pipes described in the power well descriptors.
Suggested-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
.../i915/display/intel_display_power_map.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 77268802b55e..ca73e4084354 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1748,6 +1748,16 @@ static void init_power_well_domains(const struct i915_power_well_instance *inst,
for_each_power_well_instance_in_desc_list((_descs)->list, (_descs)->count, \
(_desc), (_inst))
+static bool
+is_power_well_available(struct intel_display *display, const struct i915_power_well_desc *desc)
+{
+ if (desc->irq_pipe_mask &&
+ !(desc->irq_pipe_mask & DISPLAY_RUNTIME_INFO(display)->pipe_mask))
+ return false;
+
+ return true;
+}
+
static int
__set_power_wells(struct i915_power_domains *power_domains,
const struct i915_power_well_desc_list *power_well_descs,
@@ -1763,8 +1773,10 @@ __set_power_wells(struct i915_power_domains *power_domains,
int power_well_count = 0;
int plt_idx = 0;
- for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst)
- power_well_count++;
+ for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) {
+ if (is_power_well_available(display, desc))
+ power_well_count++;
+ }
power_domains->power_well_count = power_well_count;
power_domains->power_wells =
@@ -1778,6 +1790,9 @@ __set_power_wells(struct i915_power_domains *power_domains,
struct i915_power_well *pw = &power_domains->power_wells[plt_idx];
enum i915_power_well_id id = inst->id;
+ if (!is_power_well_available(display, desc))
+ continue;
+
pw->desc = desc;
drm_WARN_ON(display->drm,
overflows_type(inst - desc->instances->list, pw->instance_idx));
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* ✗ CI.checkpatch: warning for drm/i915/display: Skip unavailable power wells based on pipe mask 2025-07-17 5:16 [PATCH] drm/i915/display: Skip unavailable power wells based on pipe mask Chaitanya Kumar Borah @ 2025-07-17 5:39 ` Patchwork 2025-07-17 5:41 ` ✓ CI.KUnit: success " Patchwork ` (3 subsequent siblings) 4 siblings, 0 replies; 14+ messages in thread From: Patchwork @ 2025-07-17 5:39 UTC (permalink / raw) To: Chaitanya Kumar Borah; +Cc: intel-xe == Series Details == Series: drm/i915/display: Skip unavailable power wells based on pipe mask URL : https://patchwork.freedesktop.org/series/151737/ State : warning == Summary == + KERNEL=/kernel + git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt Cloning into 'mt'... warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/ + git -C mt rev-list -n1 origin/master 43254c2aa575037fc031c7ac21b0d031c700b2bf + cd /kernel + git config --global --add safe.directory /kernel + git log -n1 commit 4822f0541331cd33099d03ef1f3c6dd711cf548c Author: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Date: Thu Jul 17 10:46:03 2025 +0530 drm/i915/display: Skip unavailable power wells based on pipe mask Some power wells are only relevant for certain display pipes. Add a check to ensure we only allocate and initialize power wells whose associated pipes are available on the platform. This avoids unnecessary mapping of power wells, particularly when platforms support a subset of pipes described in the power well descriptors. Suggested-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> + /mt/dim checkpatch e7058b7a607f5fdfd7bc4586644756d7ef002331 drm-intel 4822f0541331 drm/i915/display: Skip unavailable power wells based on pipe mask -:22: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (16, 0) #22: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1748: for_each_power_well_instance_in_desc_list((_descs)->list, (_descs)->count, \ [...] +static bool total: 0 errors, 1 warnings, 0 checks, 37 lines checked ^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ CI.KUnit: success for drm/i915/display: Skip unavailable power wells based on pipe mask 2025-07-17 5:16 [PATCH] drm/i915/display: Skip unavailable power wells based on pipe mask Chaitanya Kumar Borah 2025-07-17 5:39 ` ✗ CI.checkpatch: warning for " Patchwork @ 2025-07-17 5:41 ` Patchwork 2025-07-17 7:09 ` ✓ Xe.CI.BAT: " Patchwork ` (2 subsequent siblings) 4 siblings, 0 replies; 14+ messages in thread From: Patchwork @ 2025-07-17 5:41 UTC (permalink / raw) To: Chaitanya Kumar Borah; +Cc: intel-xe == Series Details == Series: drm/i915/display: Skip unavailable power wells based on pipe mask URL : https://patchwork.freedesktop.org/series/151737/ State : success == Summary == + trap cleanup EXIT + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig [05:39:39] Configuring KUnit Kernel ... Generating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [05:39:43] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25 [05:40:17] Starting KUnit Kernel (1/1)... [05:40:17] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [05:40:17] ================== guc_buf (11 subtests) =================== [05:40:17] [PASSED] test_smallest [05:40:17] [PASSED] test_largest [05:40:17] [PASSED] test_granular [05:40:17] [PASSED] test_unique [05:40:17] [PASSED] test_overlap [05:40:17] [PASSED] test_reusable [05:40:17] [PASSED] test_too_big [05:40:17] [PASSED] test_flush [05:40:17] [PASSED] test_lookup [05:40:17] [PASSED] test_data [05:40:17] [PASSED] test_class [05:40:17] ===================== [PASSED] guc_buf ===================== [05:40:17] =================== guc_dbm (7 subtests) =================== [05:40:17] [PASSED] test_empty [05:40:17] [PASSED] test_default [05:40:17] ======================== test_size ======================== [05:40:17] [PASSED] 4 [05:40:17] [PASSED] 8 [05:40:17] [PASSED] 32 [05:40:17] [PASSED] 256 [05:40:17] ==================== [PASSED] test_size ==================== [05:40:17] ======================= test_reuse ======================== [05:40:17] [PASSED] 4 [05:40:17] [PASSED] 8 [05:40:17] [PASSED] 32 [05:40:17] [PASSED] 256 [05:40:17] =================== [PASSED] test_reuse ==================== [05:40:17] =================== test_range_overlap ==================== [05:40:17] [PASSED] 4 [05:40:17] [PASSED] 8 [05:40:17] [PASSED] 32 [05:40:17] [PASSED] 256 [05:40:17] =============== [PASSED] test_range_overlap ================ [05:40:17] =================== test_range_compact ==================== [05:40:17] [PASSED] 4 [05:40:17] [PASSED] 8 [05:40:17] [PASSED] 32 [05:40:17] [PASSED] 256 [05:40:17] =============== [PASSED] test_range_compact ================ [05:40:17] ==================== test_range_spare ===================== [05:40:17] [PASSED] 4 [05:40:17] [PASSED] 8 [05:40:17] [PASSED] 32 [05:40:17] [PASSED] 256 [05:40:17] ================ [PASSED] test_range_spare ================= [05:40:17] ===================== [PASSED] guc_dbm ===================== [05:40:17] =================== guc_idm (6 subtests) =================== [05:40:17] [PASSED] bad_init [05:40:17] [PASSED] no_init [05:40:17] [PASSED] init_fini [05:40:17] [PASSED] check_used [05:40:17] [PASSED] check_quota [05:40:17] [PASSED] check_all [05:40:17] ===================== [PASSED] guc_idm ===================== [05:40:17] ================== no_relay (3 subtests) =================== [05:40:17] [PASSED] xe_drops_guc2pf_if_not_ready [05:40:17] [PASSED] xe_drops_guc2vf_if_not_ready [05:40:17] [PASSED] xe_rejects_send_if_not_ready [05:40:17] ==================== [PASSED] no_relay ===================== [05:40:17] ================== pf_relay (14 subtests) ================== [05:40:17] [PASSED] pf_rejects_guc2pf_too_short [05:40:17] [PASSED] pf_rejects_guc2pf_too_long [05:40:17] [PASSED] pf_rejects_guc2pf_no_payload [05:40:17] [PASSED] pf_fails_no_payload [05:40:17] [PASSED] pf_fails_bad_origin [05:40:17] [PASSED] pf_fails_bad_type [05:40:17] [PASSED] pf_txn_reports_error [05:40:17] [PASSED] pf_txn_sends_pf2guc [05:40:17] [PASSED] pf_sends_pf2guc [05:40:17] [SKIPPED] pf_loopback_nop [05:40:17] [SKIPPED] pf_loopback_echo [05:40:17] [SKIPPED] pf_loopback_fail [05:40:17] [SKIPPED] pf_loopback_busy [05:40:17] [SKIPPED] pf_loopback_retry [05:40:17] ==================== [PASSED] pf_relay ===================== [05:40:17] ================== vf_relay (3 subtests) =================== [05:40:17] [PASSED] vf_rejects_guc2vf_too_short [05:40:17] [PASSED] vf_rejects_guc2vf_too_long [05:40:17] [PASSED] vf_rejects_guc2vf_no_payload [05:40:17] ==================== [PASSED] vf_relay ===================== [05:40:17] ===================== lmtt (1 subtest) ===================== [05:40:17] ======================== test_ops ========================= [05:40:17] [PASSED] 2-level [05:40:17] [PASSED] multi-level [05:40:17] ==================== [PASSED] test_ops ===================== [05:40:17] ====================== [PASSED] lmtt ======================= [05:40:17] ================= pf_service (11 subtests) ================= [05:40:17] [PASSED] pf_negotiate_any [05:40:17] [PASSED] pf_negotiate_base_match [05:40:17] [PASSED] pf_negotiate_base_newer [05:40:17] [PASSED] pf_negotiate_base_next [05:40:17] [SKIPPED] pf_negotiate_base_older [05:40:17] [PASSED] pf_negotiate_base_prev [05:40:17] [PASSED] pf_negotiate_latest_match [05:40:17] [PASSED] pf_negotiate_latest_newer [05:40:17] [PASSED] pf_negotiate_latest_next [05:40:17] [SKIPPED] pf_negotiate_latest_older [05:40:17] [SKIPPED] pf_negotiate_latest_prev [05:40:17] =================== [PASSED] pf_service ==================== [05:40:17] =================== xe_mocs (2 subtests) =================== [05:40:17] ================ xe_live_mocs_kernel_kunit ================ [05:40:17] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============ [05:40:17] ================ xe_live_mocs_reset_kunit ================= [05:40:17] ============ [SKIPPED] xe_live_mocs_reset_kunit ============ [05:40:17] ==================== [SKIPPED] xe_mocs ===================== [05:40:17] ================= xe_migrate (2 subtests) ================== [05:40:17] ================= xe_migrate_sanity_kunit ================= [05:40:17] ============ [SKIPPED] xe_migrate_sanity_kunit ============= [05:40:17] ================== xe_validate_ccs_kunit ================== [05:40:17] ============= [SKIPPED] xe_validate_ccs_kunit ============== [05:40:17] =================== [SKIPPED] xe_migrate =================== [05:40:17] ================== xe_dma_buf (1 subtest) ================== [05:40:17] ==================== xe_dma_buf_kunit ===================== [05:40:17] ================ [SKIPPED] xe_dma_buf_kunit ================ [05:40:17] =================== [SKIPPED] xe_dma_buf =================== [05:40:17] ================= xe_bo_shrink (1 subtest) ================= [05:40:17] =================== xe_bo_shrink_kunit ==================== [05:40:17] =============== [SKIPPED] xe_bo_shrink_kunit =============== [05:40:17] ================== [SKIPPED] xe_bo_shrink ================== [05:40:17] ==================== xe_bo (2 subtests) ==================== [05:40:17] ================== xe_ccs_migrate_kunit =================== [05:40:17] ============== [SKIPPED] xe_ccs_migrate_kunit ============== [05:40:17] ==================== xe_bo_evict_kunit ==================== [05:40:17] =============== [SKIPPED] xe_bo_evict_kunit ================ [05:40:17] ===================== [SKIPPED] xe_bo ====================== [05:40:17] ==================== args (11 subtests) ==================== [05:40:17] [PASSED] count_args_test [05:40:17] [PASSED] call_args_example [05:40:17] [PASSED] call_args_test [05:40:17] [PASSED] drop_first_arg_example [05:40:17] [PASSED] drop_first_arg_test [05:40:17] [PASSED] first_arg_example [05:40:17] [PASSED] first_arg_test [05:40:17] [PASSED] last_arg_example [05:40:17] [PASSED] last_arg_test [05:40:17] [PASSED] pick_arg_example [05:40:17] [PASSED] sep_comma_example [05:40:17] ====================== [PASSED] args ======================= [05:40:17] =================== xe_pci (3 subtests) ==================== [05:40:17] ==================== check_graphics_ip ==================== [05:40:17] [PASSED] 12.70 Xe_LPG [05:40:17] [PASSED] 12.71 Xe_LPG [05:40:17] [PASSED] 12.74 Xe_LPG+ [05:40:17] [PASSED] 20.01 Xe2_HPG [05:40:17] [PASSED] 20.02 Xe2_HPG [05:40:17] [PASSED] 20.04 Xe2_LPG [05:40:17] [PASSED] 30.00 Xe3_LPG [05:40:17] [PASSED] 30.01 Xe3_LPG [05:40:17] [PASSED] 30.03 Xe3_LPG [05:40:17] ================ [PASSED] check_graphics_ip ================ [05:40:17] ===================== check_media_ip ====================== [05:40:17] [PASSED] 13.00 Xe_LPM+ [05:40:17] [PASSED] 13.01 Xe2_HPM [05:40:17] [PASSED] 20.00 Xe2_LPM [05:40:17] [PASSED] 30.00 Xe3_LPM [05:40:17] [PASSED] 30.02 Xe3_LPM [05:40:17] ================= [PASSED] check_media_ip ================== [05:40:17] ================= check_platform_gt_count ================= [05:40:17] [PASSED] 0x9A60 (TIGERLAKE) [05:40:17] [PASSED] 0x9A68 (TIGERLAKE) [05:40:17] [PASSED] 0x9A70 (TIGERLAKE) [05:40:17] [PASSED] 0x9A40 (TIGERLAKE) [05:40:17] [PASSED] 0x9A49 (TIGERLAKE) [05:40:17] [PASSED] 0x9A59 (TIGERLAKE) [05:40:17] [PASSED] 0x9A78 (TIGERLAKE) [05:40:17] [PASSED] 0x9AC0 (TIGERLAKE) [05:40:17] [PASSED] 0x9AC9 (TIGERLAKE) [05:40:17] [PASSED] 0x9AD9 (TIGERLAKE) [05:40:17] [PASSED] 0x9AF8 (TIGERLAKE) [05:40:17] [PASSED] 0x4C80 (ROCKETLAKE) [05:40:17] [PASSED] 0x4C8A (ROCKETLAKE) [05:40:17] [PASSED] 0x4C8B (ROCKETLAKE) [05:40:17] [PASSED] 0x4C8C (ROCKETLAKE) [05:40:17] [PASSED] 0x4C90 (ROCKETLAKE) [05:40:17] [PASSED] 0x4C9A (ROCKETLAKE) [05:40:17] [PASSED] 0x4680 (ALDERLAKE_S) [05:40:17] [PASSED] 0x4682 (ALDERLAKE_S) [05:40:17] [PASSED] 0x4688 (ALDERLAKE_S) [05:40:17] [PASSED] 0x468A (ALDERLAKE_S) [05:40:17] [PASSED] 0x468B (ALDERLAKE_S) [05:40:17] [PASSED] 0x4690 (ALDERLAKE_S) [05:40:17] [PASSED] 0x4692 (ALDERLAKE_S) [05:40:17] [PASSED] 0x4693 (ALDERLAKE_S) [05:40:17] [PASSED] 0x46A0 (ALDERLAKE_P) [05:40:17] [PASSED] 0x46A1 (ALDERLAKE_P) [05:40:17] [PASSED] 0x46A2 (ALDERLAKE_P) [05:40:17] [PASSED] 0x46A3 (ALDERLAKE_P) [05:40:17] [PASSED] 0x46A6 (ALDERLAKE_P) [05:40:17] [PASSED] 0x46A8 (ALDERLAKE_P) [05:40:17] [PASSED] 0x46AA (ALDERLAKE_P) [05:40:17] [PASSED] 0x462A (ALDERLAKE_P) [05:40:17] [PASSED] 0x4626 (ALDERLAKE_P) [05:40:17] [PASSED] 0x4628 (ALDERLAKE_P) [05:40:17] [PASSED] 0x46B0 (ALDERLAKE_P) [05:40:17] [PASSED] 0x46B1 (ALDERLAKE_P) [05:40:17] [PASSED] 0x46B2 (ALDERLAKE_P) [05:40:17] [PASSED] 0x46B3 (ALDERLAKE_P) [05:40:17] [PASSED] 0x46C0 (ALDERLAKE_P) [05:40:17] [PASSED] 0x46C1 (ALDERLAKE_P) [05:40:17] [PASSED] 0x46C2 (ALDERLAKE_P) [05:40:17] [PASSED] 0x46C3 (ALDERLAKE_P) [05:40:17] [PASSED] 0x46D0 (ALDERLAKE_N) [05:40:17] [PASSED] 0x46D1 (ALDERLAKE_N) [05:40:17] [PASSED] 0x46D2 (ALDERLAKE_N) [05:40:17] [PASSED] 0x46D3 (ALDERLAKE_N) [05:40:17] [PASSED] 0x46D4 (ALDERLAKE_N) [05:40:17] [PASSED] 0xA721 (ALDERLAKE_P) [05:40:17] [PASSED] 0xA7A1 (ALDERLAKE_P) [05:40:17] [PASSED] 0xA7A9 (ALDERLAKE_P) [05:40:17] [PASSED] 0xA7AC (ALDERLAKE_P) [05:40:17] [PASSED] 0xA7AD (ALDERLAKE_P) [05:40:17] [PASSED] 0xA720 (ALDERLAKE_P) [05:40:17] [PASSED] 0xA7A0 (ALDERLAKE_P) [05:40:17] [PASSED] 0xA7A8 (ALDERLAKE_P) [05:40:17] [PASSED] 0xA7AA (ALDERLAKE_P) [05:40:17] [PASSED] 0xA7AB (ALDERLAKE_P) [05:40:17] [PASSED] 0xA780 (ALDERLAKE_S) [05:40:17] [PASSED] 0xA781 (ALDERLAKE_S) [05:40:17] [PASSED] 0xA782 (ALDERLAKE_S) [05:40:17] [PASSED] 0xA783 (ALDERLAKE_S) [05:40:17] [PASSED] 0xA788 (ALDERLAKE_S) [05:40:17] [PASSED] 0xA789 (ALDERLAKE_S) [05:40:17] [PASSED] 0xA78A (ALDERLAKE_S) [05:40:17] [PASSED] 0xA78B (ALDERLAKE_S) [05:40:17] [PASSED] 0x4905 (DG1) [05:40:17] [PASSED] 0x4906 (DG1) [05:40:17] [PASSED] 0x4907 (DG1) [05:40:17] [PASSED] 0x4908 (DG1) [05:40:17] [PASSED] 0x4909 (DG1) [05:40:17] [PASSED] 0x56C0 (DG2) [05:40:17] [PASSED] 0x56C2 (DG2) [05:40:17] [PASSED] 0x56C1 (DG2) [05:40:17] [PASSED] 0x7D51 (METEORLAKE) [05:40:17] [PASSED] 0x7DD1 (METEORLAKE) [05:40:17] [PASSED] 0x7D41 (METEORLAKE) [05:40:17] [PASSED] 0x7D67 (METEORLAKE) [05:40:17] [PASSED] 0xB640 (METEORLAKE) [05:40:17] [PASSED] 0x56A0 (DG2) [05:40:17] [PASSED] 0x56A1 (DG2) [05:40:17] [PASSED] 0x56A2 (DG2) [05:40:17] [PASSED] 0x56BE (DG2) [05:40:17] [PASSED] 0x56BF (DG2) [05:40:17] [PASSED] 0x5690 (DG2) [05:40:17] [PASSED] 0x5691 (DG2) [05:40:17] [PASSED] 0x5692 (DG2) [05:40:17] [PASSED] 0x56A5 (DG2) [05:40:17] [PASSED] 0x56A6 (DG2) [05:40:17] [PASSED] 0x56B0 (DG2) [05:40:17] [PASSED] 0x56B1 (DG2) [05:40:17] [PASSED] 0x56BA (DG2) [05:40:17] [PASSED] 0x56BB (DG2) [05:40:17] [PASSED] 0x56BC (DG2) [05:40:17] [PASSED] 0x56BD (DG2) [05:40:17] [PASSED] 0x5693 (DG2) [05:40:17] [PASSED] 0x5694 (DG2) [05:40:17] [PASSED] 0x5695 (DG2) [05:40:17] [PASSED] 0x56A3 (DG2) [05:40:17] [PASSED] 0x56A4 (DG2) [05:40:17] [PASSED] 0x56B2 (DG2) [05:40:17] [PASSED] 0x56B3 (DG2) [05:40:17] [PASSED] 0x5696 (DG2) [05:40:17] [PASSED] 0x5697 (DG2) [05:40:17] [PASSED] 0xB69 (PVC) [05:40:17] [PASSED] 0xB6E (PVC) [05:40:17] [PASSED] 0xBD4 (PVC) [05:40:17] [PASSED] 0xBD5 (PVC) [05:40:17] [PASSED] 0xBD6 (PVC) [05:40:17] [PASSED] 0xBD7 (PVC) [05:40:17] [PASSED] 0xBD8 (PVC) [05:40:17] [PASSED] 0xBD9 (PVC) [05:40:17] [PASSED] 0xBDA (PVC) [05:40:17] [PASSED] 0xBDB (PVC) [05:40:17] [PASSED] 0xBE0 (PVC) [05:40:17] [PASSED] 0xBE1 (PVC) [05:40:17] [PASSED] 0xBE5 (PVC) [05:40:17] [PASSED] 0x7D40 (METEORLAKE) [05:40:17] [PASSED] 0x7D45 (METEORLAKE) [05:40:17] [PASSED] 0x7D55 (METEORLAKE) [05:40:17] [PASSED] 0x7D60 (METEORLAKE) [05:40:17] [PASSED] 0x7DD5 (METEORLAKE) [05:40:17] [PASSED] 0x6420 (LUNARLAKE) [05:40:17] [PASSED] 0x64A0 (LUNARLAKE) [05:40:17] [PASSED] 0x64B0 (LUNARLAKE) [05:40:17] [PASSED] 0xE202 (BATTLEMAGE) [05:40:17] [PASSED] 0xE209 (BATTLEMAGE) [05:40:17] [PASSED] 0xE20B (BATTLEMAGE) [05:40:17] [PASSED] 0xE20C (BATTLEMAGE) [05:40:17] [PASSED] 0xE20D (BATTLEMAGE) [05:40:17] [PASSED] 0xE210 (BATTLEMAGE) [05:40:17] [PASSED] 0xE211 (BATTLEMAGE) [05:40:17] [PASSED] 0xE212 (BATTLEMAGE) [05:40:17] [PASSED] 0xE216 (BATTLEMAGE) [05:40:17] [PASSED] 0xE220 (BATTLEMAGE) [05:40:17] [PASSED] 0xE221 (BATTLEMAGE) [05:40:17] [PASSED] 0xE222 (BATTLEMAGE) [05:40:17] [PASSED] 0xE223 (BATTLEMAGE) [05:40:17] [PASSED] 0xB080 (PANTHERLAKE) [05:40:17] [PASSED] 0xB081 (PANTHERLAKE) [05:40:17] [PASSED] 0xB082 (PANTHERLAKE) [05:40:17] [PASSED] 0xB083 (PANTHERLAKE) [05:40:17] [PASSED] 0xB084 (PANTHERLAKE) [05:40:17] [PASSED] 0xB085 (PANTHERLAKE) [05:40:17] [PASSED] 0xB086 (PANTHERLAKE) [05:40:17] [PASSED] 0xB087 (PANTHERLAKE) [05:40:17] [PASSED] 0xB08F (PANTHERLAKE) [05:40:17] [PASSED] 0xB090 (PANTHERLAKE) [05:40:17] [PASSED] 0xB0A0 (PANTHERLAKE) [05:40:17] [PASSED] 0xB0B0 (PANTHERLAKE) [05:40:17] [PASSED] 0xFD80 (PANTHERLAKE) [05:40:17] [PASSED] 0xFD81 (PANTHERLAKE) [05:40:17] ============= [PASSED] check_platform_gt_count ============= [05:40:17] ===================== [PASSED] xe_pci ====================== [05:40:17] =================== xe_rtp (2 subtests) ==================== [05:40:17] =============== xe_rtp_process_to_sr_tests ================ [05:40:17] [PASSED] coalesce-same-reg [05:40:17] [PASSED] no-match-no-add [05:40:17] [PASSED] match-or [05:40:17] [PASSED] match-or-xfail [05:40:17] [PASSED] no-match-no-add-multiple-rules [05:40:17] [PASSED] two-regs-two-entries [05:40:17] [PASSED] clr-one-set-other [05:40:17] [PASSED] set-field [05:40:17] [PASSED] conflict-duplicate [05:40:17] [PASSED] conflict-not-disjoint [05:40:17] [PASSED] conflict-reg-type [05:40:17] =========== [PASSED] xe_rtp_process_to_sr_tests ============ [05:40:17] ================== xe_rtp_process_tests =================== [05:40:17] [PASSED] active1 [05:40:17] [PASSED] active2 [05:40:17] [PASSED] active-inactive [05:40:17] [PASSED] inactive-active [05:40:17] [PASSED] inactive-1st_or_active-inactive [05:40:17] [PASSED] inactive-2nd_or_active-inactive [05:40:17] [PASSED] inactive-last_or_active-inactive [05:40:17] [PASSED] inactive-no_or_active-inactive [05:40:17] ============== [PASSED] xe_rtp_process_tests =============== [05:40:17] ===================== [PASSED] xe_rtp ====================== [05:40:17] ==================== xe_wa (1 subtest) ===================== [05:40:17] ======================== xe_wa_gt ========================= [05:40:17] [PASSED] TIGERLAKE (B0) [05:40:17] [PASSED] DG1 (A0) [05:40:17] [PASSED] DG1 (B0) [05:40:17] [PASSED] ALDERLAKE_S (A0) [05:40:17] [PASSED] ALDERLAKE_S (B0) [05:40:17] [PASSED] ALDERLAKE_S (C0) [05:40:17] [PASSED] ALDERLAKE_S (D0) [05:40:17] [PASSED] ALDERLAKE_P (A0) [05:40:17] [PASSED] ALDERLAKE_P (B0) [05:40:17] [PASSED] ALDERLAKE_P (C0) [05:40:17] [PASSED] ALDERLAKE_S_RPLS (D0) [05:40:17] [PASSED] ALDERLAKE_P_RPLU (E0) [05:40:17] [PASSED] DG2_G10 (C0) [05:40:17] [PASSED] DG2_G11 (B1) [05:40:17] [PASSED] DG2_G12 (A1) [05:40:17] [PASSED] METEORLAKE (g:A0, m:A0) [05:40:17] [PASSED] METEORLAKE (g:A0, m:A0) [05:40:17] [PASSED] METEORLAKE (g:A0, m:A0) [05:40:17] [PASSED] LUNARLAKE (g:A0, m:A0) [05:40:17] [PASSED] LUNARLAKE (g:B0, m:A0) stty: 'standard input': Inappropriate ioctl for device [05:40:17] [PASSED] BATTLEMAGE (g:A0, m:A1) [05:40:17] ==================== [PASSED] xe_wa_gt ===================== [05:40:17] ====================== [PASSED] xe_wa ====================== [05:40:17] ============================================================ [05:40:17] Testing complete. Ran 297 tests: passed: 281, skipped: 16 [05:40:17] Elapsed time: 38.102s total, 4.244s configuring, 33.542s building, 0.308s running + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig [05:40:17] Configuring KUnit Kernel ... Regenerating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [05:40:19] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25 [05:40:44] Starting KUnit Kernel (1/1)... [05:40:44] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [05:40:45] == drm_test_atomic_get_connector_for_encoder (1 subtest) === [05:40:45] [PASSED] drm_test_drm_atomic_get_connector_for_encoder [05:40:45] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ==== [05:40:45] =========== drm_validate_clone_mode (2 subtests) =========== [05:40:45] ============== drm_test_check_in_clone_mode =============== [05:40:45] [PASSED] in_clone_mode [05:40:45] [PASSED] not_in_clone_mode [05:40:45] ========== [PASSED] drm_test_check_in_clone_mode =========== [05:40:45] =============== drm_test_check_valid_clones =============== [05:40:45] [PASSED] not_in_clone_mode [05:40:45] [PASSED] valid_clone [05:40:45] [PASSED] invalid_clone [05:40:45] =========== [PASSED] drm_test_check_valid_clones =========== [05:40:45] ============= [PASSED] drm_validate_clone_mode ============= [05:40:45] ============= drm_validate_modeset (1 subtest) ============= [05:40:45] [PASSED] drm_test_check_connector_changed_modeset [05:40:45] ============== [PASSED] drm_validate_modeset =============== [05:40:45] ====== drm_test_bridge_get_current_state (2 subtests) ====== [05:40:45] [PASSED] drm_test_drm_bridge_get_current_state_atomic [05:40:45] [PASSED] drm_test_drm_bridge_get_current_state_legacy [05:40:45] ======== [PASSED] drm_test_bridge_get_current_state ======== [05:40:45] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ====== [05:40:45] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic [05:40:45] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled [05:40:45] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy [05:40:45] ======== [PASSED] drm_test_bridge_helper_reset_crtc ======== [05:40:45] ============== drm_bridge_alloc (2 subtests) =============== [05:40:45] [PASSED] drm_test_drm_bridge_alloc_basic [05:40:45] [PASSED] drm_test_drm_bridge_alloc_get_put [05:40:45] ================ [PASSED] drm_bridge_alloc ================= [05:40:45] ================== drm_buddy (7 subtests) ================== [05:40:45] [PASSED] drm_test_buddy_alloc_limit [05:40:45] [PASSED] drm_test_buddy_alloc_optimistic [05:40:45] [PASSED] drm_test_buddy_alloc_pessimistic [05:40:45] [PASSED] drm_test_buddy_alloc_pathological [05:40:45] [PASSED] drm_test_buddy_alloc_contiguous [05:40:45] [PASSED] drm_test_buddy_alloc_clear [05:40:45] [PASSED] drm_test_buddy_alloc_range_bias [05:40:45] ==================== [PASSED] drm_buddy ==================== [05:40:45] ============= drm_cmdline_parser (40 subtests) ============= [05:40:45] [PASSED] drm_test_cmdline_force_d_only [05:40:45] [PASSED] drm_test_cmdline_force_D_only_dvi [05:40:45] [PASSED] drm_test_cmdline_force_D_only_hdmi [05:40:45] [PASSED] drm_test_cmdline_force_D_only_not_digital [05:40:45] [PASSED] drm_test_cmdline_force_e_only [05:40:45] [PASSED] drm_test_cmdline_res [05:40:45] [PASSED] drm_test_cmdline_res_vesa [05:40:45] [PASSED] drm_test_cmdline_res_vesa_rblank [05:40:45] [PASSED] drm_test_cmdline_res_rblank [05:40:45] [PASSED] drm_test_cmdline_res_bpp [05:40:45] [PASSED] drm_test_cmdline_res_refresh [05:40:45] [PASSED] drm_test_cmdline_res_bpp_refresh [05:40:45] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced [05:40:45] [PASSED] drm_test_cmdline_res_bpp_refresh_margins [05:40:45] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off [05:40:45] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on [05:40:45] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog [05:40:45] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital [05:40:45] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on [05:40:45] [PASSED] drm_test_cmdline_res_margins_force_on [05:40:45] [PASSED] drm_test_cmdline_res_vesa_margins [05:40:45] [PASSED] drm_test_cmdline_name [05:40:45] [PASSED] drm_test_cmdline_name_bpp [05:40:45] [PASSED] drm_test_cmdline_name_option [05:40:45] [PASSED] drm_test_cmdline_name_bpp_option [05:40:45] [PASSED] drm_test_cmdline_rotate_0 [05:40:45] [PASSED] drm_test_cmdline_rotate_90 [05:40:45] [PASSED] drm_test_cmdline_rotate_180 [05:40:45] [PASSED] drm_test_cmdline_rotate_270 [05:40:45] [PASSED] drm_test_cmdline_hmirror [05:40:45] [PASSED] drm_test_cmdline_vmirror [05:40:45] [PASSED] drm_test_cmdline_margin_options [05:40:45] [PASSED] drm_test_cmdline_multiple_options [05:40:45] [PASSED] drm_test_cmdline_bpp_extra_and_option [05:40:45] [PASSED] drm_test_cmdline_extra_and_option [05:40:45] [PASSED] drm_test_cmdline_freestanding_options [05:40:45] [PASSED] drm_test_cmdline_freestanding_force_e_and_options [05:40:45] [PASSED] drm_test_cmdline_panel_orientation [05:40:45] ================ drm_test_cmdline_invalid ================= [05:40:45] [PASSED] margin_only [05:40:45] [PASSED] interlace_only [05:40:45] [PASSED] res_missing_x [05:40:45] [PASSED] res_missing_y [05:40:45] [PASSED] res_bad_y [05:40:45] [PASSED] res_missing_y_bpp [05:40:45] [PASSED] res_bad_bpp [05:40:45] [PASSED] res_bad_refresh [05:40:45] [PASSED] res_bpp_refresh_force_on_off [05:40:45] [PASSED] res_invalid_mode [05:40:45] [PASSED] res_bpp_wrong_place_mode [05:40:45] [PASSED] name_bpp_refresh [05:40:45] [PASSED] name_refresh [05:40:45] [PASSED] name_refresh_wrong_mode [05:40:45] [PASSED] name_refresh_invalid_mode [05:40:45] [PASSED] rotate_multiple [05:40:45] [PASSED] rotate_invalid_val [05:40:45] [PASSED] rotate_truncated [05:40:45] [PASSED] invalid_option [05:40:45] [PASSED] invalid_tv_option [05:40:45] [PASSED] truncated_tv_option [05:40:45] ============ [PASSED] drm_test_cmdline_invalid ============= [05:40:45] =============== drm_test_cmdline_tv_options =============== [05:40:45] [PASSED] NTSC [05:40:45] [PASSED] NTSC_443 [05:40:45] [PASSED] NTSC_J [05:40:45] [PASSED] PAL [05:40:45] [PASSED] PAL_M [05:40:45] [PASSED] PAL_N [05:40:45] [PASSED] SECAM [05:40:45] [PASSED] MONO_525 [05:40:45] [PASSED] MONO_625 [05:40:45] =========== [PASSED] drm_test_cmdline_tv_options =========== [05:40:45] =============== [PASSED] drm_cmdline_parser ================ [05:40:45] ========== drmm_connector_hdmi_init (20 subtests) ========== [05:40:45] [PASSED] drm_test_connector_hdmi_init_valid [05:40:45] [PASSED] drm_test_connector_hdmi_init_bpc_8 [05:40:45] [PASSED] drm_test_connector_hdmi_init_bpc_10 [05:40:45] [PASSED] drm_test_connector_hdmi_init_bpc_12 [05:40:45] [PASSED] drm_test_connector_hdmi_init_bpc_invalid [05:40:45] [PASSED] drm_test_connector_hdmi_init_bpc_null [05:40:45] [PASSED] drm_test_connector_hdmi_init_formats_empty [05:40:45] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb [05:40:45] === drm_test_connector_hdmi_init_formats_yuv420_allowed === [05:40:45] [PASSED] supported_formats=0x9 yuv420_allowed=1 [05:40:45] [PASSED] supported_formats=0x9 yuv420_allowed=0 [05:40:45] [PASSED] supported_formats=0x3 yuv420_allowed=1 [05:40:45] [PASSED] supported_formats=0x3 yuv420_allowed=0 [05:40:45] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed === [05:40:45] [PASSED] drm_test_connector_hdmi_init_null_ddc [05:40:45] [PASSED] drm_test_connector_hdmi_init_null_product [05:40:45] [PASSED] drm_test_connector_hdmi_init_null_vendor [05:40:45] [PASSED] drm_test_connector_hdmi_init_product_length_exact [05:40:45] [PASSED] drm_test_connector_hdmi_init_product_length_too_long [05:40:45] [PASSED] drm_test_connector_hdmi_init_product_valid [05:40:45] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact [05:40:45] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long [05:40:45] [PASSED] drm_test_connector_hdmi_init_vendor_valid [05:40:45] ========= drm_test_connector_hdmi_init_type_valid ========= [05:40:45] [PASSED] HDMI-A [05:40:45] [PASSED] HDMI-B [05:40:45] ===== [PASSED] drm_test_connector_hdmi_init_type_valid ===== [05:40:45] ======== drm_test_connector_hdmi_init_type_invalid ======== [05:40:45] [PASSED] Unknown [05:40:45] [PASSED] VGA [05:40:45] [PASSED] DVI-I [05:40:45] [PASSED] DVI-D [05:40:45] [PASSED] DVI-A [05:40:45] [PASSED] Composite [05:40:45] [PASSED] SVIDEO [05:40:45] [PASSED] LVDS [05:40:45] [PASSED] Component [05:40:45] [PASSED] DIN [05:40:45] [PASSED] DP [05:40:45] [PASSED] TV [05:40:45] [PASSED] eDP [05:40:45] [PASSED] Virtual [05:40:45] [PASSED] DSI [05:40:45] [PASSED] DPI [05:40:45] [PASSED] Writeback [05:40:45] [PASSED] SPI [05:40:45] [PASSED] USB [05:40:45] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ==== [05:40:45] ============ [PASSED] drmm_connector_hdmi_init ============= [05:40:45] ============= drmm_connector_init (3 subtests) ============= [05:40:45] [PASSED] drm_test_drmm_connector_init [05:40:45] [PASSED] drm_test_drmm_connector_init_null_ddc [05:40:45] ========= drm_test_drmm_connector_init_type_valid ========= [05:40:45] [PASSED] Unknown [05:40:45] [PASSED] VGA [05:40:45] [PASSED] DVI-I [05:40:45] [PASSED] DVI-D [05:40:45] [PASSED] DVI-A [05:40:45] [PASSED] Composite [05:40:45] [PASSED] SVIDEO [05:40:45] [PASSED] LVDS [05:40:45] [PASSED] Component [05:40:45] [PASSED] DIN [05:40:45] [PASSED] DP [05:40:45] [PASSED] HDMI-A [05:40:45] [PASSED] HDMI-B [05:40:45] [PASSED] TV [05:40:45] [PASSED] eDP [05:40:45] [PASSED] Virtual [05:40:45] [PASSED] DSI [05:40:45] [PASSED] DPI [05:40:45] [PASSED] Writeback [05:40:45] [PASSED] SPI [05:40:45] [PASSED] USB [05:40:45] ===== [PASSED] drm_test_drmm_connector_init_type_valid ===== [05:40:45] =============== [PASSED] drmm_connector_init =============== [05:40:45] ========= drm_connector_dynamic_init (6 subtests) ========== [05:40:45] [PASSED] drm_test_drm_connector_dynamic_init [05:40:45] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc [05:40:45] [PASSED] drm_test_drm_connector_dynamic_init_not_added [05:40:45] [PASSED] drm_test_drm_connector_dynamic_init_properties [05:40:45] ===== drm_test_drm_connector_dynamic_init_type_valid ====== [05:40:45] [PASSED] Unknown [05:40:45] [PASSED] VGA [05:40:45] [PASSED] DVI-I [05:40:45] [PASSED] DVI-D [05:40:45] [PASSED] DVI-A [05:40:45] [PASSED] Composite [05:40:45] [PASSED] SVIDEO [05:40:45] [PASSED] LVDS [05:40:45] [PASSED] Component [05:40:45] [PASSED] DIN [05:40:45] [PASSED] DP [05:40:45] [PASSED] HDMI-A [05:40:45] [PASSED] HDMI-B [05:40:45] [PASSED] TV [05:40:45] [PASSED] eDP [05:40:45] [PASSED] Virtual [05:40:45] [PASSED] DSI [05:40:45] [PASSED] DPI [05:40:45] [PASSED] Writeback [05:40:45] [PASSED] SPI [05:40:45] [PASSED] USB [05:40:45] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid == [05:40:45] ======== drm_test_drm_connector_dynamic_init_name ========= [05:40:45] [PASSED] Unknown [05:40:45] [PASSED] VGA [05:40:45] [PASSED] DVI-I [05:40:45] [PASSED] DVI-D [05:40:45] [PASSED] DVI-A [05:40:45] [PASSED] Composite [05:40:45] [PASSED] SVIDEO [05:40:45] [PASSED] LVDS [05:40:45] [PASSED] Component [05:40:45] [PASSED] DIN [05:40:45] [PASSED] DP [05:40:45] [PASSED] HDMI-A [05:40:45] [PASSED] HDMI-B [05:40:45] [PASSED] TV [05:40:45] [PASSED] eDP [05:40:45] [PASSED] Virtual [05:40:45] [PASSED] DSI [05:40:45] [PASSED] DPI [05:40:45] [PASSED] Writeback [05:40:45] [PASSED] SPI [05:40:45] [PASSED] USB [05:40:45] ==== [PASSED] drm_test_drm_connector_dynamic_init_name ===== [05:40:45] =========== [PASSED] drm_connector_dynamic_init ============ [05:40:45] ==== drm_connector_dynamic_register_early (4 subtests) ===== [05:40:45] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list [05:40:45] [PASSED] drm_test_drm_connector_dynamic_register_early_defer [05:40:45] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init [05:40:45] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object [05:40:45] ====== [PASSED] drm_connector_dynamic_register_early ======= [05:40:45] ======= drm_connector_dynamic_register (7 subtests) ======== [05:40:45] [PASSED] drm_test_drm_connector_dynamic_register_on_list [05:40:45] [PASSED] drm_test_drm_connector_dynamic_register_no_defer [05:40:45] [PASSED] drm_test_drm_connector_dynamic_register_no_init [05:40:45] [PASSED] drm_test_drm_connector_dynamic_register_mode_object [05:40:45] [PASSED] drm_test_drm_connector_dynamic_register_sysfs [05:40:45] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name [05:40:45] [PASSED] drm_test_drm_connector_dynamic_register_debugfs [05:40:45] ========= [PASSED] drm_connector_dynamic_register ========== [05:40:45] = drm_connector_attach_broadcast_rgb_property (2 subtests) = [05:40:45] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property [05:40:45] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector [05:40:45] === [PASSED] drm_connector_attach_broadcast_rgb_property === [05:40:45] ========== drm_get_tv_mode_from_name (2 subtests) ========== [05:40:45] ========== drm_test_get_tv_mode_from_name_valid =========== [05:40:45] [PASSED] NTSC [05:40:45] [PASSED] NTSC-443 [05:40:45] [PASSED] NTSC-J [05:40:45] [PASSED] PAL [05:40:45] [PASSED] PAL-M [05:40:45] [PASSED] PAL-N [05:40:45] [PASSED] SECAM [05:40:45] [PASSED] Mono [05:40:45] ====== [PASSED] drm_test_get_tv_mode_from_name_valid ======= [05:40:45] [PASSED] drm_test_get_tv_mode_from_name_truncated [05:40:45] ============ [PASSED] drm_get_tv_mode_from_name ============ [05:40:45] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) = [05:40:45] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb [05:40:45] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc [05:40:45] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1 [05:40:45] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc [05:40:45] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1 [05:40:45] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double [05:40:45] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid = [05:40:45] [PASSED] VIC 96 [05:40:45] [PASSED] VIC 97 [05:40:45] [PASSED] VIC 101 [05:40:45] [PASSED] VIC 102 [05:40:45] [PASSED] VIC 106 [05:40:45] [PASSED] VIC 107 [05:40:45] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid === [05:40:45] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc [05:40:45] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc [05:40:45] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc [05:40:45] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc [05:40:45] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc [05:40:45] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ==== [05:40:45] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) == [05:40:45] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ==== [05:40:45] [PASSED] Automatic [05:40:45] [PASSED] Full [05:40:45] [PASSED] Limited 16:235 [05:40:45] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name === [05:40:45] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid [05:40:45] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ==== [05:40:45] == drm_hdmi_connector_get_output_format_name (2 subtests) == [05:40:45] === drm_test_drm_hdmi_connector_get_output_format_name ==== [05:40:45] [PASSED] RGB [05:40:45] [PASSED] YUV 4:2:0 [05:40:45] [PASSED] YUV 4:2:2 [05:40:45] [PASSED] YUV 4:4:4 [05:40:45] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name === [05:40:45] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid [05:40:45] ==== [PASSED] drm_hdmi_connector_get_output_format_name ==== [05:40:45] ============= drm_damage_helper (21 subtests) ============== [05:40:45] [PASSED] drm_test_damage_iter_no_damage [05:40:45] [PASSED] drm_test_damage_iter_no_damage_fractional_src [05:40:45] [PASSED] drm_test_damage_iter_no_damage_src_moved [05:40:45] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved [05:40:45] [PASSED] drm_test_damage_iter_no_damage_not_visible [05:40:45] [PASSED] drm_test_damage_iter_no_damage_no_crtc [05:40:45] [PASSED] drm_test_damage_iter_no_damage_no_fb [05:40:45] [PASSED] drm_test_damage_iter_simple_damage [05:40:45] [PASSED] drm_test_damage_iter_single_damage [05:40:45] [PASSED] drm_test_damage_iter_single_damage_intersect_src [05:40:45] [PASSED] drm_test_damage_iter_single_damage_outside_src [05:40:45] [PASSED] drm_test_damage_iter_single_damage_fractional_src [05:40:45] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src [05:40:45] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src [05:40:45] [PASSED] drm_test_damage_iter_single_damage_src_moved [05:40:45] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved [05:40:45] [PASSED] drm_test_damage_iter_damage [05:40:45] [PASSED] drm_test_damage_iter_damage_one_intersect [05:40:45] [PASSED] drm_test_damage_iter_damage_one_outside [05:40:45] [PASSED] drm_test_damage_iter_damage_src_moved [05:40:45] [PASSED] drm_test_damage_iter_damage_not_visible [05:40:45] ================ [PASSED] drm_damage_helper ================ [05:40:45] ============== drm_dp_mst_helper (3 subtests) ============== [05:40:45] ============== drm_test_dp_mst_calc_pbn_mode ============== [05:40:45] [PASSED] Clock 154000 BPP 30 DSC disabled [05:40:45] [PASSED] Clock 234000 BPP 30 DSC disabled [05:40:45] [PASSED] Clock 297000 BPP 24 DSC disabled [05:40:45] [PASSED] Clock 332880 BPP 24 DSC enabled [05:40:45] [PASSED] Clock 324540 BPP 24 DSC enabled [05:40:45] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ========== [05:40:45] ============== drm_test_dp_mst_calc_pbn_div =============== [05:40:45] [PASSED] Link rate 2000000 lane count 4 [05:40:45] [PASSED] Link rate 2000000 lane count 2 [05:40:45] [PASSED] Link rate 2000000 lane count 1 [05:40:45] [PASSED] Link rate 1350000 lane count 4 [05:40:45] [PASSED] Link rate 1350000 lane count 2 [05:40:45] [PASSED] Link rate 1350000 lane count 1 [05:40:45] [PASSED] Link rate 1000000 lane count 4 [05:40:45] [PASSED] Link rate 1000000 lane count 2 [05:40:45] [PASSED] Link rate 1000000 lane count 1 [05:40:45] [PASSED] Link rate 810000 lane count 4 [05:40:45] [PASSED] Link rate 810000 lane count 2 [05:40:45] [PASSED] Link rate 810000 lane count 1 [05:40:45] [PASSED] Link rate 540000 lane count 4 [05:40:45] [PASSED] Link rate 540000 lane count 2 [05:40:45] [PASSED] Link rate 540000 lane count 1 [05:40:45] [PASSED] Link rate 270000 lane count 4 [05:40:45] [PASSED] Link rate 270000 lane count 2 [05:40:45] [PASSED] Link rate 270000 lane count 1 [05:40:45] [PASSED] Link rate 162000 lane count 4 [05:40:45] [PASSED] Link rate 162000 lane count 2 [05:40:45] [PASSED] Link rate 162000 lane count 1 [05:40:45] ========== [PASSED] drm_test_dp_mst_calc_pbn_div =========== [05:40:45] ========= drm_test_dp_mst_sideband_msg_req_decode ========= [05:40:45] [PASSED] DP_ENUM_PATH_RESOURCES with port number [05:40:45] [PASSED] DP_POWER_UP_PHY with port number [05:40:45] [PASSED] DP_POWER_DOWN_PHY with port number [05:40:45] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks [05:40:45] [PASSED] DP_ALLOCATE_PAYLOAD with port number [05:40:45] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI [05:40:45] [PASSED] DP_ALLOCATE_PAYLOAD with PBN [05:40:45] [PASSED] DP_QUERY_PAYLOAD with port number [05:40:45] [PASSED] DP_QUERY_PAYLOAD with VCPI [05:40:45] [PASSED] DP_REMOTE_DPCD_READ with port number [05:40:45] [PASSED] DP_REMOTE_DPCD_READ with DPCD address [05:40:45] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes [05:40:45] [PASSED] DP_REMOTE_DPCD_WRITE with port number [05:40:45] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address [05:40:45] [PASSED] DP_REMOTE_DPCD_WRITE with data array [05:40:45] [PASSED] DP_REMOTE_I2C_READ with port number [05:40:45] [PASSED] DP_REMOTE_I2C_READ with I2C device ID [05:40:45] [PASSED] DP_REMOTE_I2C_READ with transactions array [05:40:45] [PASSED] DP_REMOTE_I2C_WRITE with port number [05:40:45] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID [05:40:45] [PASSED] DP_REMOTE_I2C_WRITE with data array [05:40:45] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID [05:40:45] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID [05:40:45] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event [05:40:45] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event [05:40:45] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior [05:40:45] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior [05:40:45] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode ===== [05:40:45] ================ [PASSED] drm_dp_mst_helper ================ [05:40:45] ================== drm_exec (7 subtests) =================== [05:40:45] [PASSED] sanitycheck [05:40:45] [PASSED] test_lock [05:40:45] [PASSED] test_lock_unlock [05:40:45] [PASSED] test_duplicates [05:40:45] [PASSED] test_prepare [05:40:45] [PASSED] test_prepare_array [05:40:45] [PASSED] test_multiple_loops [05:40:45] ==================== [PASSED] drm_exec ===================== [05:40:45] =========== drm_format_helper_test (17 subtests) =========== [05:40:45] ============== drm_test_fb_xrgb8888_to_gray8 ============== [05:40:45] [PASSED] single_pixel_source_buffer [05:40:45] [PASSED] single_pixel_clip_rectangle [05:40:45] [PASSED] well_known_colors [05:40:45] [PASSED] destination_pitch [05:40:45] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ========== [05:40:45] ============= drm_test_fb_xrgb8888_to_rgb332 ============== [05:40:45] [PASSED] single_pixel_source_buffer [05:40:45] [PASSED] single_pixel_clip_rectangle [05:40:45] [PASSED] well_known_colors [05:40:45] [PASSED] destination_pitch [05:40:45] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ========== [05:40:45] ============= drm_test_fb_xrgb8888_to_rgb565 ============== [05:40:45] [PASSED] single_pixel_source_buffer [05:40:45] [PASSED] single_pixel_clip_rectangle [05:40:45] [PASSED] well_known_colors [05:40:45] [PASSED] destination_pitch [05:40:45] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ========== [05:40:45] ============ drm_test_fb_xrgb8888_to_xrgb1555 ============= [05:40:45] [PASSED] single_pixel_source_buffer [05:40:45] [PASSED] single_pixel_clip_rectangle [05:40:45] [PASSED] well_known_colors [05:40:45] [PASSED] destination_pitch [05:40:45] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 ========= [05:40:45] ============ drm_test_fb_xrgb8888_to_argb1555 ============= [05:40:45] [PASSED] single_pixel_source_buffer [05:40:45] [PASSED] single_pixel_clip_rectangle [05:40:45] [PASSED] well_known_colors [05:40:45] [PASSED] destination_pitch [05:40:45] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 ========= [05:40:45] ============ drm_test_fb_xrgb8888_to_rgba5551 ============= [05:40:45] [PASSED] single_pixel_source_buffer [05:40:45] [PASSED] single_pixel_clip_rectangle [05:40:45] [PASSED] well_known_colors [05:40:45] [PASSED] destination_pitch [05:40:45] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 ========= [05:40:45] ============= drm_test_fb_xrgb8888_to_rgb888 ============== [05:40:45] [PASSED] single_pixel_source_buffer [05:40:45] [PASSED] single_pixel_clip_rectangle [05:40:45] [PASSED] well_known_colors [05:40:45] [PASSED] destination_pitch [05:40:45] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ========== [05:40:45] ============= drm_test_fb_xrgb8888_to_bgr888 ============== [05:40:45] [PASSED] single_pixel_source_buffer [05:40:45] [PASSED] single_pixel_clip_rectangle [05:40:45] [PASSED] well_known_colors [05:40:45] [PASSED] destination_pitch [05:40:45] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ========== [05:40:45] ============ drm_test_fb_xrgb8888_to_argb8888 ============= [05:40:45] [PASSED] single_pixel_source_buffer [05:40:45] [PASSED] single_pixel_clip_rectangle [05:40:45] [PASSED] well_known_colors [05:40:45] [PASSED] destination_pitch [05:40:45] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 ========= [05:40:45] =========== drm_test_fb_xrgb8888_to_xrgb2101010 =========== [05:40:45] [PASSED] single_pixel_source_buffer [05:40:45] [PASSED] single_pixel_clip_rectangle [05:40:45] [PASSED] well_known_colors [05:40:45] [PASSED] destination_pitch [05:40:45] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 ======= [05:40:45] =========== drm_test_fb_xrgb8888_to_argb2101010 =========== [05:40:45] [PASSED] single_pixel_source_buffer [05:40:45] [PASSED] single_pixel_clip_rectangle [05:40:45] [PASSED] well_known_colors [05:40:45] [PASSED] destination_pitch [05:40:45] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 ======= [05:40:45] ============== drm_test_fb_xrgb8888_to_mono =============== [05:40:45] [PASSED] single_pixel_source_buffer [05:40:45] [PASSED] single_pixel_clip_rectangle [05:40:45] [PASSED] well_known_colors [05:40:45] [PASSED] destination_pitch [05:40:45] ========== [PASSED] drm_test_fb_xrgb8888_to_mono =========== [05:40:45] ==================== drm_test_fb_swab ===================== [05:40:45] [PASSED] single_pixel_source_buffer [05:40:45] [PASSED] single_pixel_clip_rectangle [05:40:45] [PASSED] well_known_colors [05:40:45] [PASSED] destination_pitch [05:40:45] ================ [PASSED] drm_test_fb_swab ================= [05:40:45] ============ drm_test_fb_xrgb8888_to_xbgr8888 ============= [05:40:45] [PASSED] single_pixel_source_buffer [05:40:45] [PASSED] single_pixel_clip_rectangle [05:40:45] [PASSED] well_known_colors [05:40:45] [PASSED] destination_pitch [05:40:45] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 ========= [05:40:45] ============ drm_test_fb_xrgb8888_to_abgr8888 ============= [05:40:45] [PASSED] single_pixel_source_buffer [05:40:45] [PASSED] single_pixel_clip_rectangle [05:40:45] [PASSED] well_known_colors [05:40:45] [PASSED] destination_pitch [05:40:45] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 ========= [05:40:45] ================= drm_test_fb_clip_offset ================= [05:40:45] [PASSED] pass through [05:40:45] [PASSED] horizontal offset [05:40:45] [PASSED] vertical offset [05:40:45] [PASSED] horizontal and vertical offset [05:40:45] [PASSED] horizontal offset (custom pitch) [05:40:45] [PASSED] vertical offset (custom pitch) [05:40:45] [PASSED] horizontal and vertical offset (custom pitch) [05:40:45] ============= [PASSED] drm_test_fb_clip_offset ============= [05:40:45] =================== drm_test_fb_memcpy ==================== [05:40:45] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258) [05:40:45] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258) [05:40:45] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559) [05:40:45] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258) [05:40:45] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258) [05:40:45] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559) [05:40:45] [PASSED] well_known_colors: XB24 little-endian (0x34324258) [05:40:45] [PASSED] well_known_colors: XRA8 little-endian (0x38415258) [05:40:45] [PASSED] well_known_colors: YU24 little-endian (0x34325559) [05:40:45] [PASSED] destination_pitch: XB24 little-endian (0x34324258) [05:40:45] [PASSED] destination_pitch: XRA8 little-endian (0x38415258) [05:40:45] [PASSED] destination_pitch: YU24 little-endian (0x34325559) [05:40:45] =============== [PASSED] drm_test_fb_memcpy ================ [05:40:45] ============= [PASSED] drm_format_helper_test ============== [05:40:45] ================= drm_format (18 subtests) ================= [05:40:45] [PASSED] drm_test_format_block_width_invalid [05:40:45] [PASSED] drm_test_format_block_width_one_plane [05:40:45] [PASSED] drm_test_format_block_width_two_plane [05:40:45] [PASSED] drm_test_format_block_width_three_plane [05:40:45] [PASSED] drm_test_format_block_width_tiled [05:40:45] [PASSED] drm_test_format_block_height_invalid [05:40:45] [PASSED] drm_test_format_block_height_one_plane [05:40:45] [PASSED] drm_test_format_block_height_two_plane [05:40:45] [PASSED] drm_test_format_block_height_three_plane [05:40:45] [PASSED] drm_test_format_block_height_tiled [05:40:45] [PASSED] drm_test_format_min_pitch_invalid [05:40:45] [PASSED] drm_test_format_min_pitch_one_plane_8bpp [05:40:45] [PASSED] drm_test_format_min_pitch_one_plane_16bpp [05:40:45] [PASSED] drm_test_format_min_pitch_one_plane_24bpp [05:40:45] [PASSED] drm_test_format_min_pitch_one_plane_32bpp [05:40:45] [PASSED] drm_test_format_min_pitch_two_plane [05:40:45] [PASSED] drm_test_format_min_pitch_three_plane_8bpp [05:40:45] [PASSED] drm_test_format_min_pitch_tiled [05:40:45] =================== [PASSED] drm_format ==================== [05:40:45] ============== drm_framebuffer (10 subtests) =============== [05:40:45] ========== drm_test_framebuffer_check_src_coords ========== [05:40:45] [PASSED] Success: source fits into fb [05:40:45] [PASSED] Fail: overflowing fb with x-axis coordinate [05:40:45] [PASSED] Fail: overflowing fb with y-axis coordinate [05:40:45] [PASSED] Fail: overflowing fb with source width [05:40:45] [PASSED] Fail: overflowing fb with source height [05:40:45] ====== [PASSED] drm_test_framebuffer_check_src_coords ====== [05:40:45] [PASSED] drm_test_framebuffer_cleanup [05:40:45] =============== drm_test_framebuffer_create =============== [05:40:45] [PASSED] ABGR8888 normal sizes [05:40:45] [PASSED] ABGR8888 max sizes [05:40:45] [PASSED] ABGR8888 pitch greater than min required [05:40:45] [PASSED] ABGR8888 pitch less than min required [05:40:45] [PASSED] ABGR8888 Invalid width [05:40:45] [PASSED] ABGR8888 Invalid buffer handle [05:40:45] [PASSED] No pixel format [05:40:45] [PASSED] ABGR8888 Width 0 [05:40:45] [PASSED] ABGR8888 Height 0 [05:40:45] [PASSED] ABGR8888 Out of bound height * pitch combination [05:40:45] [PASSED] ABGR8888 Large buffer offset [05:40:45] [PASSED] ABGR8888 Buffer offset for inexistent plane [05:40:45] [PASSED] ABGR8888 Invalid flag [05:40:45] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers [05:40:45] [PASSED] ABGR8888 Valid buffer modifier [05:40:45] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE) [05:40:45] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS [05:40:45] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS [05:40:45] [PASSED] NV12 Normal sizes [05:40:45] [PASSED] NV12 Max sizes [05:40:45] [PASSED] NV12 Invalid pitch [05:40:45] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag [05:40:45] [PASSED] NV12 different modifier per-plane [05:40:45] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE [05:40:45] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS [05:40:45] [PASSED] NV12 Modifier for inexistent plane [05:40:45] [PASSED] NV12 Handle for inexistent plane [05:40:45] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS [05:40:45] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier [05:40:45] [PASSED] YVU420 Normal sizes [05:40:45] [PASSED] YVU420 Max sizes [05:40:45] [PASSED] YVU420 Invalid pitch [05:40:45] [PASSED] YVU420 Different pitches [05:40:45] [PASSED] YVU420 Different buffer offsets/pitches [05:40:45] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS [05:40:45] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS [05:40:45] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS [05:40:45] [PASSED] YVU420 Valid modifier [05:40:45] [PASSED] YVU420 Different modifiers per plane [05:40:45] [PASSED] YVU420 Modifier for inexistent plane [05:40:45] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR) [05:40:45] [PASSED] X0L2 Normal sizes [05:40:45] [PASSED] X0L2 Max sizes [05:40:45] [PASSED] X0L2 Invalid pitch [05:40:45] [PASSED] X0L2 Pitch greater than minimum required [05:40:45] [PASSED] X0L2 Handle for inexistent plane [05:40:45] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set [05:40:45] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set [05:40:45] [PASSED] X0L2 Valid modifier [05:40:45] [PASSED] X0L2 Modifier for inexistent plane [05:40:45] =========== [PASSED] drm_test_framebuffer_create =========== [05:40:45] [PASSED] drm_test_framebuffer_free [05:40:45] [PASSED] drm_test_framebuffer_init [05:40:45] [PASSED] drm_test_framebuffer_init_bad_format [05:40:45] [PASSED] drm_test_framebuffer_init_dev_mismatch [05:40:45] [PASSED] drm_test_framebuffer_lookup [05:40:45] [PASSED] drm_test_framebuffer_lookup_inexistent [05:40:45] [PASSED] drm_test_framebuffer_modifiers_not_supported [05:40:45] ================= [PASSED] drm_framebuffer ================= [05:40:45] ================ drm_gem_shmem (8 subtests) ================ [05:40:45] [PASSED] drm_gem_shmem_test_obj_create [05:40:45] [PASSED] drm_gem_shmem_test_obj_create_private [05:40:45] [PASSED] drm_gem_shmem_test_pin_pages [05:40:45] [PASSED] drm_gem_shmem_test_vmap [05:40:45] [PASSED] drm_gem_shmem_test_get_pages_sgt [05:40:45] [PASSED] drm_gem_shmem_test_get_sg_table [05:40:45] [PASSED] drm_gem_shmem_test_madvise [05:40:45] [PASSED] drm_gem_shmem_test_purge [05:40:45] ================== [PASSED] drm_gem_shmem ================== [05:40:45] === drm_atomic_helper_connector_hdmi_check (27 subtests) === [05:40:45] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode [05:40:45] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1 [05:40:45] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode [05:40:45] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1 [05:40:45] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode [05:40:45] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1 [05:40:45] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 ======= [05:40:45] [PASSED] Automatic [05:40:45] [PASSED] Full [05:40:45] [PASSED] Limited 16:235 [05:40:45] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 === [05:40:45] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed [05:40:45] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed [05:40:45] [PASSED] drm_test_check_disable_connector [05:40:45] [PASSED] drm_test_check_hdmi_funcs_reject_rate [05:40:45] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb [05:40:45] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420 [05:40:45] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422 [05:40:45] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420 [05:40:45] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420 [05:40:45] [PASSED] drm_test_check_output_bpc_crtc_mode_changed [05:40:45] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed [05:40:45] [PASSED] drm_test_check_output_bpc_dvi [05:40:45] [PASSED] drm_test_check_output_bpc_format_vic_1 [05:40:45] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only [05:40:45] [PASSED] drm_test_check_output_bpc_format_display_rgb_only [05:40:45] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only [05:40:45] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only [05:40:45] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc [05:40:45] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc [05:40:45] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc [05:40:45] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ====== [05:40:45] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ==== [05:40:45] [PASSED] drm_test_check_broadcast_rgb_value [05:40:45] [PASSED] drm_test_check_bpc_8_value [05:40:45] [PASSED] drm_test_check_bpc_10_value [05:40:45] [PASSED] drm_test_check_bpc_12_value [05:40:45] [PASSED] drm_test_check_format_value [05:40:45] [PASSED] drm_test_check_tmds_char_value [05:40:45] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ====== [05:40:45] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) = [05:40:45] [PASSED] drm_test_check_mode_valid [05:40:45] [PASSED] drm_test_check_mode_valid_reject [05:40:45] [PASSED] drm_test_check_mode_valid_reject_rate [05:40:45] [PASSED] drm_test_check_mode_valid_reject_max_clock [05:40:45] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid === [05:40:45] ================= drm_managed (2 subtests) ================= [05:40:45] [PASSED] drm_test_managed_release_action [05:40:45] [PASSED] drm_test_managed_run_action [05:40:45] =================== [PASSED] drm_managed =================== [05:40:45] =================== drm_mm (6 subtests) ==================== [05:40:45] [PASSED] drm_test_mm_init [05:40:45] [PASSED] drm_test_mm_debug [05:40:45] [PASSED] drm_test_mm_align32 [05:40:45] [PASSED] drm_test_mm_align64 [05:40:45] [PASSED] drm_test_mm_lowest [05:40:45] [PASSED] drm_test_mm_highest [05:40:45] ===================== [PASSED] drm_mm ====================== [05:40:45] ============= drm_modes_analog_tv (5 subtests) ============= [05:40:45] [PASSED] drm_test_modes_analog_tv_mono_576i [05:40:45] [PASSED] drm_test_modes_analog_tv_ntsc_480i [05:40:45] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined [05:40:45] [PASSED] drm_test_modes_analog_tv_pal_576i [05:40:45] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined [05:40:45] =============== [PASSED] drm_modes_analog_tv =============== [05:40:45] ============== drm_plane_helper (2 subtests) =============== [05:40:45] =============== drm_test_check_plane_state ================ [05:40:45] [PASSED] clipping_simple [05:40:45] [PASSED] clipping_rotate_reflect [05:40:45] [PASSED] positioning_simple [05:40:45] [PASSED] upscaling [05:40:45] [PASSED] downscaling [05:40:45] [PASSED] rounding1 [05:40:45] [PASSED] rounding2 [05:40:45] [PASSED] rounding3 [05:40:45] [PASSED] rounding4 [05:40:45] =========== [PASSED] drm_test_check_plane_state ============ [05:40:45] =========== drm_test_check_invalid_plane_state ============ [05:40:45] [PASSED] positioning_invalid [05:40:45] [PASSED] upscaling_invalid [05:40:45] [PASSED] downscaling_invalid [05:40:45] ======= [PASSED] drm_test_check_invalid_plane_state ======== [05:40:45] ================ [PASSED] drm_plane_helper ================= [05:40:45] ====== drm_connector_helper_tv_get_modes (1 subtest) ======= [05:40:45] ====== drm_test_connector_helper_tv_get_modes_check ======= [05:40:45] [PASSED] None [05:40:45] [PASSED] PAL [05:40:45] [PASSED] NTSC [05:40:45] [PASSED] Both, NTSC Default [05:40:45] [PASSED] Both, PAL Default [05:40:45] [PASSED] Both, NTSC Default, with PAL on command-line [05:40:45] [PASSED] Both, PAL Default, with NTSC on command-line [05:40:45] == [PASSED] drm_test_connector_helper_tv_get_modes_check === [05:40:45] ======== [PASSED] drm_connector_helper_tv_get_modes ======== [05:40:45] ================== drm_rect (9 subtests) =================== [05:40:45] [PASSED] drm_test_rect_clip_scaled_div_by_zero [05:40:45] [PASSED] drm_test_rect_clip_scaled_not_clipped [05:40:45] [PASSED] drm_test_rect_clip_scaled_clipped [05:40:45] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned [05:40:45] ================= drm_test_rect_intersect ================= [05:40:45] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0 [05:40:45] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1 [05:40:45] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0 [05:40:45] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1 [05:40:45] [PASSED] right x left: 2x1+0+0 x 3x1+1+0 [05:40:45] [PASSED] left x right: 3x1+1+0 x 2x1+0+0 [05:40:45] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1 [05:40:45] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0 [05:40:45] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1 [05:40:45] [PASSED] touching side: 1x1+0+0 x 1x1+1+0 [05:40:45] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0 [05:40:45] [PASSED] inside another: 2x2+0+0 x 1x1+1+1 [05:40:45] [PASSED] far away: 1x1+0+0 x 1x1+3+6 [05:40:45] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10 [05:40:45] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10 [05:40:45] ============= [PASSED] drm_test_rect_intersect ============= [05:40:45] ================ drm_test_rect_calc_hscale ================ [05:40:45] [PASSED] normal use [05:40:45] [PASSED] out of max range [05:40:45] [PASSED] out of min range [05:40:45] [PASSED] zero dst [05:40:45] [PASSED] negative src [05:40:45] [PASSED] negative dst [05:40:45] ============ [PASSED] drm_test_rect_calc_hscale ============ [05:40:45] ================ drm_test_rect_calc_vscale ================ [05:40:45] [PASSED] normal use [05:40:45] [PASSED] out of max range [05:40:45] [PASSED] out of min range [05:40:45] [PASSED] zero dst [05:40:45] [PASSED] negative src [05:40:45] [PASSED] negative dst [05:40:45] ============ [PASSED] drm_test_rect_calc_vscale ============ [05:40:45] ================== drm_test_rect_rotate =================== [05:40:45] [PASSED] reflect-x [05:40:45] [PASSED] reflect-y [05:40:45] [PASSED] rotate-0 [05:40:45] [PASSED] rotate-90 [05:40:45] [PASSED] rotate-180 [05:40:45] [PASSED] rotate-270 stty: 'standard input': Inappropriate ioctl for device [05:40:45] ============== [PASSED] drm_test_rect_rotate =============== [05:40:45] ================ drm_test_rect_rotate_inv ================= [05:40:45] [PASSED] reflect-x [05:40:45] [PASSED] reflect-y [05:40:45] [PASSED] rotate-0 [05:40:45] [PASSED] rotate-90 [05:40:45] [PASSED] rotate-180 [05:40:45] [PASSED] rotate-270 [05:40:45] ============ [PASSED] drm_test_rect_rotate_inv ============= [05:40:45] ==================== [PASSED] drm_rect ===================== [05:40:45] ============ drm_sysfb_modeset_test (1 subtest) ============ [05:40:45] ============ drm_test_sysfb_build_fourcc_list ============= [05:40:45] [PASSED] no native formats [05:40:45] [PASSED] XRGB8888 as native format [05:40:45] [PASSED] remove duplicates [05:40:45] [PASSED] convert alpha formats [05:40:45] [PASSED] random formats [05:40:45] ======== [PASSED] drm_test_sysfb_build_fourcc_list ========= [05:40:45] ============= [PASSED] drm_sysfb_modeset_test ============== [05:40:45] ============================================================ [05:40:45] Testing complete. Ran 616 tests: passed: 616 [05:40:45] Elapsed time: 27.549s total, 1.589s configuring, 25.743s building, 0.187s running + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig [05:40:45] Configuring KUnit Kernel ... Regenerating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [05:40:46] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25 [05:40:54] Starting KUnit Kernel (1/1)... [05:40:54] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [05:40:54] ================= ttm_device (5 subtests) ================== [05:40:54] [PASSED] ttm_device_init_basic [05:40:54] [PASSED] ttm_device_init_multiple [05:40:54] [PASSED] ttm_device_fini_basic [05:40:54] [PASSED] ttm_device_init_no_vma_man [05:40:54] ================== ttm_device_init_pools ================== [05:40:54] [PASSED] No DMA allocations, no DMA32 required [05:40:54] [PASSED] DMA allocations, DMA32 required [05:40:54] [PASSED] No DMA allocations, DMA32 required [05:40:54] [PASSED] DMA allocations, no DMA32 required [05:40:54] ============== [PASSED] ttm_device_init_pools ============== [05:40:54] =================== [PASSED] ttm_device ==================== [05:40:54] ================== ttm_pool (8 subtests) =================== [05:40:54] ================== ttm_pool_alloc_basic =================== [05:40:54] [PASSED] One page [05:40:54] [PASSED] More than one page [05:40:54] [PASSED] Above the allocation limit [05:40:54] [PASSED] One page, with coherent DMA mappings enabled [05:40:54] [PASSED] Above the allocation limit, with coherent DMA mappings enabled [05:40:54] ============== [PASSED] ttm_pool_alloc_basic =============== [05:40:54] ============== ttm_pool_alloc_basic_dma_addr ============== [05:40:54] [PASSED] One page [05:40:54] [PASSED] More than one page [05:40:54] [PASSED] Above the allocation limit [05:40:54] [PASSED] One page, with coherent DMA mappings enabled [05:40:54] [PASSED] Above the allocation limit, with coherent DMA mappings enabled [05:40:54] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ========== [05:40:54] [PASSED] ttm_pool_alloc_order_caching_match [05:40:54] [PASSED] ttm_pool_alloc_caching_mismatch [05:40:54] [PASSED] ttm_pool_alloc_order_mismatch [05:40:54] [PASSED] ttm_pool_free_dma_alloc [05:40:54] [PASSED] ttm_pool_free_no_dma_alloc [05:40:54] [PASSED] ttm_pool_fini_basic [05:40:54] ==================== [PASSED] ttm_pool ===================== [05:40:54] ================ ttm_resource (8 subtests) ================= [05:40:54] ================= ttm_resource_init_basic ================= [05:40:54] [PASSED] Init resource in TTM_PL_SYSTEM [05:40:54] [PASSED] Init resource in TTM_PL_VRAM [05:40:54] [PASSED] Init resource in a private placement [05:40:54] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags [05:40:54] ============= [PASSED] ttm_resource_init_basic ============= [05:40:54] [PASSED] ttm_resource_init_pinned [05:40:54] [PASSED] ttm_resource_fini_basic [05:40:54] [PASSED] ttm_resource_manager_init_basic [05:40:54] [PASSED] ttm_resource_manager_usage_basic [05:40:54] [PASSED] ttm_resource_manager_set_used_basic [05:40:54] [PASSED] ttm_sys_man_alloc_basic [05:40:54] [PASSED] ttm_sys_man_free_basic [05:40:54] ================== [PASSED] ttm_resource =================== [05:40:54] =================== ttm_tt (15 subtests) =================== [05:40:54] ==================== ttm_tt_init_basic ==================== [05:40:54] [PASSED] Page-aligned size [05:40:54] [PASSED] Extra pages requested [05:40:54] ================ [PASSED] ttm_tt_init_basic ================ [05:40:54] [PASSED] ttm_tt_init_misaligned [05:40:54] [PASSED] ttm_tt_fini_basic [05:40:54] [PASSED] ttm_tt_fini_sg [05:40:54] [PASSED] ttm_tt_fini_shmem [05:40:54] [PASSED] ttm_tt_create_basic [05:40:54] [PASSED] ttm_tt_create_invalid_bo_type [05:40:54] [PASSED] ttm_tt_create_ttm_exists [05:40:54] [PASSED] ttm_tt_create_failed [05:40:54] [PASSED] ttm_tt_destroy_basic [05:40:54] [PASSED] ttm_tt_populate_null_ttm [05:40:54] [PASSED] ttm_tt_populate_populated_ttm [05:40:54] [PASSED] ttm_tt_unpopulate_basic [05:40:54] [PASSED] ttm_tt_unpopulate_empty_ttm [05:40:54] [PASSED] ttm_tt_swapin_basic [05:40:54] ===================== [PASSED] ttm_tt ====================== [05:40:54] =================== ttm_bo (14 subtests) =================== [05:40:54] =========== ttm_bo_reserve_optimistic_no_ticket =========== [05:40:54] [PASSED] Cannot be interrupted and sleeps [05:40:54] [PASSED] Cannot be interrupted, locks straight away [05:40:54] [PASSED] Can be interrupted, sleeps [05:40:54] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket ======= [05:40:54] [PASSED] ttm_bo_reserve_locked_no_sleep [05:40:54] [PASSED] ttm_bo_reserve_no_wait_ticket [05:40:54] [PASSED] ttm_bo_reserve_double_resv [05:40:54] [PASSED] ttm_bo_reserve_interrupted [05:40:54] [PASSED] ttm_bo_reserve_deadlock [05:40:54] [PASSED] ttm_bo_unreserve_basic [05:40:54] [PASSED] ttm_bo_unreserve_pinned [05:40:54] [PASSED] ttm_bo_unreserve_bulk [05:40:54] [PASSED] ttm_bo_put_basic [05:40:54] [PASSED] ttm_bo_put_shared_resv [05:40:54] [PASSED] ttm_bo_pin_basic [05:40:54] [PASSED] ttm_bo_pin_unpin_resource [05:40:54] [PASSED] ttm_bo_multiple_pin_one_unpin [05:40:54] ===================== [PASSED] ttm_bo ====================== [05:40:54] ============== ttm_bo_validate (21 subtests) =============== [05:40:54] ============== ttm_bo_init_reserved_sys_man =============== [05:40:54] [PASSED] Buffer object for userspace [05:40:54] [PASSED] Kernel buffer object [05:40:54] [PASSED] Shared buffer object [05:40:54] ========== [PASSED] ttm_bo_init_reserved_sys_man =========== [05:40:54] ============== ttm_bo_init_reserved_mock_man ============== [05:40:54] [PASSED] Buffer object for userspace [05:40:54] [PASSED] Kernel buffer object [05:40:54] [PASSED] Shared buffer object [05:40:54] ========== [PASSED] ttm_bo_init_reserved_mock_man ========== [05:40:54] [PASSED] ttm_bo_init_reserved_resv [05:40:54] ================== ttm_bo_validate_basic ================== [05:40:54] [PASSED] Buffer object for userspace [05:40:54] [PASSED] Kernel buffer object [05:40:54] [PASSED] Shared buffer object [05:40:54] ============== [PASSED] ttm_bo_validate_basic ============== [05:40:54] [PASSED] ttm_bo_validate_invalid_placement [05:40:54] ============= ttm_bo_validate_same_placement ============== [05:40:54] [PASSED] System manager [05:40:54] [PASSED] VRAM manager [05:40:54] ========= [PASSED] ttm_bo_validate_same_placement ========== [05:40:54] [PASSED] ttm_bo_validate_failed_alloc [05:40:54] [PASSED] ttm_bo_validate_pinned [05:40:54] [PASSED] ttm_bo_validate_busy_placement [05:40:54] ================ ttm_bo_validate_multihop ================= [05:40:54] [PASSED] Buffer object for userspace [05:40:54] [PASSED] Kernel buffer object [05:40:54] [PASSED] Shared buffer object [05:40:54] ============ [PASSED] ttm_bo_validate_multihop ============= [05:40:54] ========== ttm_bo_validate_no_placement_signaled ========== [05:40:54] [PASSED] Buffer object in system domain, no page vector [05:40:54] [PASSED] Buffer object in system domain with an existing page vector [05:40:54] ====== [PASSED] ttm_bo_validate_no_placement_signaled ====== [05:40:54] ======== ttm_bo_validate_no_placement_not_signaled ======== [05:40:54] [PASSED] Buffer object for userspace [05:40:54] [PASSED] Kernel buffer object [05:40:54] [PASSED] Shared buffer object [05:40:54] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ==== [05:40:54] [PASSED] ttm_bo_validate_move_fence_signaled [05:40:54] ========= ttm_bo_validate_move_fence_not_signaled ========= [05:40:54] [PASSED] Waits for GPU [05:40:54] [PASSED] Tries to lock straight away [05:40:54] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled ===== [05:40:54] [PASSED] ttm_bo_validate_happy_evict [05:40:54] [PASSED] ttm_bo_validate_all_pinned_evict [05:40:54] [PASSED] ttm_bo_validate_allowed_only_evict [05:40:54] [PASSED] ttm_bo_validate_deleted_evict [05:40:54] [PASSED] ttm_bo_validate_busy_domain_evict [05:40:54] [PASSED] ttm_bo_validate_evict_gutting [05:40:54] [PASSED] ttm_bo_validate_recrusive_evict stty: 'standard input': Inappropriate ioctl for device [05:40:54] ================= [PASSED] ttm_bo_validate ================= [05:40:54] ============================================================ [05:40:54] Testing complete. Ran 101 tests: passed: 101 [05:40:54] Elapsed time: 9.526s total, 1.605s configuring, 7.655s building, 0.230s running + cleanup ++ stat -c %u:%g /kernel + chown -R 1003:1003 /kernel ^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Xe.CI.BAT: success for drm/i915/display: Skip unavailable power wells based on pipe mask 2025-07-17 5:16 [PATCH] drm/i915/display: Skip unavailable power wells based on pipe mask Chaitanya Kumar Borah 2025-07-17 5:39 ` ✗ CI.checkpatch: warning for " Patchwork 2025-07-17 5:41 ` ✓ CI.KUnit: success " Patchwork @ 2025-07-17 7:09 ` Patchwork 2025-07-17 12:02 ` [PATCH] " Gustavo Sousa 2025-07-18 8:46 ` ✗ Xe.CI.Full: failure for " Patchwork 4 siblings, 0 replies; 14+ messages in thread From: Patchwork @ 2025-07-17 7:09 UTC (permalink / raw) To: Chaitanya Kumar Borah; +Cc: intel-xe [-- Attachment #1: Type: text/plain, Size: 972 bytes --] == Series Details == Series: drm/i915/display: Skip unavailable power wells based on pipe mask URL : https://patchwork.freedesktop.org/series/151737/ State : success == Summary == CI Bug Log - changes from xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331_BAT -> xe-pw-151737v1_BAT ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (8 -> 7) ------------------------------ Missing (1): bat-adlp-vm Changes ------- No changes found Build changes ------------- * Linux: xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331 -> xe-pw-151737v1 IGT_8462: f33a311145a889757f45313d2ff4bf58f7ef01d6 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331: e7058b7a607f5fdfd7bc4586644756d7ef002331 xe-pw-151737v1: 151737v1 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/index.html [-- Attachment #2: Type: text/html, Size: 1520 bytes --] ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/display: Skip unavailable power wells based on pipe mask 2025-07-17 5:16 [PATCH] drm/i915/display: Skip unavailable power wells based on pipe mask Chaitanya Kumar Borah ` (2 preceding siblings ...) 2025-07-17 7:09 ` ✓ Xe.CI.BAT: " Patchwork @ 2025-07-17 12:02 ` Gustavo Sousa 2025-07-18 15:54 ` Imre Deak 2025-07-18 8:46 ` ✗ Xe.CI.Full: failure for " Patchwork 4 siblings, 1 reply; 14+ messages in thread From: Gustavo Sousa @ 2025-07-17 12:02 UTC (permalink / raw) To: Chaitanya Kumar Borah, intel-gfx, intel-xe Cc: dnyaneshwar.bhadane, dibin.moolakadan.subrahmanian, imre.deak Quoting Chaitanya Kumar Borah (2025-07-17 02:16:03-03:00) >Some power wells are only relevant for certain display pipes. Add a check >to ensure we only allocate and initialize power wells whose associated >pipes are available on the platform. > >This avoids unnecessary mapping of power wells, particularly when platforms >support a subset of pipes described in the power well descriptors. > >Suggested-by: Imre Deak <imre.deak@intel.com> >Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> >--- > .../i915/display/intel_display_power_map.c | 19 +++++++++++++++++-- > 1 file changed, 17 insertions(+), 2 deletions(-) > >diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c >index 77268802b55e..ca73e4084354 100644 >--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c >+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c >@@ -1748,6 +1748,16 @@ static void init_power_well_domains(const struct i915_power_well_instance *inst, > for_each_power_well_instance_in_desc_list((_descs)->list, (_descs)->count, \ > (_desc), (_inst)) > >+static bool >+is_power_well_available(struct intel_display *display, const struct i915_power_well_desc *desc) >+{ >+ if (desc->irq_pipe_mask && >+ !(desc->irq_pipe_mask & DISPLAY_RUNTIME_INFO(display)->pipe_mask)) According to irq_pipe_mask's documentation, that member contains a "mask of pipes whose IRQ logic is backed by the pw". I think we are overloading the meaning of that field with this logic. * Do we have guarantees that irq_pipe_mask will always be associated with the power well that powers the pipe? * If the power well that has irq_pipe_mask is also used to power something else than the pipes, we could have issues if pipes in that mask are fused off. I'm leaning more toward a solution that makes POWER_DOMAIN_INIT map to POWER_DOMAIN_PIPE_* based on DISPLAY_RUNTIME_INFO(display)->pipe_mask. I have some idea of how to do that without rewriting code to use a hierarchical structure (which IMO would be ideal, but takes more effort). The idea is to, during runtime and initialization of the mapping, set the bit respective to POWER_DOMAIN_INIT in each power well that has the bit for POWER_DOMAIN_PIPE_* set for non-fused off pipes. That would also require removing the POWER_DOMAIN_INIT from the static mapping for power wells directly responsible for POWER_DOMAIN_PIPE_*. -- Gustavo Sousa >+ return false; >+ >+ return true; >+} >+ > static int > __set_power_wells(struct i915_power_domains *power_domains, > const struct i915_power_well_desc_list *power_well_descs, >@@ -1763,8 +1773,10 @@ __set_power_wells(struct i915_power_domains *power_domains, > int power_well_count = 0; > int plt_idx = 0; > >- for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) >- power_well_count++; >+ for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) { >+ if (is_power_well_available(display, desc)) >+ power_well_count++; >+ } > > power_domains->power_well_count = power_well_count; > power_domains->power_wells = >@@ -1778,6 +1790,9 @@ __set_power_wells(struct i915_power_domains *power_domains, > struct i915_power_well *pw = &power_domains->power_wells[plt_idx]; > enum i915_power_well_id id = inst->id; > >+ if (!is_power_well_available(display, desc)) >+ continue; >+ > pw->desc = desc; > drm_WARN_ON(display->drm, > overflows_type(inst - desc->instances->list, pw->instance_idx)); >-- >2.25.1 > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/display: Skip unavailable power wells based on pipe mask 2025-07-17 12:02 ` [PATCH] " Gustavo Sousa @ 2025-07-18 15:54 ` Imre Deak 2025-07-18 16:33 ` Gustavo Sousa 0 siblings, 1 reply; 14+ messages in thread From: Imre Deak @ 2025-07-18 15:54 UTC (permalink / raw) To: Gustavo Sousa, Chaitanya Kumar Borah Cc: intel-gfx, intel-xe, dnyaneshwar.bhadane, dibin.moolakadan.subrahmanian On Thu, Jul 17, 2025 at 09:02:45AM -0300, Gustavo Sousa wrote: > Quoting Chaitanya Kumar Borah (2025-07-17 02:16:03-03:00) > >Some power wells are only relevant for certain display pipes. Add a check > >to ensure we only allocate and initialize power wells whose associated > >pipes are available on the platform. > > > >This avoids unnecessary mapping of power wells, particularly when platforms > >support a subset of pipes described in the power well descriptors. > > > >Suggested-by: Imre Deak <imre.deak@intel.com> > >Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> > >--- > > .../i915/display/intel_display_power_map.c | 19 +++++++++++++++++-- > > 1 file changed, 17 insertions(+), 2 deletions(-) > > > >diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c > >index 77268802b55e..ca73e4084354 100644 > >--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c > >+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c > >@@ -1748,6 +1748,16 @@ static void init_power_well_domains(const struct i915_power_well_instance *inst, > > for_each_power_well_instance_in_desc_list((_descs)->list, (_descs)->count, \ > > (_desc), (_inst)) > > > >+static bool > >+is_power_well_available(struct intel_display *display, const struct i915_power_well_desc *desc) > >+{ > >+ if (desc->irq_pipe_mask && > >+ !(desc->irq_pipe_mask & DISPLAY_RUNTIME_INFO(display)->pipe_mask)) > > According to irq_pipe_mask's documentation, that member contains a "mask > of pipes whose IRQ logic is backed by the pw". I think we are > overloading the meaning of that field with this logic. > > * Do we have guarantees that irq_pipe_mask will always be associated > with the power well that powers the pipe? It is the case on all the platforms and so it also provides the required way to identify the power well for a particular pipe. irq_pipe_mask could be renamed to pipe_mask accordingly. > * If the power well that has irq_pipe_mask is also used to power > something else than the pipes, we could have issues if pipes in that > mask are fused off. > > I'm leaning more toward a solution that makes POWER_DOMAIN_INIT map to > POWER_DOMAIN_PIPE_* based on DISPLAY_RUNTIME_INFO(display)->pipe_mask. I > have some idea of how to do that without rewriting code to use a > hierarchical structure (which IMO would be ideal, but takes more > effort). > > The idea is to, during runtime and initialization of the mapping, set > the bit respective to POWER_DOMAIN_INIT in each power well that has the > bit for POWER_DOMAIN_PIPE_* set for non-fused off pipes. That would > also require removing the POWER_DOMAIN_INIT from the static mapping for > power wells directly responsible for POWER_DOMAIN_PIPE_*. Power wells that don't exist on a platform shouldn't be registered in the first place, so it's not enough to only remove them from the power well->domain mapping, while still registering the power well. Otherwise these non-existant power wells would still be accessed while disabling any unused power well during driver loading/resume. Also these power wells non-existant on a platform would be incorrectly listed in debugfs and other state dumps. However, I realized that pipe power wells that do exist on a platform, but for which the corresponing pipe is fused off (for instance pipe A/B/C on WCL) we still need to register the power well. On some platforms at least such power wells may be enabled after HW reset/by BIOS and so these still need to be checked and disabled if needed during driver loading/resume. I.e. instead of the above DISPLAY_RUNTIME_INFO(display)->pipe_mask something like the following should be used: u8 pipe_pw_mask(display) { if (DISPLAY_VERx100(display) == 3002) return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); return BIT(I915_MAX_PIPES + 1) - 1; } > -- > Gustavo Sousa > > >+ return false; > >+ > >+ return true; > >+} > >+ > > static int > > __set_power_wells(struct i915_power_domains *power_domains, > > const struct i915_power_well_desc_list *power_well_descs, > >@@ -1763,8 +1773,10 @@ __set_power_wells(struct i915_power_domains *power_domains, > > int power_well_count = 0; > > int plt_idx = 0; > > > >- for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) > >- power_well_count++; > >+ for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) { > >+ if (is_power_well_available(display, desc)) > >+ power_well_count++; > >+ } > > > > power_domains->power_well_count = power_well_count; > > power_domains->power_wells = > >@@ -1778,6 +1790,9 @@ __set_power_wells(struct i915_power_domains *power_domains, > > struct i915_power_well *pw = &power_domains->power_wells[plt_idx]; > > enum i915_power_well_id id = inst->id; > > > >+ if (!is_power_well_available(display, desc)) > >+ continue; > >+ > > pw->desc = desc; > > drm_WARN_ON(display->drm, > > overflows_type(inst - desc->instances->list, pw->instance_idx)); > >-- > >2.25.1 > > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/display: Skip unavailable power wells based on pipe mask 2025-07-18 15:54 ` Imre Deak @ 2025-07-18 16:33 ` Gustavo Sousa 2025-07-18 17:17 ` Imre Deak 0 siblings, 1 reply; 14+ messages in thread From: Gustavo Sousa @ 2025-07-18 16:33 UTC (permalink / raw) To: Chaitanya Kumar Borah, Imre Deak Cc: intel-gfx, intel-xe, dnyaneshwar.bhadane, dibin.moolakadan.subrahmanian Quoting Imre Deak (2025-07-18 12:54:11-03:00) >On Thu, Jul 17, 2025 at 09:02:45AM -0300, Gustavo Sousa wrote: >> Quoting Chaitanya Kumar Borah (2025-07-17 02:16:03-03:00) >> >Some power wells are only relevant for certain display pipes. Add a check >> >to ensure we only allocate and initialize power wells whose associated >> >pipes are available on the platform. >> > >> >This avoids unnecessary mapping of power wells, particularly when platforms >> >support a subset of pipes described in the power well descriptors. >> > >> >Suggested-by: Imre Deak <imre.deak@intel.com> >> >Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> >> >--- >> > .../i915/display/intel_display_power_map.c | 19 +++++++++++++++++-- >> > 1 file changed, 17 insertions(+), 2 deletions(-) >> > >> >diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c >> >index 77268802b55e..ca73e4084354 100644 >> >--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c >> >+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c >> >@@ -1748,6 +1748,16 @@ static void init_power_well_domains(const struct i915_power_well_instance *inst, >> > for_each_power_well_instance_in_desc_list((_descs)->list, (_descs)->count, \ >> > (_desc), (_inst)) >> > >> >+static bool >> >+is_power_well_available(struct intel_display *display, const struct i915_power_well_desc *desc) >> >+{ >> >+ if (desc->irq_pipe_mask && >> >+ !(desc->irq_pipe_mask & DISPLAY_RUNTIME_INFO(display)->pipe_mask)) >> >> According to irq_pipe_mask's documentation, that member contains a "mask >> of pipes whose IRQ logic is backed by the pw". I think we are >> overloading the meaning of that field with this logic. >> >> * Do we have guarantees that irq_pipe_mask will always be associated >> with the power well that powers the pipe? > >It is the case on all the platforms and so it also provides the required >way to identify the power well for a particular pipe. irq_pipe_mask >could be renamed to pipe_mask accordingly. I mean, that *exclusively* powers the pipe(s). As an example, bdw_pwdoms_display appears to be responsible not only for pipe B and C, but also ddi lanes and audio, for example. > >> * If the power well that has irq_pipe_mask is also used to power >> something else than the pipes, we could have issues if pipes in that >> mask are fused off. >> >> I'm leaning more toward a solution that makes POWER_DOMAIN_INIT map to >> POWER_DOMAIN_PIPE_* based on DISPLAY_RUNTIME_INFO(display)->pipe_mask. I >> have some idea of how to do that without rewriting code to use a >> hierarchical structure (which IMO would be ideal, but takes more >> effort). >> >> The idea is to, during runtime and initialization of the mapping, set >> the bit respective to POWER_DOMAIN_INIT in each power well that has the >> bit for POWER_DOMAIN_PIPE_* set for non-fused off pipes. That would >> also require removing the POWER_DOMAIN_INIT from the static mapping for >> power wells directly responsible for POWER_DOMAIN_PIPE_*. > >Power wells that don't exist on a platform shouldn't be registered in >the first place, so it's not enough to only remove them from the power >well->domain mapping, while still registering the power well. Otherwise >these non-existant power wells would still be accessed while disabling >any unused power well during driver loading/resume. Also these power >wells non-existant on a platform would be incorrectly listed in debugfs >and other state dumps. > >However, I realized that pipe power wells that do exist on a platform, >but for which the corresponing pipe is fused off (for instance pipe >A/B/C on WCL) we still need to register the power well. On some >platforms at least such power wells may be enabled after HW reset/by >BIOS and so these still need to be checked and disabled if needed during >driver loading/resume. I.e. instead of the above Ah, I see. Yeah, that makes sense. Thanks for the details! Well, although Bspec overview page tells that WCL's display has only pipes A, B and C, the page specific for power wells still lists power well D. So I'm wondering if WCL display just has pipe D fused off and the power well still exists or if power well D being listed in Bspec is just a documentation mistake. I'll check with the hardware team. > >DISPLAY_RUNTIME_INFO(display)->pipe_mask > >something like the following should be used: > >u8 pipe_pw_mask(display) >{ > if (DISPLAY_VERx100(display) == 3002) > return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); > > return BIT(I915_MAX_PIPES + 1) - 1; >} Well, if power well D does not exist indeed (i.e. not a case of pipe D fused-off), we need either this above or maybe go back to Chaitanya's original patch. I think I prefer the original patch, making the power well mapping explicit. -- Gustavo Sousa > >> -- >> Gustavo Sousa >> >> >+ return false; >> >+ >> >+ return true; >> >+} >> >+ >> > static int >> > __set_power_wells(struct i915_power_domains *power_domains, >> > const struct i915_power_well_desc_list *power_well_descs, >> >@@ -1763,8 +1773,10 @@ __set_power_wells(struct i915_power_domains *power_domains, >> > int power_well_count = 0; >> > int plt_idx = 0; >> > >> >- for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) >> >- power_well_count++; >> >+ for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) { >> >+ if (is_power_well_available(display, desc)) >> >+ power_well_count++; >> >+ } >> > >> > power_domains->power_well_count = power_well_count; >> > power_domains->power_wells = >> >@@ -1778,6 +1790,9 @@ __set_power_wells(struct i915_power_domains *power_domains, >> > struct i915_power_well *pw = &power_domains->power_wells[plt_idx]; >> > enum i915_power_well_id id = inst->id; >> > >> >+ if (!is_power_well_available(display, desc)) >> >+ continue; >> >+ >> > pw->desc = desc; >> > drm_WARN_ON(display->drm, >> > overflows_type(inst - desc->instances->list, pw->instance_idx)); >> >-- >> >2.25.1 >> > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/display: Skip unavailable power wells based on pipe mask 2025-07-18 16:33 ` Gustavo Sousa @ 2025-07-18 17:17 ` Imre Deak 2025-07-18 20:16 ` Gustavo Sousa 0 siblings, 1 reply; 14+ messages in thread From: Imre Deak @ 2025-07-18 17:17 UTC (permalink / raw) To: Gustavo Sousa Cc: Chaitanya Kumar Borah, intel-gfx, intel-xe, dnyaneshwar.bhadane, dibin.moolakadan.subrahmanian On Fri, Jul 18, 2025 at 01:33:26PM -0300, Gustavo Sousa wrote: > Quoting Imre Deak (2025-07-18 12:54:11-03:00) > >On Thu, Jul 17, 2025 at 09:02:45AM -0300, Gustavo Sousa wrote: > >> Quoting Chaitanya Kumar Borah (2025-07-17 02:16:03-03:00) > >> >Some power wells are only relevant for certain display pipes. Add a check > >> >to ensure we only allocate and initialize power wells whose associated > >> >pipes are available on the platform. > >> > > >> >This avoids unnecessary mapping of power wells, particularly when platforms > >> >support a subset of pipes described in the power well descriptors. > >> > > >> >Suggested-by: Imre Deak <imre.deak@intel.com> > >> >Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> > >> >--- > >> > .../i915/display/intel_display_power_map.c | 19 +++++++++++++++++-- > >> > 1 file changed, 17 insertions(+), 2 deletions(-) > >> > > >> >diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c > >> >index 77268802b55e..ca73e4084354 100644 > >> >--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c > >> >+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c > >> >@@ -1748,6 +1748,16 @@ static void init_power_well_domains(const struct i915_power_well_instance *inst, > >> > for_each_power_well_instance_in_desc_list((_descs)->list, (_descs)->count, \ > >> > (_desc), (_inst)) > >> > > >> >+static bool > >> >+is_power_well_available(struct intel_display *display, const struct i915_power_well_desc *desc) > >> >+{ > >> >+ if (desc->irq_pipe_mask && > >> >+ !(desc->irq_pipe_mask & DISPLAY_RUNTIME_INFO(display)->pipe_mask)) > >> > >> According to irq_pipe_mask's documentation, that member contains a "mask > >> of pipes whose IRQ logic is backed by the pw". I think we are > >> overloading the meaning of that field with this logic. > >> > >> * Do we have guarantees that irq_pipe_mask will always be associated > >> with the power well that powers the pipe? > > > >It is the case on all the platforms and so it also provides the required > >way to identify the power well for a particular pipe. irq_pipe_mask > >could be renamed to pipe_mask accordingly. > > I mean, that *exclusively* powers the pipe(s). > > As an example, bdw_pwdoms_display appears to be responsible not only for > pipe B and C, but also ddi lanes and audio, for example. Yes, these power wells do support other functionalities as well and so they must be registered unconditionally. pipe_mask would still be correctly indicating that this is the power well for the pipes in the mask; these power wells wouldn't be skipped either during registration, since that logic must use a platform pipe power well mask vs. a non-fused-off pipe mask. > >> * If the power well that has irq_pipe_mask is also used to power > >> something else than the pipes, we could have issues if pipes in that > >> mask are fused off. > >> > >> I'm leaning more toward a solution that makes POWER_DOMAIN_INIT map to > >> POWER_DOMAIN_PIPE_* based on DISPLAY_RUNTIME_INFO(display)->pipe_mask. I > >> have some idea of how to do that without rewriting code to use a > >> hierarchical structure (which IMO would be ideal, but takes more > >> effort). > >> > >> The idea is to, during runtime and initialization of the mapping, set > >> the bit respective to POWER_DOMAIN_INIT in each power well that has the > >> bit for POWER_DOMAIN_PIPE_* set for non-fused off pipes. That would > >> also require removing the POWER_DOMAIN_INIT from the static mapping for > >> power wells directly responsible for POWER_DOMAIN_PIPE_*. > > > >Power wells that don't exist on a platform shouldn't be registered in > >the first place, so it's not enough to only remove them from the power > >well->domain mapping, while still registering the power well. Otherwise > >these non-existant power wells would still be accessed while disabling > >any unused power well during driver loading/resume. Also these power > >wells non-existant on a platform would be incorrectly listed in debugfs > >and other state dumps. > > > >However, I realized that pipe power wells that do exist on a platform, > >but for which the corresponing pipe is fused off (for instance pipe > >A/B/C on WCL) we still need to register the power well. On some > >platforms at least such power wells may be enabled after HW reset/by > >BIOS and so these still need to be checked and disabled if needed during > >driver loading/resume. I.e. instead of the above > > Ah, I see. Yeah, that makes sense. Thanks for the details! > > Well, although Bspec overview page tells that WCL's display has only > pipes A, B and C, the page specific for power wells still lists power > well D. So I'm wondering if WCL display just has pipe D fused off and > the power well still exists or if power well D being listed in Bspec is > just a documentation mistake. I'll check with the hardware team. > > > > >DISPLAY_RUNTIME_INFO(display)->pipe_mask > > > >something like the following should be used: > > > >u8 pipe_pw_mask(display) > >{ > > if (DISPLAY_VERx100(display) == 3002) > > return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); > > > > return BIT(I915_MAX_PIPES + 1) - 1; > >} > > Well, if power well D does not exist indeed (i.e. not a case of pipe D > fused-off), we need either this above or maybe go back to Chaitanya's > original patch. > > I think I prefer the original patch, making the power well mapping > explicit. > > -- > Gustavo Sousa > > > > >> -- > >> Gustavo Sousa > >> > >> >+ return false; > >> >+ > >> >+ return true; > >> >+} > >> >+ > >> > static int > >> > __set_power_wells(struct i915_power_domains *power_domains, > >> > const struct i915_power_well_desc_list *power_well_descs, > >> >@@ -1763,8 +1773,10 @@ __set_power_wells(struct i915_power_domains *power_domains, > >> > int power_well_count = 0; > >> > int plt_idx = 0; > >> > > >> >- for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) > >> >- power_well_count++; > >> >+ for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) { > >> >+ if (is_power_well_available(display, desc)) > >> >+ power_well_count++; > >> >+ } > >> > > >> > power_domains->power_well_count = power_well_count; > >> > power_domains->power_wells = > >> >@@ -1778,6 +1790,9 @@ __set_power_wells(struct i915_power_domains *power_domains, > >> > struct i915_power_well *pw = &power_domains->power_wells[plt_idx]; > >> > enum i915_power_well_id id = inst->id; > >> > > >> >+ if (!is_power_well_available(display, desc)) > >> >+ continue; > >> >+ > >> > pw->desc = desc; > >> > drm_WARN_ON(display->drm, > >> > overflows_type(inst - desc->instances->list, pw->instance_idx)); > >> >-- > >> >2.25.1 > >> > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/display: Skip unavailable power wells based on pipe mask 2025-07-18 17:17 ` Imre Deak @ 2025-07-18 20:16 ` Gustavo Sousa 2025-07-19 10:37 ` Imre Deak 0 siblings, 1 reply; 14+ messages in thread From: Gustavo Sousa @ 2025-07-18 20:16 UTC (permalink / raw) To: Imre Deak Cc: Chaitanya Kumar Borah, intel-gfx, intel-xe, dnyaneshwar.bhadane, dibin.moolakadan.subrahmanian Quoting Imre Deak (2025-07-18 14:17:09-03:00) >On Fri, Jul 18, 2025 at 01:33:26PM -0300, Gustavo Sousa wrote: >> Quoting Imre Deak (2025-07-18 12:54:11-03:00) >> >On Thu, Jul 17, 2025 at 09:02:45AM -0300, Gustavo Sousa wrote: >> >> Quoting Chaitanya Kumar Borah (2025-07-17 02:16:03-03:00) >> >> >Some power wells are only relevant for certain display pipes. Add a check >> >> >to ensure we only allocate and initialize power wells whose associated >> >> >pipes are available on the platform. >> >> > >> >> >This avoids unnecessary mapping of power wells, particularly when platforms >> >> >support a subset of pipes described in the power well descriptors. >> >> > >> >> >Suggested-by: Imre Deak <imre.deak@intel.com> >> >> >Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> >> >> >--- >> >> > .../i915/display/intel_display_power_map.c | 19 +++++++++++++++++-- >> >> > 1 file changed, 17 insertions(+), 2 deletions(-) >> >> > >> >> >diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c >> >> >index 77268802b55e..ca73e4084354 100644 >> >> >--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c >> >> >+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c >> >> >@@ -1748,6 +1748,16 @@ static void init_power_well_domains(const struct i915_power_well_instance *inst, >> >> > for_each_power_well_instance_in_desc_list((_descs)->list, (_descs)->count, \ >> >> > (_desc), (_inst)) >> >> > >> >> >+static bool >> >> >+is_power_well_available(struct intel_display *display, const struct i915_power_well_desc *desc) >> >> >+{ >> >> >+ if (desc->irq_pipe_mask && >> >> >+ !(desc->irq_pipe_mask & DISPLAY_RUNTIME_INFO(display)->pipe_mask)) >> >> >> >> According to irq_pipe_mask's documentation, that member contains a "mask >> >> of pipes whose IRQ logic is backed by the pw". I think we are >> >> overloading the meaning of that field with this logic. >> >> >> >> * Do we have guarantees that irq_pipe_mask will always be associated >> >> with the power well that powers the pipe? >> > >> >It is the case on all the platforms and so it also provides the required >> >way to identify the power well for a particular pipe. irq_pipe_mask >> >could be renamed to pipe_mask accordingly. >> >> I mean, that *exclusively* powers the pipe(s). >> >> As an example, bdw_pwdoms_display appears to be responsible not only for >> pipe B and C, but also ddi lanes and audio, for example. > >Yes, these power wells do support other functionalities as well and so >they must be registered unconditionally. pipe_mask would still be >correctly indicating that this is the power well for the pipes in the >mask; these power wells wouldn't be skipped either during registration, >since that logic must use a platform pipe power well mask vs. a >non-fused-off pipe mask. Yep. I think that works for the platforms that we have today. That said, this whole thing started because I had the impression that pipe D was fused-off and that power wells for fused-off pipes should not be touched. It turns out I was wrong in both cases: * I just got confirmation from hardware team that WCL does not have pipe D neither power well D. * As you explained in a previous reply, the driver needs to deal with power wells of fused-off pipes to ensure those get properly powered off in case whatever was controlling display before the driver takes control let them enabled. So, I guess we could either (1) go back to Chaitanya's original patch; (2) or tweak this patch to use a mask of pipes supported by the display IP instead of non-fused-off ones. I personally would prefer (1), since then we would make the presence of power wells and mapping more explicit in the code; but I wouldn't be against (2). -- Gustavo Sousa > >> >> * If the power well that has irq_pipe_mask is also used to power >> >> something else than the pipes, we could have issues if pipes in that >> >> mask are fused off. >> >> >> >> I'm leaning more toward a solution that makes POWER_DOMAIN_INIT map to >> >> POWER_DOMAIN_PIPE_* based on DISPLAY_RUNTIME_INFO(display)->pipe_mask. I >> >> have some idea of how to do that without rewriting code to use a >> >> hierarchical structure (which IMO would be ideal, but takes more >> >> effort). >> >> >> >> The idea is to, during runtime and initialization of the mapping, set >> >> the bit respective to POWER_DOMAIN_INIT in each power well that has the >> >> bit for POWER_DOMAIN_PIPE_* set for non-fused off pipes. That would >> >> also require removing the POWER_DOMAIN_INIT from the static mapping for >> >> power wells directly responsible for POWER_DOMAIN_PIPE_*. >> > >> >Power wells that don't exist on a platform shouldn't be registered in >> >the first place, so it's not enough to only remove them from the power >> >well->domain mapping, while still registering the power well. Otherwise >> >these non-existant power wells would still be accessed while disabling >> >any unused power well during driver loading/resume. Also these power >> >wells non-existant on a platform would be incorrectly listed in debugfs >> >and other state dumps. >> > >> >However, I realized that pipe power wells that do exist on a platform, >> >but for which the corresponing pipe is fused off (for instance pipe >> >A/B/C on WCL) we still need to register the power well. On some >> >platforms at least such power wells may be enabled after HW reset/by >> >BIOS and so these still need to be checked and disabled if needed during >> >driver loading/resume. I.e. instead of the above >> >> Ah, I see. Yeah, that makes sense. Thanks for the details! >> >> Well, although Bspec overview page tells that WCL's display has only >> pipes A, B and C, the page specific for power wells still lists power >> well D. So I'm wondering if WCL display just has pipe D fused off and >> the power well still exists or if power well D being listed in Bspec is >> just a documentation mistake. I'll check with the hardware team. >> >> > >> >DISPLAY_RUNTIME_INFO(display)->pipe_mask >> > >> >something like the following should be used: >> > >> >u8 pipe_pw_mask(display) >> >{ >> > if (DISPLAY_VERx100(display) == 3002) >> > return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); >> > >> > return BIT(I915_MAX_PIPES + 1) - 1; >> >} >> >> Well, if power well D does not exist indeed (i.e. not a case of pipe D >> fused-off), we need either this above or maybe go back to Chaitanya's >> original patch. >> >> I think I prefer the original patch, making the power well mapping >> explicit. >> >> -- >> Gustavo Sousa >> >> > >> >> -- >> >> Gustavo Sousa >> >> >> >> >+ return false; >> >> >+ >> >> >+ return true; >> >> >+} >> >> >+ >> >> > static int >> >> > __set_power_wells(struct i915_power_domains *power_domains, >> >> > const struct i915_power_well_desc_list *power_well_descs, >> >> >@@ -1763,8 +1773,10 @@ __set_power_wells(struct i915_power_domains *power_domains, >> >> > int power_well_count = 0; >> >> > int plt_idx = 0; >> >> > >> >> >- for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) >> >> >- power_well_count++; >> >> >+ for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) { >> >> >+ if (is_power_well_available(display, desc)) >> >> >+ power_well_count++; >> >> >+ } >> >> > >> >> > power_domains->power_well_count = power_well_count; >> >> > power_domains->power_wells = >> >> >@@ -1778,6 +1790,9 @@ __set_power_wells(struct i915_power_domains *power_domains, >> >> > struct i915_power_well *pw = &power_domains->power_wells[plt_idx]; >> >> > enum i915_power_well_id id = inst->id; >> >> > >> >> >+ if (!is_power_well_available(display, desc)) >> >> >+ continue; >> >> >+ >> >> > pw->desc = desc; >> >> > drm_WARN_ON(display->drm, >> >> > overflows_type(inst - desc->instances->list, pw->instance_idx)); >> >> >-- >> >> >2.25.1 >> >> > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/display: Skip unavailable power wells based on pipe mask 2025-07-18 20:16 ` Gustavo Sousa @ 2025-07-19 10:37 ` Imre Deak 2025-07-21 14:17 ` Gustavo Sousa 2025-07-21 15:17 ` Borah, Chaitanya Kumar 0 siblings, 2 replies; 14+ messages in thread From: Imre Deak @ 2025-07-19 10:37 UTC (permalink / raw) To: Gustavo Sousa Cc: Chaitanya Kumar Borah, intel-gfx, intel-xe, dnyaneshwar.bhadane, dibin.moolakadan.subrahmanian On Fri, Jul 18, 2025 at 05:16:20PM -0300, Gustavo Sousa wrote: > Quoting Imre Deak (2025-07-18 14:17:09-03:00) > >On Fri, Jul 18, 2025 at 01:33:26PM -0300, Gustavo Sousa wrote: > >> Quoting Imre Deak (2025-07-18 12:54:11-03:00) > >> >On Thu, Jul 17, 2025 at 09:02:45AM -0300, Gustavo Sousa wrote: > >> >> Quoting Chaitanya Kumar Borah (2025-07-17 02:16:03-03:00) > >> >> >Some power wells are only relevant for certain display pipes. Add a check > >> >> >to ensure we only allocate and initialize power wells whose associated > >> >> >pipes are available on the platform. > >> >> > > >> >> >This avoids unnecessary mapping of power wells, particularly when platforms > >> >> >support a subset of pipes described in the power well descriptors. > >> >> > > >> >> >Suggested-by: Imre Deak <imre.deak@intel.com> > >> >> >Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> > >> >> >--- > >> >> > .../i915/display/intel_display_power_map.c | 19 +++++++++++++++++-- > >> >> > 1 file changed, 17 insertions(+), 2 deletions(-) > >> >> > > >> >> >diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c > >> >> >index 77268802b55e..ca73e4084354 100644 > >> >> >--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c > >> >> >+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c > >> >> >@@ -1748,6 +1748,16 @@ static void init_power_well_domains(const struct i915_power_well_instance *inst, > >> >> > for_each_power_well_instance_in_desc_list((_descs)->list, (_descs)->count, \ > >> >> > (_desc), (_inst)) > >> >> > > >> >> >+static bool > >> >> >+is_power_well_available(struct intel_display *display, const struct i915_power_well_desc *desc) > >> >> >+{ > >> >> >+ if (desc->irq_pipe_mask && > >> >> >+ !(desc->irq_pipe_mask & DISPLAY_RUNTIME_INFO(display)->pipe_mask)) > >> >> > >> >> According to irq_pipe_mask's documentation, that member contains a "mask > >> >> of pipes whose IRQ logic is backed by the pw". I think we are > >> >> overloading the meaning of that field with this logic. > >> >> > >> >> * Do we have guarantees that irq_pipe_mask will always be associated > >> >> with the power well that powers the pipe? > >> > > >> >It is the case on all the platforms and so it also provides the required > >> >way to identify the power well for a particular pipe. irq_pipe_mask > >> >could be renamed to pipe_mask accordingly. > >> > >> I mean, that *exclusively* powers the pipe(s). > >> > >> As an example, bdw_pwdoms_display appears to be responsible not only for > >> pipe B and C, but also ddi lanes and audio, for example. > > > >Yes, these power wells do support other functionalities as well and so > >they must be registered unconditionally. pipe_mask would still be > >correctly indicating that this is the power well for the pipes in the > >mask; these power wells wouldn't be skipped either during registration, > >since that logic must use a platform pipe power well mask vs. a > >non-fused-off pipe mask. > > Yep. I think that works for the platforms that we have today. That said, > this whole thing started because I had the impression that pipe D was > fused-off and that power wells for fused-off pipes should not be > touched. > > It turns out I was wrong in both cases: > > * I just got confirmation from hardware team that WCL does not have > pipe D neither power well D. Ok, so on WCL TGL_DFSM_PIPE_D_DISABLE is always set. I wonder if it'd make sense to add an assert for this somewhere (__intel_display_device_info_runtime_init() ?), so that the assumptions on this elsewhere are always correct. Would it make sense to clarify on the power well bspec page that PW_D is not present on WCL? I presume the "Block Diagram"s, like the one at index/74286, show what pipes/DDIs are present in the IP, which may be fused off or not wired/enabled at all like DDI TC3/4, for all of which the HW power wells exist and so the driver must register a power well for them regardless of the fused state or never being wired/enabled. DDI TC3/4 are never wired on WCL, so I'd still confirm the above, i.e. do the PORT_AUX_CTL_USBC3/4 registers exist indeed (they do based on the spec) and do the 'PHY Power Request' / 'PHY Power State' flags get updated if the request bit is set/cleared as expected? > * As you explained in a previous reply, the driver needs to deal with > power wells of fused-off pipes to ensure those get properly powered > off in case whatever was controlling display before the driver takes > control let them enabled. > > So, I guess we could either > > (1) go back to Chaitanya's original patch; > (2) or tweak this patch to use a mask of pipes supported by the > display IP instead of non-fused-off ones. > > I personally would prefer (1), since then we would make the presence of > power wells and mapping more explicit in the code; Agreed, I'd also prefer (1). I'd still check if registering the AUX_TC3/4 power wells is correct based on the above. Apart from all the above, something that could be done as a follow-up: POWER_DOMAIN_INIT should be removed eventually. It was initially added to make sure that all HW blocks accessed during HW readout are powered. By now all of these accesses should get an explicit power reference, so POWER_DOMAIN_INIT isn't reqiured for that any more. The HW readout during driver loading/resume still needs to hold POWER_DOMAIN_INIT though (in intel_modeset_setup_hw_state()), because w/o that the explicit power references get/put during readout would incorrectly disable a power well inherited by the driver in the enabled state for an enabled pipe/port etc. So this needs another solution before POWER_DOMAIN_INIT could be removed. > but I wouldn't be against (2). > > -- > Gustavo Sousa > > > > >> >> * If the power well that has irq_pipe_mask is also used to power > >> >> something else than the pipes, we could have issues if pipes in that > >> >> mask are fused off. > >> >> > >> >> I'm leaning more toward a solution that makes POWER_DOMAIN_INIT map to > >> >> POWER_DOMAIN_PIPE_* based on DISPLAY_RUNTIME_INFO(display)->pipe_mask. I > >> >> have some idea of how to do that without rewriting code to use a > >> >> hierarchical structure (which IMO would be ideal, but takes more > >> >> effort). > >> >> > >> >> The idea is to, during runtime and initialization of the mapping, set > >> >> the bit respective to POWER_DOMAIN_INIT in each power well that has the > >> >> bit for POWER_DOMAIN_PIPE_* set for non-fused off pipes. That would > >> >> also require removing the POWER_DOMAIN_INIT from the static mapping for > >> >> power wells directly responsible for POWER_DOMAIN_PIPE_*. > >> > > >> >Power wells that don't exist on a platform shouldn't be registered in > >> >the first place, so it's not enough to only remove them from the power > >> >well->domain mapping, while still registering the power well. Otherwise > >> >these non-existant power wells would still be accessed while disabling > >> >any unused power well during driver loading/resume. Also these power > >> >wells non-existant on a platform would be incorrectly listed in debugfs > >> >and other state dumps. > >> > > >> >However, I realized that pipe power wells that do exist on a platform, > >> >but for which the corresponing pipe is fused off (for instance pipe > >> >A/B/C on WCL) we still need to register the power well. On some > >> >platforms at least such power wells may be enabled after HW reset/by > >> >BIOS and so these still need to be checked and disabled if needed during > >> >driver loading/resume. I.e. instead of the above > >> > >> Ah, I see. Yeah, that makes sense. Thanks for the details! > >> > >> Well, although Bspec overview page tells that WCL's display has only > >> pipes A, B and C, the page specific for power wells still lists power > >> well D. So I'm wondering if WCL display just has pipe D fused off and > >> the power well still exists or if power well D being listed in Bspec is > >> just a documentation mistake. I'll check with the hardware team. > >> > >> > > >> >DISPLAY_RUNTIME_INFO(display)->pipe_mask > >> > > >> >something like the following should be used: > >> > > >> >u8 pipe_pw_mask(display) > >> >{ > >> > if (DISPLAY_VERx100(display) == 3002) > >> > return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); > >> > > >> > return BIT(I915_MAX_PIPES + 1) - 1; > >> >} > >> > >> Well, if power well D does not exist indeed (i.e. not a case of pipe D > >> fused-off), we need either this above or maybe go back to Chaitanya's > >> original patch. > >> > >> I think I prefer the original patch, making the power well mapping > >> explicit. > >> > >> -- > >> Gustavo Sousa > >> > >> > > >> >> -- > >> >> Gustavo Sousa > >> >> > >> >> >+ return false; > >> >> >+ > >> >> >+ return true; > >> >> >+} > >> >> >+ > >> >> > static int > >> >> > __set_power_wells(struct i915_power_domains *power_domains, > >> >> > const struct i915_power_well_desc_list *power_well_descs, > >> >> >@@ -1763,8 +1773,10 @@ __set_power_wells(struct i915_power_domains *power_domains, > >> >> > int power_well_count = 0; > >> >> > int plt_idx = 0; > >> >> > > >> >> >- for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) > >> >> >- power_well_count++; > >> >> >+ for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) { > >> >> >+ if (is_power_well_available(display, desc)) > >> >> >+ power_well_count++; > >> >> >+ } > >> >> > > >> >> > power_domains->power_well_count = power_well_count; > >> >> > power_domains->power_wells = > >> >> >@@ -1778,6 +1790,9 @@ __set_power_wells(struct i915_power_domains *power_domains, > >> >> > struct i915_power_well *pw = &power_domains->power_wells[plt_idx]; > >> >> > enum i915_power_well_id id = inst->id; > >> >> > > >> >> >+ if (!is_power_well_available(display, desc)) > >> >> >+ continue; > >> >> >+ > >> >> > pw->desc = desc; > >> >> > drm_WARN_ON(display->drm, > >> >> > overflows_type(inst - desc->instances->list, pw->instance_idx)); > >> >> >-- > >> >> >2.25.1 > >> >> > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/display: Skip unavailable power wells based on pipe mask 2025-07-19 10:37 ` Imre Deak @ 2025-07-21 14:17 ` Gustavo Sousa 2025-07-21 15:17 ` Borah, Chaitanya Kumar 1 sibling, 0 replies; 14+ messages in thread From: Gustavo Sousa @ 2025-07-21 14:17 UTC (permalink / raw) To: Imre Deak Cc: Chaitanya Kumar Borah, intel-gfx, intel-xe, dnyaneshwar.bhadane, dibin.moolakadan.subrahmanian Quoting Imre Deak (2025-07-19 07:37:56-03:00) >On Fri, Jul 18, 2025 at 05:16:20PM -0300, Gustavo Sousa wrote: >> Quoting Imre Deak (2025-07-18 14:17:09-03:00) >> >On Fri, Jul 18, 2025 at 01:33:26PM -0300, Gustavo Sousa wrote: >> >> Quoting Imre Deak (2025-07-18 12:54:11-03:00) >> >> >On Thu, Jul 17, 2025 at 09:02:45AM -0300, Gustavo Sousa wrote: >> >> >> Quoting Chaitanya Kumar Borah (2025-07-17 02:16:03-03:00) >> >> >> >Some power wells are only relevant for certain display pipes. Add a check >> >> >> >to ensure we only allocate and initialize power wells whose associated >> >> >> >pipes are available on the platform. >> >> >> > >> >> >> >This avoids unnecessary mapping of power wells, particularly when platforms >> >> >> >support a subset of pipes described in the power well descriptors. >> >> >> > >> >> >> >Suggested-by: Imre Deak <imre.deak@intel.com> >> >> >> >Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> >> >> >> >--- >> >> >> > .../i915/display/intel_display_power_map.c | 19 +++++++++++++++++-- >> >> >> > 1 file changed, 17 insertions(+), 2 deletions(-) >> >> >> > >> >> >> >diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c >> >> >> >index 77268802b55e..ca73e4084354 100644 >> >> >> >--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c >> >> >> >+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c >> >> >> >@@ -1748,6 +1748,16 @@ static void init_power_well_domains(const struct i915_power_well_instance *inst, >> >> >> > for_each_power_well_instance_in_desc_list((_descs)->list, (_descs)->count, \ >> >> >> > (_desc), (_inst)) >> >> >> > >> >> >> >+static bool >> >> >> >+is_power_well_available(struct intel_display *display, const struct i915_power_well_desc *desc) >> >> >> >+{ >> >> >> >+ if (desc->irq_pipe_mask && >> >> >> >+ !(desc->irq_pipe_mask & DISPLAY_RUNTIME_INFO(display)->pipe_mask)) >> >> >> >> >> >> According to irq_pipe_mask's documentation, that member contains a "mask >> >> >> of pipes whose IRQ logic is backed by the pw". I think we are >> >> >> overloading the meaning of that field with this logic. >> >> >> >> >> >> * Do we have guarantees that irq_pipe_mask will always be associated >> >> >> with the power well that powers the pipe? >> >> > >> >> >It is the case on all the platforms and so it also provides the required >> >> >way to identify the power well for a particular pipe. irq_pipe_mask >> >> >could be renamed to pipe_mask accordingly. >> >> >> >> I mean, that *exclusively* powers the pipe(s). >> >> >> >> As an example, bdw_pwdoms_display appears to be responsible not only for >> >> pipe B and C, but also ddi lanes and audio, for example. >> > >> >Yes, these power wells do support other functionalities as well and so >> >they must be registered unconditionally. pipe_mask would still be >> >correctly indicating that this is the power well for the pipes in the >> >mask; these power wells wouldn't be skipped either during registration, >> >since that logic must use a platform pipe power well mask vs. a >> >non-fused-off pipe mask. >> >> Yep. I think that works for the platforms that we have today. That said, >> this whole thing started because I had the impression that pipe D was >> fused-off and that power wells for fused-off pipes should not be >> touched. >> >> It turns out I was wrong in both cases: >> >> * I just got confirmation from hardware team that WCL does not have >> pipe D neither power well D. > >Ok, so on WCL TGL_DFSM_PIPE_D_DISABLE is always set. I wonder if it'd >make sense to add an assert for this somewhere >(__intel_display_device_info_runtime_init() ?), so that the assumptions >on this elsewhere are always correct. Hm. Not sure. I'm thinking of a different approach. According to Bspec, a pipe's "*_DFSM_PIPE_*_DISABLE" bit mean that the pipe capability has been disabled. That brings brings the assumption that the capability is there in the hardware. So, I'm wondering if the respective "*_DFSM_PIPE_*_DISABLE" bit for a pipe that does not exist in the display IP should rather be treated as "don't care", that is, only trust that bit if we know the display IP has the respective pipe. In both cases (assert suggestion vs what I just wrote above), I think we would need to map display version 30.02 to a new struct intel_display_device_info that has the correct __runtime_defaults.pipe_mask. -- Gustavo Sousa > >Would it make sense to clarify on the power well bspec page that PW_D is >not present on WCL? > >I presume the "Block Diagram"s, like the one at index/74286, show what >pipes/DDIs are present in the IP, which may be fused off or not >wired/enabled at all like DDI TC3/4, for all of which the HW power wells >exist and so the driver must register a power well for them regardless >of the fused state or never being wired/enabled. > >DDI TC3/4 are never wired on WCL, so I'd still confirm the above, i.e. >do the PORT_AUX_CTL_USBC3/4 registers exist indeed (they do based on the >spec) and do the 'PHY Power Request' / 'PHY Power State' flags get >updated if the request bit is set/cleared as expected? > >> * As you explained in a previous reply, the driver needs to deal with >> power wells of fused-off pipes to ensure those get properly powered >> off in case whatever was controlling display before the driver takes >> control let them enabled. >> >> So, I guess we could either >> >> (1) go back to Chaitanya's original patch; >> (2) or tweak this patch to use a mask of pipes supported by the >> display IP instead of non-fused-off ones. >> >> I personally would prefer (1), since then we would make the presence of >> power wells and mapping more explicit in the code; > >Agreed, I'd also prefer (1). I'd still check if registering the >AUX_TC3/4 power wells is correct based on the above. > >Apart from all the above, something that could be done as a follow-up: >POWER_DOMAIN_INIT should be removed eventually. It was initially added >to make sure that all HW blocks accessed during HW readout are powered. >By now all of these accesses should get an explicit power reference, so >POWER_DOMAIN_INIT isn't reqiured for that any more. > >The HW readout during driver loading/resume still needs to hold >POWER_DOMAIN_INIT though (in intel_modeset_setup_hw_state()), because >w/o that the explicit power references get/put during readout would >incorrectly disable a power well inherited by the driver in the enabled >state for an enabled pipe/port etc. So this needs another solution >before POWER_DOMAIN_INIT could be removed. > >> but I wouldn't be against (2). >> >> -- >> Gustavo Sousa >> >> > >> >> >> * If the power well that has irq_pipe_mask is also used to power >> >> >> something else than the pipes, we could have issues if pipes in that >> >> >> mask are fused off. >> >> >> >> >> >> I'm leaning more toward a solution that makes POWER_DOMAIN_INIT map to >> >> >> POWER_DOMAIN_PIPE_* based on DISPLAY_RUNTIME_INFO(display)->pipe_mask. I >> >> >> have some idea of how to do that without rewriting code to use a >> >> >> hierarchical structure (which IMO would be ideal, but takes more >> >> >> effort). >> >> >> >> >> >> The idea is to, during runtime and initialization of the mapping, set >> >> >> the bit respective to POWER_DOMAIN_INIT in each power well that has the >> >> >> bit for POWER_DOMAIN_PIPE_* set for non-fused off pipes. That would >> >> >> also require removing the POWER_DOMAIN_INIT from the static mapping for >> >> >> power wells directly responsible for POWER_DOMAIN_PIPE_*. >> >> > >> >> >Power wells that don't exist on a platform shouldn't be registered in >> >> >the first place, so it's not enough to only remove them from the power >> >> >well->domain mapping, while still registering the power well. Otherwise >> >> >these non-existant power wells would still be accessed while disabling >> >> >any unused power well during driver loading/resume. Also these power >> >> >wells non-existant on a platform would be incorrectly listed in debugfs >> >> >and other state dumps. >> >> > >> >> >However, I realized that pipe power wells that do exist on a platform, >> >> >but for which the corresponing pipe is fused off (for instance pipe >> >> >A/B/C on WCL) we still need to register the power well. On some >> >> >platforms at least such power wells may be enabled after HW reset/by >> >> >BIOS and so these still need to be checked and disabled if needed during >> >> >driver loading/resume. I.e. instead of the above >> >> >> >> Ah, I see. Yeah, that makes sense. Thanks for the details! >> >> >> >> Well, although Bspec overview page tells that WCL's display has only >> >> pipes A, B and C, the page specific for power wells still lists power >> >> well D. So I'm wondering if WCL display just has pipe D fused off and >> >> the power well still exists or if power well D being listed in Bspec is >> >> just a documentation mistake. I'll check with the hardware team. >> >> >> >> > >> >> >DISPLAY_RUNTIME_INFO(display)->pipe_mask >> >> > >> >> >something like the following should be used: >> >> > >> >> >u8 pipe_pw_mask(display) >> >> >{ >> >> > if (DISPLAY_VERx100(display) == 3002) >> >> > return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); >> >> > >> >> > return BIT(I915_MAX_PIPES + 1) - 1; >> >> >} >> >> >> >> Well, if power well D does not exist indeed (i.e. not a case of pipe D >> >> fused-off), we need either this above or maybe go back to Chaitanya's >> >> original patch. >> >> >> >> I think I prefer the original patch, making the power well mapping >> >> explicit. >> >> >> >> -- >> >> Gustavo Sousa >> >> >> >> > >> >> >> -- >> >> >> Gustavo Sousa >> >> >> >> >> >> >+ return false; >> >> >> >+ >> >> >> >+ return true; >> >> >> >+} >> >> >> >+ >> >> >> > static int >> >> >> > __set_power_wells(struct i915_power_domains *power_domains, >> >> >> > const struct i915_power_well_desc_list *power_well_descs, >> >> >> >@@ -1763,8 +1773,10 @@ __set_power_wells(struct i915_power_domains *power_domains, >> >> >> > int power_well_count = 0; >> >> >> > int plt_idx = 0; >> >> >> > >> >> >> >- for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) >> >> >> >- power_well_count++; >> >> >> >+ for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) { >> >> >> >+ if (is_power_well_available(display, desc)) >> >> >> >+ power_well_count++; >> >> >> >+ } >> >> >> > >> >> >> > power_domains->power_well_count = power_well_count; >> >> >> > power_domains->power_wells = >> >> >> >@@ -1778,6 +1790,9 @@ __set_power_wells(struct i915_power_domains *power_domains, >> >> >> > struct i915_power_well *pw = &power_domains->power_wells[plt_idx]; >> >> >> > enum i915_power_well_id id = inst->id; >> >> >> > >> >> >> >+ if (!is_power_well_available(display, desc)) >> >> >> >+ continue; >> >> >> >+ >> >> >> > pw->desc = desc; >> >> >> > drm_WARN_ON(display->drm, >> >> >> > overflows_type(inst - desc->instances->list, pw->instance_idx)); >> >> >> >-- >> >> >> >2.25.1 >> >> >> > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/display: Skip unavailable power wells based on pipe mask 2025-07-19 10:37 ` Imre Deak 2025-07-21 14:17 ` Gustavo Sousa @ 2025-07-21 15:17 ` Borah, Chaitanya Kumar 2025-07-21 16:21 ` Imre Deak 1 sibling, 1 reply; 14+ messages in thread From: Borah, Chaitanya Kumar @ 2025-07-21 15:17 UTC (permalink / raw) To: imre.deak, Gustavo Sousa Cc: intel-gfx, intel-xe, dnyaneshwar.bhadane, dibin.moolakadan.subrahmanian On 7/19/2025 4:07 PM, Imre Deak wrote: > On Fri, Jul 18, 2025 at 05:16:20PM -0300, Gustavo Sousa wrote: > ... > > DDI TC3/4 are never wired on WCL, so I'd still confirm the above, i.e. > do the PORT_AUX_CTL_USBC3/4 registers exist indeed (they do based on the > spec) and do the 'PHY Power Request' / 'PHY Power State' flags get > updated if the request bit is set/cleared as expected? > >> * As you explained in a previous reply, the driver needs to deal with >> power wells of fused-off pipes to ensure those get properly powered >> off in case whatever was controlling display before the driver takes >> control let them enabled. >> >> So, I guess we could either >> >> (1) go back to Chaitanya's original patch; >> (2) or tweak this patch to use a mask of pipes supported by the >> display IP instead of non-fused-off ones. >> >> I personally would prefer (1), since then we would make the presence of >> power wells and mapping more explicit in the code; > Agreed, I'd also prefer (1). I'd still check if registering the > AUX_TC3/4 power wells is correct based on the above. > I had a version of my first patch that excluded AUX_TC3/4. That lead to the following warning. I need to dig deeper to understand the failure but it might be more obvious to one of you. At the time I just assumed that these power wells are actually present. [ 4.223342] ------------[ cut here ]------------ [ 4.223343] xe 0000:00:02.0: [drm] drm_WARN_ON(aux_powered) [ 4.223367] WARNING: CPU: 0 PID: 145 at drivers/gpu/drm/i915/display/intel_tc.c:1447 intel_tc_port_reset_mode+0x135/0x350 [xe] [ 4.223583] Modules linked in: xe(+) drm_ttm_helper ttm drm_suballoc_helper cec rc_core drm_buddy gpu_sched drm_gpuvm drm_exec drm_gpusvm drm_display_helper mac_hid video wmi pinctrl_intel_platform pinctrl_intel pwm_lpss ... [ 4.223801] Call Trace: [ 4.223803] <TASK> [ 4.223806] __intel_tc_port_lock+0xdf/0x130 [xe] [ 4.223943] intel_tc_port_lock+0x1e/0x30 [xe] [ 4.224062] intel_digital_port_connected+0x33/0xa0 [xe] [ 4.224258] intel_dp_detect+0xef/0x860 [xe] [ 4.224474] ? ww_mutex_lock+0xfd/0x110 [ 4.224482] detect_connector_status+0x1e/0x50 [ 4.224490] drm_helper_probe_detect+0x4b/0x80 [ 4.224495] drm_helper_probe_single_connector_modes+0x3f4/0x680 [ 4.224502] drm_client_modeset_probe+0x251/0x1a40 [ 4.224506] ? kmem_cache_alloc_lru_noprof+0x2cd/0x3b0 [ 4.224512] ? __d_alloc+0x2e/0x1f0 [ 4.224519] ? __kmalloc_node_track_caller_noprof+0x347/0x4c0 [ 4.224524] __drm_fb_helper_initial_config_and_unlock+0x3e/0x560 [ 4.224529] ? kstrdup+0x3c/0x70 [ 4.224533] ? kstrdup+0x52/0x70 [ 4.224536] drm_fb_helper_initial_config+0x36/0x40 [ 4.224540] drm_fbdev_client_hotplug+0x76/0xc0 [ 4.224543] drm_client_register+0x68/0xb0 [ 4.224549] drm_fbdev_client_setup+0xe8/0x1d0 [ 4.224552] drm_client_setup+0x5b/0x80 [ 4.224555] drm_client_setup_with_color_mode+0x29/0x40 [ 4.224557] intel_fbdev_setup+0x20f/0x4c0 [xe] [ 4.224699] intel_display_driver_register+0xb9/0x100 [xe] [ 4.224905] ? __pfx___drm_printfn_dbg+0x10/0x10 [ 4.224909] ? intel_display_driver_register+0x32/0x100 [xe] [ 4.225108] xe_display_register+0x2c/0x40 [xe] [ 4.225321] xe_device_probe+0x4af/0x580 [xe] [ 4.225467] xe_pci_probe+0x9a2/0xcd0 [xe] [ 4.225653] local_pci_probe+0x4c/0xb0 [ 4.225657] pci_device_probe+0xdb/0x230 [ 4.225660] really_probe+0xe2/0x390 [ 4.225665] __driver_probe_device+0x7e/0x160 [ 4.225669] driver_probe_device+0x23/0xa0 [ 4.225673] __driver_attach+0xe8/0x1e0 [ 4.225677] ? __pfx___driver_attach+0x10/0x10 [ 4.225681] bus_for_each_dev+0x7d/0xd0 [ 4.225684] driver_attach+0x22/0x30 [ 4.225687] bus_add_driver+0x118/0x240 [ 4.225691] driver_register+0x68/0x130 [ 4.225695] __pci_register_driver+0x65/0x70 [ 4.225697] xe_register_pci_driver+0x27/0x30 [xe] [ 4.225875] xe_init+0x35/0x90 [xe] [ 4.226005] ? __pfx_xe_init+0x10/0x10 [xe] [ 4.226131] do_one_initcall+0x49/0x330 [ 4.226137] do_init_module+0x6a/0x2a0 [ 4.226141] load_module+0x21e6/0x22b0 [ 4.226145] ? kernel_read_file+0x240/0x2c0 [ 4.226150] init_module_from_file+0x9b/0xe0 [ 4.226153] ? init_module_from_file+0x9b/0xe0 [ 4.226156] idempotent_init_module+0x170/0x270 [ 4.226159] __x64_sys_finit_module+0x6f/0xe0 [ 4.226162] x64_sys_call+0x1b7a/0x2150 [ 4.226165] do_syscall_64+0x56/0x860 [ 4.226169] entry_SYSCALL_64_after_hwframe+0x76/0x7e [ 4.226172] RIP: 0033:0x7fab2003b25d ... [ 4.226190] ---[ end trace 0000000000000000 ]--- - Chaitanya > >> but I wouldn't be against (2). >> >> -- >> Gustavo Sousa >> >>>>>> * If the power well that has irq_pipe_mask is also used to power >>>>>> something else than the pipes, we could have issues if pipes in that >>>>>> mask are fused off. >>>>>> >>>>>> I'm leaning more toward a solution that makes POWER_DOMAIN_INIT map to >>>>>> POWER_DOMAIN_PIPE_* based on DISPLAY_RUNTIME_INFO(display)->pipe_mask. I >>>>>> have some idea of how to do that without rewriting code to use a >>>>>> hierarchical structure (which IMO would be ideal, but takes more >>>>>> effort). >>>>>> >>>>>> The idea is to, during runtime and initialization of the mapping, set >>>>>> the bit respective to POWER_DOMAIN_INIT in each power well that has the >>>>>> bit for POWER_DOMAIN_PIPE_* set for non-fused off pipes. That would >>>>>> also require removing the POWER_DOMAIN_INIT from the static mapping for >>>>>> power wells directly responsible for POWER_DOMAIN_PIPE_*. >>>>> Power wells that don't exist on a platform shouldn't be registered in >>>>> the first place, so it's not enough to only remove them from the power >>>>> well->domain mapping, while still registering the power well. Otherwise >>>>> these non-existant power wells would still be accessed while disabling >>>>> any unused power well during driver loading/resume. Also these power >>>>> wells non-existant on a platform would be incorrectly listed in debugfs >>>>> and other state dumps. >>>>> >>>>> However, I realized that pipe power wells that do exist on a platform, >>>>> but for which the corresponing pipe is fused off (for instance pipe >>>>> A/B/C on WCL) we still need to register the power well. On some >>>>> platforms at least such power wells may be enabled after HW reset/by >>>>> BIOS and so these still need to be checked and disabled if needed during >>>>> driver loading/resume. I.e. instead of the above >>>> Ah, I see. Yeah, that makes sense. Thanks for the details! >>>> >>>> Well, although Bspec overview page tells that WCL's display has only >>>> pipes A, B and C, the page specific for power wells still lists power >>>> well D. So I'm wondering if WCL display just has pipe D fused off and >>>> the power well still exists or if power well D being listed in Bspec is >>>> just a documentation mistake. I'll check with the hardware team. >>>> >>>>> DISPLAY_RUNTIME_INFO(display)->pipe_mask >>>>> >>>>> something like the following should be used: >>>>> >>>>> u8 pipe_pw_mask(display) >>>>> { >>>>> if (DISPLAY_VERx100(display) == 3002) >>>>> return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); >>>>> >>>>> return BIT(I915_MAX_PIPES + 1) - 1; >>>>> } >>>> Well, if power well D does not exist indeed (i.e. not a case of pipe D >>>> fused-off), we need either this above or maybe go back to Chaitanya's >>>> original patch. >>>> >>>> I think I prefer the original patch, making the power well mapping >>>> explicit. >>>> >>>> -- >>>> Gustavo Sousa >>>> >>>>>> -- >>>>>> Gustavo Sousa >>>>>> >>>>>>> + return false; >>>>>>> + >>>>>>> + return true; >>>>>>> +} >>>>>>> + >>>>>>> static int >>>>>>> __set_power_wells(struct i915_power_domains *power_domains, >>>>>>> const struct i915_power_well_desc_list *power_well_descs, >>>>>>> @@ -1763,8 +1773,10 @@ __set_power_wells(struct i915_power_domains *power_domains, >>>>>>> int power_well_count = 0; >>>>>>> int plt_idx = 0; >>>>>>> >>>>>>> - for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) >>>>>>> - power_well_count++; >>>>>>> + for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) { >>>>>>> + if (is_power_well_available(display, desc)) >>>>>>> + power_well_count++; >>>>>>> + } >>>>>>> >>>>>>> power_domains->power_well_count = power_well_count; >>>>>>> power_domains->power_wells = >>>>>>> @@ -1778,6 +1790,9 @@ __set_power_wells(struct i915_power_domains *power_domains, >>>>>>> struct i915_power_well *pw = &power_domains->power_wells[plt_idx]; >>>>>>> enum i915_power_well_id id = inst->id; >>>>>>> >>>>>>> + if (!is_power_well_available(display, desc)) >>>>>>> + continue; >>>>>>> + >>>>>>> pw->desc = desc; >>>>>>> drm_WARN_ON(display->drm, >>>>>>> overflows_type(inst - desc->instances->list, pw->instance_idx)); >>>>>>> -- >>>>>>> 2.25.1 >>>>>>> ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/display: Skip unavailable power wells based on pipe mask 2025-07-21 15:17 ` Borah, Chaitanya Kumar @ 2025-07-21 16:21 ` Imre Deak 0 siblings, 0 replies; 14+ messages in thread From: Imre Deak @ 2025-07-21 16:21 UTC (permalink / raw) To: Borah, Chaitanya Kumar Cc: Gustavo Sousa, intel-gfx, intel-xe, dnyaneshwar.bhadane, dibin.moolakadan.subrahmanian On Mon, Jul 21, 2025 at 08:47:56PM +0530, Borah, Chaitanya Kumar wrote: > > On 7/19/2025 4:07 PM, Imre Deak wrote: > > On Fri, Jul 18, 2025 at 05:16:20PM -0300, Gustavo Sousa wrote: > > ... > > > > DDI TC3/4 are never wired on WCL, so I'd still confirm the above, i.e. > > do the PORT_AUX_CTL_USBC3/4 registers exist indeed (they do based on the > > spec) and do the 'PHY Power Request' / 'PHY Power State' flags get > > updated if the request bit is set/cleared as expected? > > > > > * As you explained in a previous reply, the driver needs to deal with > > > power wells of fused-off pipes to ensure those get properly powered > > > off in case whatever was controlling display before the driver takes > > > control let them enabled. > > > > > > So, I guess we could either > > > > > > (1) go back to Chaitanya's original patch; > > > (2) or tweak this patch to use a mask of pipes supported by the > > > display IP instead of non-fused-off ones. > > > > > > I personally would prefer (1), since then we would make the presence of > > > power wells and mapping more explicit in the code; > > Agreed, I'd also prefer (1). I'd still check if registering the > > AUX_TC3/4 power wells is correct based on the above. > > > I had a version of my first patch that excluded AUX_TC3/4. > > That lead to the following warning. I need to dig deeper to understand the > failure but it might be more obvious to one of you. > At the time I just assumed that these power wells are actually present. Is the connector for the TC3/4 ports get added? That would be incorrect, as WCL doesn't have these ports. The VBT on WCL should indicate only TC1/2 as present, but if the above is true that's probably not the case. Please provide a full dmesg. Regardless of the above, could you please check what happens with the above PHY power request/state flags if you set the request flag to 1 in the PORT_AUX_CTL_USBC3/4 registers? > > [ 4.223342] ------------[ cut here ]------------ > [ 4.223343] xe 0000:00:02.0: [drm] drm_WARN_ON(aux_powered) > [ 4.223367] WARNING: CPU: 0 PID: 145 at > drivers/gpu/drm/i915/display/intel_tc.c:1447 > intel_tc_port_reset_mode+0x135/0x350 [xe] > [ 4.223583] Modules linked in: xe(+) drm_ttm_helper ttm > drm_suballoc_helper cec rc_core drm_buddy gpu_sched drm_gpuvm drm_exec > drm_gpusvm drm_display_helper mac_hid video wmi pinctrl_intel_platform > pinctrl_intel pwm_lpss > ... > [ 4.223801] Call Trace: > [ 4.223803] <TASK> > [ 4.223806] __intel_tc_port_lock+0xdf/0x130 [xe] > [ 4.223943] intel_tc_port_lock+0x1e/0x30 [xe] > [ 4.224062] intel_digital_port_connected+0x33/0xa0 [xe] > [ 4.224258] intel_dp_detect+0xef/0x860 [xe] > [ 4.224474] ? ww_mutex_lock+0xfd/0x110 > [ 4.224482] detect_connector_status+0x1e/0x50 > [ 4.224490] drm_helper_probe_detect+0x4b/0x80 > [ 4.224495] drm_helper_probe_single_connector_modes+0x3f4/0x680 > [ 4.224502] drm_client_modeset_probe+0x251/0x1a40 > [ 4.224506] ? kmem_cache_alloc_lru_noprof+0x2cd/0x3b0 > [ 4.224512] ? __d_alloc+0x2e/0x1f0 > [ 4.224519] ? __kmalloc_node_track_caller_noprof+0x347/0x4c0 > [ 4.224524] __drm_fb_helper_initial_config_and_unlock+0x3e/0x560 > [ 4.224529] ? kstrdup+0x3c/0x70 > [ 4.224533] ? kstrdup+0x52/0x70 > [ 4.224536] drm_fb_helper_initial_config+0x36/0x40 > [ 4.224540] drm_fbdev_client_hotplug+0x76/0xc0 > [ 4.224543] drm_client_register+0x68/0xb0 > [ 4.224549] drm_fbdev_client_setup+0xe8/0x1d0 > [ 4.224552] drm_client_setup+0x5b/0x80 > [ 4.224555] drm_client_setup_with_color_mode+0x29/0x40 > [ 4.224557] intel_fbdev_setup+0x20f/0x4c0 [xe] > [ 4.224699] intel_display_driver_register+0xb9/0x100 [xe] > [ 4.224905] ? __pfx___drm_printfn_dbg+0x10/0x10 > [ 4.224909] ? intel_display_driver_register+0x32/0x100 [xe] > [ 4.225108] xe_display_register+0x2c/0x40 [xe] > [ 4.225321] xe_device_probe+0x4af/0x580 [xe] > [ 4.225467] xe_pci_probe+0x9a2/0xcd0 [xe] > [ 4.225653] local_pci_probe+0x4c/0xb0 > [ 4.225657] pci_device_probe+0xdb/0x230 > [ 4.225660] really_probe+0xe2/0x390 > [ 4.225665] __driver_probe_device+0x7e/0x160 > [ 4.225669] driver_probe_device+0x23/0xa0 > [ 4.225673] __driver_attach+0xe8/0x1e0 > [ 4.225677] ? __pfx___driver_attach+0x10/0x10 > [ 4.225681] bus_for_each_dev+0x7d/0xd0 > [ 4.225684] driver_attach+0x22/0x30 > [ 4.225687] bus_add_driver+0x118/0x240 > [ 4.225691] driver_register+0x68/0x130 > [ 4.225695] __pci_register_driver+0x65/0x70 > [ 4.225697] xe_register_pci_driver+0x27/0x30 [xe] > [ 4.225875] xe_init+0x35/0x90 [xe] > [ 4.226005] ? __pfx_xe_init+0x10/0x10 [xe] > [ 4.226131] do_one_initcall+0x49/0x330 > [ 4.226137] do_init_module+0x6a/0x2a0 > [ 4.226141] load_module+0x21e6/0x22b0 > [ 4.226145] ? kernel_read_file+0x240/0x2c0 > [ 4.226150] init_module_from_file+0x9b/0xe0 > [ 4.226153] ? init_module_from_file+0x9b/0xe0 > [ 4.226156] idempotent_init_module+0x170/0x270 > [ 4.226159] __x64_sys_finit_module+0x6f/0xe0 > [ 4.226162] x64_sys_call+0x1b7a/0x2150 > [ 4.226165] do_syscall_64+0x56/0x860 > [ 4.226169] entry_SYSCALL_64_after_hwframe+0x76/0x7e > [ 4.226172] RIP: 0033:0x7fab2003b25d > ... > [ 4.226190] ---[ end trace 0000000000000000 ]--- > > - Chaitanya > > > > > > but I wouldn't be against (2). > > > > > > -- > > > Gustavo Sousa > > > > > > > > > > * If the power well that has irq_pipe_mask is also used to power > > > > > > > something else than the pipes, we could have issues if pipes in that > > > > > > > mask are fused off. > > > > > > > > > > > > > > I'm leaning more toward a solution that makes POWER_DOMAIN_INIT map to > > > > > > > POWER_DOMAIN_PIPE_* based on DISPLAY_RUNTIME_INFO(display)->pipe_mask. I > > > > > > > have some idea of how to do that without rewriting code to use a > > > > > > > hierarchical structure (which IMO would be ideal, but takes more > > > > > > > effort). > > > > > > > > > > > > > > The idea is to, during runtime and initialization of the mapping, set > > > > > > > the bit respective to POWER_DOMAIN_INIT in each power well that has the > > > > > > > bit for POWER_DOMAIN_PIPE_* set for non-fused off pipes. That would > > > > > > > also require removing the POWER_DOMAIN_INIT from the static mapping for > > > > > > > power wells directly responsible for POWER_DOMAIN_PIPE_*. > > > > > > Power wells that don't exist on a platform shouldn't be registered in > > > > > > the first place, so it's not enough to only remove them from the power > > > > > > well->domain mapping, while still registering the power well. Otherwise > > > > > > these non-existant power wells would still be accessed while disabling > > > > > > any unused power well during driver loading/resume. Also these power > > > > > > wells non-existant on a platform would be incorrectly listed in debugfs > > > > > > and other state dumps. > > > > > > > > > > > > However, I realized that pipe power wells that do exist on a platform, > > > > > > but for which the corresponing pipe is fused off (for instance pipe > > > > > > A/B/C on WCL) we still need to register the power well. On some > > > > > > platforms at least such power wells may be enabled after HW reset/by > > > > > > BIOS and so these still need to be checked and disabled if needed during > > > > > > driver loading/resume. I.e. instead of the above > > > > > Ah, I see. Yeah, that makes sense. Thanks for the details! > > > > > > > > > > Well, although Bspec overview page tells that WCL's display has only > > > > > pipes A, B and C, the page specific for power wells still lists power > > > > > well D. So I'm wondering if WCL display just has pipe D fused off and > > > > > the power well still exists or if power well D being listed in Bspec is > > > > > just a documentation mistake. I'll check with the hardware team. > > > > > > > > > > > DISPLAY_RUNTIME_INFO(display)->pipe_mask > > > > > > > > > > > > something like the following should be used: > > > > > > > > > > > > u8 pipe_pw_mask(display) > > > > > > { > > > > > > if (DISPLAY_VERx100(display) == 3002) > > > > > > return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); > > > > > > > > > > > > return BIT(I915_MAX_PIPES + 1) - 1; > > > > > > } > > > > > Well, if power well D does not exist indeed (i.e. not a case of pipe D > > > > > fused-off), we need either this above or maybe go back to Chaitanya's > > > > > original patch. > > > > > > > > > > I think I prefer the original patch, making the power well mapping > > > > > explicit. > > > > > > > > > > -- > > > > > Gustavo Sousa > > > > > > > > > > > > -- > > > > > > > Gustavo Sousa > > > > > > > > > > > > > > > + return false; > > > > > > > > + > > > > > > > > + return true; > > > > > > > > +} > > > > > > > > + > > > > > > > > static int > > > > > > > > __set_power_wells(struct i915_power_domains *power_domains, > > > > > > > > const struct i915_power_well_desc_list *power_well_descs, > > > > > > > > @@ -1763,8 +1773,10 @@ __set_power_wells(struct i915_power_domains *power_domains, > > > > > > > > int power_well_count = 0; > > > > > > > > int plt_idx = 0; > > > > > > > > > > > > > > > > - for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) > > > > > > > > - power_well_count++; > > > > > > > > + for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) { > > > > > > > > + if (is_power_well_available(display, desc)) > > > > > > > > + power_well_count++; > > > > > > > > + } > > > > > > > > > > > > > > > > power_domains->power_well_count = power_well_count; > > > > > > > > power_domains->power_wells = > > > > > > > > @@ -1778,6 +1790,9 @@ __set_power_wells(struct i915_power_domains *power_domains, > > > > > > > > struct i915_power_well *pw = &power_domains->power_wells[plt_idx]; > > > > > > > > enum i915_power_well_id id = inst->id; > > > > > > > > > > > > > > > > + if (!is_power_well_available(display, desc)) > > > > > > > > + continue; > > > > > > > > + > > > > > > > > pw->desc = desc; > > > > > > > > drm_WARN_ON(display->drm, > > > > > > > > overflows_type(inst - desc->instances->list, pw->instance_idx)); > > > > > > > > -- > > > > > > > > 2.25.1 > > > > > > > > ^ permalink raw reply [flat|nested] 14+ messages in thread
* ✗ Xe.CI.Full: failure for drm/i915/display: Skip unavailable power wells based on pipe mask 2025-07-17 5:16 [PATCH] drm/i915/display: Skip unavailable power wells based on pipe mask Chaitanya Kumar Borah ` (3 preceding siblings ...) 2025-07-17 12:02 ` [PATCH] " Gustavo Sousa @ 2025-07-18 8:46 ` Patchwork 4 siblings, 0 replies; 14+ messages in thread From: Patchwork @ 2025-07-18 8:46 UTC (permalink / raw) To: Chaitanya Kumar Borah; +Cc: intel-xe [-- Attachment #1: Type: text/plain, Size: 41204 bytes --] == Series Details == Series: drm/i915/display: Skip unavailable power wells based on pipe mask URL : https://patchwork.freedesktop.org/series/151737/ State : failure == Summary == CI Bug Log - changes from xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331_FULL -> xe-pw-151737v1_FULL ==================================================== Summary ------- **WARNING** Minor unknown changes coming with xe-pw-151737v1_FULL need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in xe-pw-151737v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (4 -> 4) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in xe-pw-151737v1_FULL: ### IGT changes ### #### Warnings #### * igt@xe_pm@d3cold-basic-exec: - shard-adlp: [SKIP][1] ([Intel XE#2284] / [Intel XE#366]) -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-8/igt@xe_pm@d3cold-basic-exec.html [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-adlp-8/igt@xe_pm@d3cold-basic-exec.html Known issues ------------ Here are the changes found in xe-pw-151737v1_FULL that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_big_fb@x-tiled-64bpp-rotate-90: - shard-dg2-set2: NOTRUN -> [SKIP][3] ([Intel XE#316]) +1 other test skip [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-436/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip: - shard-adlp: [PASS][4] -> [DMESG-FAIL][5] ([Intel XE#4543]) [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-adlp-3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html * igt@kms_big_fb@yf-tiled-64bpp-rotate-270: - shard-dg2-set2: NOTRUN -> [SKIP][6] ([Intel XE#1124]) [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-432/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html * igt@kms_big_fb@yf-tiled-8bpp-rotate-180: - shard-bmg: NOTRUN -> [SKIP][7] ([Intel XE#1124]) +1 other test skip [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@kms_big_fb@yf-tiled-8bpp-rotate-180.html * igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p: - shard-dg2-set2: NOTRUN -> [SKIP][8] ([Intel XE#2191]) [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-436/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html * igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p: - shard-bmg: NOTRUN -> [SKIP][9] ([Intel XE#2314] / [Intel XE#2894]) [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-6: - shard-dg2-set2: NOTRUN -> [SKIP][10] ([Intel XE#787]) +111 other tests skip [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-433/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-6.html * igt@kms_ccs@crc-primary-basic-y-tiled-ccs: - shard-bmg: NOTRUN -> [SKIP][11] ([Intel XE#2887]) +2 other tests skip [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@kms_ccs@crc-primary-basic-y-tiled-ccs.html * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs: - shard-dg2-set2: NOTRUN -> [SKIP][12] ([Intel XE#2907]) [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-432/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs: - shard-dg2-set2: NOTRUN -> [SKIP][13] ([Intel XE#455] / [Intel XE#787]) +20 other tests skip [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-436/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs.html * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2: - shard-bmg: NOTRUN -> [SKIP][14] ([Intel XE#2652] / [Intel XE#787]) +12 other tests skip [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-8/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2.html * igt@kms_chamelium_color@ctm-limited-range: - shard-bmg: NOTRUN -> [SKIP][15] ([Intel XE#2325]) [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@kms_chamelium_color@ctm-limited-range.html * igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k: - shard-bmg: NOTRUN -> [SKIP][16] ([Intel XE#2252]) +1 other test skip [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html * igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode: - shard-dg2-set2: NOTRUN -> [SKIP][17] ([Intel XE#373]) +4 other tests skip [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-436/igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode.html * igt@kms_content_protection@lic-type-0@pipe-a-dp-2: - shard-bmg: NOTRUN -> [FAIL][18] ([Intel XE#1178]) +1 other test fail [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html * igt@kms_content_protection@uevent@pipe-a-dp-2: - shard-bmg: NOTRUN -> [FAIL][19] ([Intel XE#1188]) [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-8/igt@kms_content_protection@uevent@pipe-a-dp-2.html * igt@kms_content_protection@uevent@pipe-a-dp-4: - shard-dg2-set2: NOTRUN -> [FAIL][20] ([Intel XE#1188]) [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-433/igt@kms_content_protection@uevent@pipe-a-dp-4.html * igt@kms_cursor_crc@cursor-random-512x170: - shard-bmg: NOTRUN -> [SKIP][21] ([Intel XE#2321]) [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@kms_cursor_crc@cursor-random-512x170.html * igt@kms_cursor_crc@cursor-random-512x512: - shard-dg2-set2: NOTRUN -> [SKIP][22] ([Intel XE#308]) [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-432/igt@kms_cursor_crc@cursor-random-512x512.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-bmg: [PASS][23] -> [SKIP][24] ([Intel XE#2291]) +2 other tests skip [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html * igt@kms_dp_linktrain_fallback@dsc-fallback: - shard-bmg: NOTRUN -> [SKIP][25] ([Intel XE#4331]) [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@kms_dp_linktrain_fallback@dsc-fallback.html * igt@kms_dsc@dsc-with-bpc-formats: - shard-dg2-set2: NOTRUN -> [SKIP][26] ([Intel XE#455]) [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-432/igt@kms_dsc@dsc-with-bpc-formats.html * igt@kms_fbcon_fbt@fbc: - shard-dg2-set2: [PASS][27] -> [SKIP][28] ([Intel XE#2231] / [Intel XE#4208]) [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-dg2-435/igt@kms_fbcon_fbt@fbc.html [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-432/igt@kms_fbcon_fbt@fbc.html * igt@kms_fbcon_fbt@psr-suspend: - shard-dg2-set2: NOTRUN -> [SKIP][29] ([Intel XE#776]) [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-432/igt@kms_fbcon_fbt@psr-suspend.html * igt@kms_feature_discovery@dp-mst: - shard-bmg: NOTRUN -> [SKIP][30] ([Intel XE#2375]) [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@kms_feature_discovery@dp-mst.html * igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible: - shard-dg2-set2: [PASS][31] -> [SKIP][32] ([Intel XE#4208] / [i915#2575]) +1 other test skip [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-dg2-435/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-432/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html * igt@kms_flip@2x-plain-flip-ts-check-interruptible: - shard-bmg: [PASS][33] -> [SKIP][34] ([Intel XE#2316]) +4 other tests skip [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-1/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-6/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html * igt@kms_flip@basic-flip-vs-wf_vblank: - shard-lnl: [PASS][35] -> [FAIL][36] ([Intel XE#3098]) +1 other test fail [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-lnl-3/igt@kms_flip@basic-flip-vs-wf_vblank.html [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-lnl-5/igt@kms_flip@basic-flip-vs-wf_vblank.html * igt@kms_flip@basic-plain-flip@b-hdmi-a1: - shard-adlp: [PASS][37] -> [DMESG-WARN][38] ([Intel XE#4543]) [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-6/igt@kms_flip@basic-plain-flip@b-hdmi-a1.html [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-adlp-3/igt@kms_flip@basic-plain-flip@b-hdmi-a1.html * igt@kms_flip@flip-vs-expired-vblank@c-edp1: - shard-lnl: [PASS][39] -> [FAIL][40] ([Intel XE#301] / [Intel XE#3149]) +1 other test fail [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-adlp: [PASS][41] -> [DMESG-WARN][42] ([Intel XE#2953] / [Intel XE#4173]) +6 other tests dmesg-warn [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-9/igt@kms_flip@flip-vs-suspend-interruptible.html [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-adlp-1/igt@kms_flip@flip-vs-suspend-interruptible.html * igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a3: - shard-bmg: [PASS][43] -> [FAIL][44] ([Intel XE#5338]) +1 other test fail [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-4/igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a3.html [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-6/igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a3.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling: - shard-bmg: NOTRUN -> [SKIP][45] ([Intel XE#2293] / [Intel XE#2380]) [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode: - shard-bmg: NOTRUN -> [SKIP][46] ([Intel XE#2293]) [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff: - shard-dg2-set2: NOTRUN -> [SKIP][47] ([Intel XE#651]) +7 other tests skip [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff.html * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc: - shard-bmg: NOTRUN -> [SKIP][48] ([Intel XE#2311]) +6 other tests skip [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary: - shard-bmg: NOTRUN -> [SKIP][49] ([Intel XE#5390]) +1 other test skip [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc: - shard-bmg: NOTRUN -> [SKIP][50] ([Intel XE#2313]) +6 other tests skip [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move: - shard-dg2-set2: NOTRUN -> [SKIP][51] ([Intel XE#653]) +7 other tests skip [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move.html * igt@kms_pipe_stress@stress-xrgb8888-ytiled: - shard-dg2-set2: NOTRUN -> [SKIP][52] ([Intel XE#4359]) [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-432/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html * igt@kms_plane_cursor@primary@pipe-a-hdmi-a-2-size-256: - shard-dg2-set2: NOTRUN -> [FAIL][53] ([Intel XE#616]) +2 other tests fail [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-432/igt@kms_plane_cursor@primary@pipe-a-hdmi-a-2-size-256.html * igt@kms_pm_dc@dc5-psr: - shard-dg2-set2: NOTRUN -> [SKIP][54] ([Intel XE#1129]) [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-432/igt@kms_pm_dc@dc5-psr.html * igt@kms_pm_dc@dc5-retention-flops: - shard-bmg: NOTRUN -> [SKIP][55] ([Intel XE#3309]) [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@kms_pm_dc@dc5-retention-flops.html * igt@kms_pm_dc@dc6-dpms: - shard-dg2-set2: NOTRUN -> [SKIP][56] ([Intel XE#908]) [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-436/igt@kms_pm_dc@dc6-dpms.html - shard-adlp: [PASS][57] -> [FAIL][58] ([Intel XE#718]) [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-8/igt@kms_pm_dc@dc6-dpms.html [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-adlp-6/igt@kms_pm_dc@dc6-dpms.html * igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area: - shard-dg2-set2: NOTRUN -> [SKIP][59] ([Intel XE#1489]) +2 other tests skip [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-432/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area.html * igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area: - shard-bmg: NOTRUN -> [SKIP][60] ([Intel XE#1489]) +1 other test skip [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area.html * igt@kms_psr@fbc-psr-sprite-plane-onoff: - shard-dg2-set2: NOTRUN -> [SKIP][61] ([Intel XE#2850] / [Intel XE#929]) +3 other tests skip [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-436/igt@kms_psr@fbc-psr-sprite-plane-onoff.html * igt@kms_psr@psr-cursor-plane-onoff: - shard-bmg: NOTRUN -> [SKIP][62] ([Intel XE#2234] / [Intel XE#2850]) +3 other tests skip [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@kms_psr@psr-cursor-plane-onoff.html * igt@kms_rotation_crc@bad-tiling: - shard-dg2-set2: NOTRUN -> [SKIP][63] ([Intel XE#3414]) [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-436/igt@kms_rotation_crc@bad-tiling.html * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0: - shard-bmg: NOTRUN -> [SKIP][64] ([Intel XE#2330]) [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html * igt@kms_scaling_modes@scaling-mode-full: - shard-bmg: NOTRUN -> [SKIP][65] ([Intel XE#2413]) [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@kms_scaling_modes@scaling-mode-full.html * igt@kms_setmode@invalid-clone-single-crtc-stealing: - shard-bmg: [PASS][66] -> [SKIP][67] ([Intel XE#1435]) +1 other test skip [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-4/igt@kms_setmode@invalid-clone-single-crtc-stealing.html [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-6/igt@kms_setmode@invalid-clone-single-crtc-stealing.html * igt@kms_vrr@max-min: - shard-bmg: NOTRUN -> [SKIP][68] ([Intel XE#1499]) +1 other test skip [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@kms_vrr@max-min.html * igt@kms_vrr@negative-basic: - shard-bmg: [PASS][69] -> [SKIP][70] ([Intel XE#1499]) [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-4/igt@kms_vrr@negative-basic.html [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-6/igt@kms_vrr@negative-basic.html * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all: - shard-dg2-set2: NOTRUN -> [SKIP][71] ([Intel XE#1091] / [Intel XE#2849]) [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-436/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html * igt@xe_compute_preempt@compute-preempt: - shard-dg2-set2: NOTRUN -> [SKIP][72] ([Intel XE#1280] / [Intel XE#455]) +1 other test skip [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-432/igt@xe_compute_preempt@compute-preempt.html * igt@xe_eudebug_online@interrupt-other: - shard-dg2-set2: NOTRUN -> [SKIP][73] ([Intel XE#4837]) +3 other tests skip [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-432/igt@xe_eudebug_online@interrupt-other.html * igt@xe_eudebug_online@stopped-thread: - shard-bmg: NOTRUN -> [SKIP][74] ([Intel XE#4837]) +2 other tests skip [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@xe_eudebug_online@stopped-thread.html * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-rebind: - shard-bmg: NOTRUN -> [SKIP][75] ([Intel XE#2322]) +2 other tests skip [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-rebind.html * igt@xe_exec_basic@multigpu-no-exec-null-rebind: - shard-dg2-set2: [PASS][76] -> [SKIP][77] ([Intel XE#1392]) +2 other tests skip [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-dg2-435/igt@xe_exec_basic@multigpu-no-exec-null-rebind.html [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-null-rebind.html * igt@xe_exec_fault_mode@invalid-va: - shard-dg2-set2: NOTRUN -> [SKIP][78] ([Intel XE#288]) +3 other tests skip [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-436/igt@xe_exec_fault_mode@invalid-va.html * igt@xe_exec_reset@parallel-gt-reset: - shard-adlp: [PASS][79] -> [DMESG-WARN][80] ([Intel XE#3876]) [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-8/igt@xe_exec_reset@parallel-gt-reset.html [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-adlp-8/igt@xe_exec_reset@parallel-gt-reset.html - shard-bmg: NOTRUN -> [DMESG-WARN][81] ([Intel XE#3876]) [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@xe_exec_reset@parallel-gt-reset.html * igt@xe_exec_reset@virtual-close-fd-no-exec: - shard-dg2-set2: NOTRUN -> [SKIP][82] ([Intel XE#4208]) +2 other tests skip [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-432/igt@xe_exec_reset@virtual-close-fd-no-exec.html * igt@xe_exec_system_allocator@process-many-execqueues-mmap-free-huge: - shard-bmg: NOTRUN -> [SKIP][83] ([Intel XE#4943]) +4 other tests skip [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@xe_exec_system_allocator@process-many-execqueues-mmap-free-huge.html * igt@xe_exec_system_allocator@threads-many-execqueues-mmap-remap-ro-eocheck: - shard-dg2-set2: NOTRUN -> [SKIP][84] ([Intel XE#4915]) +57 other tests skip [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-432/igt@xe_exec_system_allocator@threads-many-execqueues-mmap-remap-ro-eocheck.html * igt@xe_exec_threads@threads-hang-fd-userptr-rebind: - shard-dg2-set2: [PASS][85] -> [DMESG-WARN][86] ([Intel XE#3876]) [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-dg2-432/igt@xe_exec_threads@threads-hang-fd-userptr-rebind.html [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-433/igt@xe_exec_threads@threads-hang-fd-userptr-rebind.html * igt@xe_exec_threads@threads-mixed-userptr-invalidate-race: - shard-adlp: [PASS][87] -> [DMESG-FAIL][88] ([Intel XE#3876]) +1 other test dmesg-fail [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-8/igt@xe_exec_threads@threads-mixed-userptr-invalidate-race.html [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-adlp-8/igt@xe_exec_threads@threads-mixed-userptr-invalidate-race.html * igt@xe_oa@invalid-create-userspace-config: - shard-dg2-set2: NOTRUN -> [SKIP][89] ([Intel XE#2541] / [Intel XE#3573]) [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-432/igt@xe_oa@invalid-create-userspace-config.html * igt@xe_oa@syncs-userptr-wait: - shard-dg2-set2: NOTRUN -> [SKIP][90] ([Intel XE#2541] / [Intel XE#3573] / [Intel XE#4501]) [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-436/igt@xe_oa@syncs-userptr-wait.html * igt@xe_pm@d3cold-basic-exec: - shard-bmg: NOTRUN -> [SKIP][91] ([Intel XE#2284]) [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@xe_pm@d3cold-basic-exec.html * igt@xe_pxp@pxp-stale-bo-bind-post-rpm: - shard-bmg: NOTRUN -> [SKIP][92] ([Intel XE#4733]) [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@xe_pxp@pxp-stale-bo-bind-post-rpm.html * igt@xe_pxp@regular-src-to-pxp-dest-rendercopy: - shard-dg2-set2: NOTRUN -> [SKIP][93] ([Intel XE#4733]) [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-436/igt@xe_pxp@regular-src-to-pxp-dest-rendercopy.html * igt@xe_sriov_flr@flr-vfs-parallel: - shard-bmg: NOTRUN -> [SKIP][94] ([Intel XE#4273]) [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-2/igt@xe_sriov_flr@flr-vfs-parallel.html #### Possible fixes #### * igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p: - shard-bmg: [SKIP][95] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][96] +1 other test pass [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-4/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc: - shard-dg2-set2: [INCOMPLETE][97] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522]) -> [PASS][98] +1 other test pass [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size: - shard-bmg: [SKIP][99] ([Intel XE#2291]) -> [PASS][100] +4 other tests pass [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-3/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html * igt@kms_dp_linktrain_fallback@dp-fallback: - shard-bmg: [SKIP][101] ([Intel XE#4294]) -> [PASS][102] [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-6/igt@kms_dp_linktrain_fallback@dp-fallback.html [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-3/igt@kms_dp_linktrain_fallback@dp-fallback.html * igt@kms_flip@2x-flip-vs-dpms: - shard-bmg: [SKIP][103] ([Intel XE#2316]) -> [PASS][104] +3 other tests pass [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms.html [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-4/igt@kms_flip@2x-flip-vs-dpms.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-lnl: [FAIL][105] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][106] [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1: - shard-lnl: [FAIL][107] ([Intel XE#301]) -> [PASS][108] +2 other tests pass [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html * igt@kms_flip@flip-vs-rmfb-interruptible: - shard-adlp: [DMESG-WARN][109] ([Intel XE#4543] / [Intel XE#5208]) -> [PASS][110] [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-1/igt@kms_flip@flip-vs-rmfb-interruptible.html [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-adlp-9/igt@kms_flip@flip-vs-rmfb-interruptible.html * igt@kms_flip@flip-vs-rmfb-interruptible@b-hdmi-a1: - shard-adlp: [DMESG-WARN][111] ([Intel XE#4543]) -> [PASS][112] +1 other test pass [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-1/igt@kms_flip@flip-vs-rmfb-interruptible@b-hdmi-a1.html [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-adlp-9/igt@kms_flip@flip-vs-rmfb-interruptible@b-hdmi-a1.html * igt@kms_flip@flip-vs-suspend@b-hdmi-a1: - shard-adlp: [DMESG-WARN][113] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][114] +3 other tests pass [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-8/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-adlp-6/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html * igt@kms_hdr@static-toggle-suspend: - shard-bmg: [SKIP][115] ([Intel XE#1503]) -> [PASS][116] [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-6/igt@kms_hdr@static-toggle-suspend.html [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-4/igt@kms_hdr@static-toggle-suspend.html * igt@kms_pm_dc@dc5-dpms: - shard-adlp: [FAIL][117] ([Intel XE#718]) -> [PASS][118] [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-adlp-1/igt@kms_pm_dc@dc5-dpms.html [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-adlp-9/igt@kms_pm_dc@dc5-dpms.html * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-rebind: - shard-dg2-set2: [SKIP][119] ([Intel XE#1392]) -> [PASS][120] +4 other tests pass [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-dg2-432/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-rebind.html [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-433/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-rebind.html #### Warnings #### * igt@kms_content_protection@uevent: - shard-bmg: [SKIP][121] ([Intel XE#2341]) -> [FAIL][122] ([Intel XE#1188]) [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-6/igt@kms_content_protection@uevent.html [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-8/igt@kms_content_protection@uevent.html * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt: - shard-bmg: [SKIP][123] ([Intel XE#2311]) -> [SKIP][124] ([Intel XE#2312]) +6 other tests skip [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt.html [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render: - shard-bmg: [SKIP][125] ([Intel XE#2312]) -> [SKIP][126] ([Intel XE#5390]) +6 other tests skip [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff: - shard-bmg: [SKIP][127] ([Intel XE#5390]) -> [SKIP][128] ([Intel XE#2312]) +4 other tests skip [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc: - shard-bmg: [SKIP][129] ([Intel XE#2312]) -> [SKIP][130] ([Intel XE#2311]) +12 other tests skip [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt: - shard-bmg: [SKIP][131] ([Intel XE#2312]) -> [SKIP][132] ([Intel XE#2313]) +11 other tests skip [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt.html [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc: - shard-bmg: [SKIP][133] ([Intel XE#2313]) -> [SKIP][134] ([Intel XE#2312]) +4 other tests skip [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html * igt@kms_tiled_display@basic-test-pattern: - shard-bmg: [FAIL][135] ([Intel XE#1729]) -> [SKIP][136] ([Intel XE#2426]) [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern.html * igt@xe_exec_capture@reset: - shard-dg2-set2: [INCOMPLETE][137] ([Intel XE#4842]) -> [SKIP][138] ([Intel XE#4208]) [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-dg2-435/igt@xe_exec_capture@reset.html [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-432/igt@xe_exec_capture@reset.html * igt@xe_exec_system_allocator@many-execqueues-mmap-file-nomemset: - shard-dg2-set2: [SKIP][139] ([Intel XE#4915]) -> [SKIP][140] ([Intel XE#4208]) +3 other tests skip [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331/shard-dg2-435/igt@xe_exec_system_allocator@many-execqueues-mmap-file-nomemset.html [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/shard-dg2-432/igt@xe_exec_system_allocator@many-execqueues-mmap-file-nomemset.html [Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091 [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124 [Intel XE#1129]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1129 [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178 [Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188 [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280 [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392 [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435 [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489 [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499 [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503 [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727 [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729 [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191 [Intel XE#2231]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2231 [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234 [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252 [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284 [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291 [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293 [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311 [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312 [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313 [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314 [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316 [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321 [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322 [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325 [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330 [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341 [Intel XE#2375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2375 [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380 [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413 [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426 [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541 [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652 [Intel XE#2849]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2849 [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850 [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288 [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887 [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894 [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907 [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953 [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301 [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308 [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098 [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113 [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149 [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316 [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309 [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414 [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573 [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366 [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373 [Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876 [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173 [Intel XE#4208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4208 [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212 [Intel XE#4273]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4273 [Intel XE#4294]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4294 [Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331 [Intel XE#4359]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4359 [Intel XE#4501]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4501 [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522 [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543 [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455 [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733 [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837 [Intel XE#4842]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4842 [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915 [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943 [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208 [Intel XE#5338]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5338 [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390 [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616 [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651 [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653 [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718 [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776 [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787 [Intel XE#908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/908 [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929 [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575 Build changes ------------- * Linux: xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331 -> xe-pw-151737v1 IGT_8462: f33a311145a889757f45313d2ff4bf58f7ef01d6 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git xe-3429-e7058b7a607f5fdfd7bc4586644756d7ef002331: e7058b7a607f5fdfd7bc4586644756d7ef002331 xe-pw-151737v1: 151737v1 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151737v1/index.html [-- Attachment #2: Type: text/html, Size: 47304 bytes --] ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2025-07-21 16:22 UTC | newest] Thread overview: 14+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-07-17 5:16 [PATCH] drm/i915/display: Skip unavailable power wells based on pipe mask Chaitanya Kumar Borah 2025-07-17 5:39 ` ✗ CI.checkpatch: warning for " Patchwork 2025-07-17 5:41 ` ✓ CI.KUnit: success " Patchwork 2025-07-17 7:09 ` ✓ Xe.CI.BAT: " Patchwork 2025-07-17 12:02 ` [PATCH] " Gustavo Sousa 2025-07-18 15:54 ` Imre Deak 2025-07-18 16:33 ` Gustavo Sousa 2025-07-18 17:17 ` Imre Deak 2025-07-18 20:16 ` Gustavo Sousa 2025-07-19 10:37 ` Imre Deak 2025-07-21 14:17 ` Gustavo Sousa 2025-07-21 15:17 ` Borah, Chaitanya Kumar 2025-07-21 16:21 ` Imre Deak 2025-07-18 8:46 ` ✗ Xe.CI.Full: failure for " Patchwork
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