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From: Gustavo Sousa <gustavo.sousa@intel.com>
To: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>,
	<intel-gfx@lists.freedesktop.org>,
	<intel-xe@lists.freedesktop.org>
Cc: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Subject: Re: [PATCH v2 3/3] drm/i915/xe3: Restrict PTL intel_encoder_is_c10phy() to only PHY A
Date: Fri, 19 Sep 2025 18:01:16 -0300	[thread overview]
Message-ID: <175831567651.1987.11686211487230198274@intel.com> (raw)
In-Reply-To: <20250919162233.1624905-4-dnyaneshwar.bhadane@intel.com>

Quoting Dnyaneshwar Bhadane (2025-09-19 13:22:33-03:00)
>On PTL, no combo PHY is connected to PORT B. However, PORT B can
>still be used for Type-C and will utilize the C20 PHY for eDP
>over Type-C. In such configurations, VBTs also enumerate PORT B.
>
>This leads to issues where PORT B is incorrectly identified as using the
>C10 PHY, due to the assumption that returning true for PORT B in
>intel_encoder_is_c10phy() would not cause problems.
>
>From PTL's perspective, only PORT A/PHY A uses the C10 PHY.
>
>Update the helper intel_encoder_is_c10phy() to return true only for
>PORT A/PHY on PTL.
>
>Bspec: 72571,73944
>Fixes: 9d10de78a37f ("drm/i915/wcl: C10 phy connected to port A and B")
>Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 ++++-------
> 1 file changed, 4 insertions(+), 7 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>index 801235a5bc0a..e8b354d1c513 100644
>--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>@@ -39,13 +39,10 @@ bool intel_encoder_is_c10phy(struct intel_encoder *encoder)
>         struct intel_display *display = to_intel_display(encoder);
>         enum phy phy = intel_encoder_to_phy(encoder);
> 
>-        /* PTL doesn't have a PHY connected to PORT B; as such,
>-         * there will never be a case where PTL uses PHY B.
>-         * WCL uses PORT A and B with the C10 PHY.
>-         * Reusing the condition for WCL and extending it for PORT B
>-         * should not cause any issues for PTL.
>-         */
>-        if (display->platform.pantherlake && phy < PHY_C)
>+        if (display->platform.pantherlake && phy == PHY_A)
>+                return true;

While we know that WCL will return true for PHY_A here, this might not
be so obvious...

>+
>+        if (display->platform.pantherlake_wildcatlake && phy == PHY_B)
>                 return true;


...so, what about something like below?

    if (display->platform.pantherlake) {
        if (display->platform.pantherlake_wildcatlake)
            return phy <= PHY_B;
        else
            return phy == PHY_A;
    }

We could also update the style for MTL and LNL in a follow-up patch...

--
Gustavo Sousa

> 
>         if ((display->platform.lunarlake || display->platform.meteorlake) && phy < PHY_C)
>-- 
>2.51.0
>

  reply	other threads:[~2025-09-19 21:01 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-19 16:22 [PATCH v2 0/3] drm/i915/xe3: Restrict PTL intel_encoder_is_c10phy() to only PHY A Dnyaneshwar Bhadane
2025-09-19 16:22 ` [PATCH v2 1/3] drm/pcids: Split PTL pciids group to make wcl subplatform Dnyaneshwar Bhadane
2025-09-19 20:19   ` Gustavo Sousa
2025-09-19 16:22 ` [PATCH v2 2/3] drm/i915/display: Add definition for wcl as subplatform Dnyaneshwar Bhadane
2025-09-19 20:32   ` Gustavo Sousa
2025-09-22  8:55     ` Jani Nikula
2025-09-19 16:22 ` [PATCH v2 3/3] drm/i915/xe3: Restrict PTL intel_encoder_is_c10phy() to only PHY A Dnyaneshwar Bhadane
2025-09-19 21:01   ` Gustavo Sousa [this message]
2025-09-22 15:14     ` Bhadane, Dnyaneshwar
2025-09-19 16:59 ` ✗ CI.checkpatch: warning for drm/i915/xe3: Restrict PTL intel_encoder_is_c10phy() to only PHY A (rev2) Patchwork
2025-09-19 17:00 ` ✓ CI.KUnit: success " Patchwork
2025-09-19 17:15 ` ✗ CI.checksparse: warning " Patchwork
2025-09-19 17:34 ` ✓ Xe.CI.BAT: success " Patchwork
2025-09-20  1:41 ` ✗ Xe.CI.Full: failure " Patchwork

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