Re: [PATCH 05/14] drm/i915/cdclk: Stop forcing voltage level to 3 all the time on DG2

[Jani Nikula <jani.nikula@linux.intel.com>]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> SKL_CDCLK_PREPARE_FOR_CHANGE == DISPLAY_TO_PCODE_VOLTAGE(3) so
> we are currently forcing the voltage level to 3 all the time on
> DG2. Remove SKL_CDCLK_PREPARE_FOR_CHANGE from the mask to avoid
> this.

Fixes: ?

The pcode mailbox defines are a mess.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 7259048361a7..ecb6be3383ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2598,7 +2598,6 @@ static void intel_pcode_notify(struct intel_display *display,
>  		update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID;
>  
>  	ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
> -					 SKL_CDCLK_PREPARE_FOR_CHANGE |
>  					 update_mask,
>  					 SKL_CDCLK_READY_FOR_CHANGE,
>  					 SKL_CDCLK_READY_FOR_CHANGE, 3);

-- 
Jani Nikula, Intel