From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [PATCH 02/14] drm/i915/cdclk: Pass CDCLK in MHz to pcode on DG2
Date: Wed, 10 Jun 2026 21:54:39 +0300 [thread overview]
Message-ID: <aimy71wEwM-ky0Tw@intel.com> (raw)
In-Reply-To: <4e72aea4331149f4f54016dfb884e171255ba483@intel.com>
On Wed, Jun 10, 2026 at 08:31:48PM +0300, Jani Nikula wrote:
> On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > We are currently trying to pass the CDCLK in kHz to the pcode
> > on DG2, while the pcode expects a value in MHz units. Adjust
> > the units appropriately.
>
> How is it working? :o
I don't think DG2 pcode does all that much a with the information.
Eg. AFAIK it doesn't actually adjust any voltages due to this stuff.
I think it's more for some internal power usage estimates or something,
but dunno what that really means in practice.
>
> Fixes: ?
>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 8 ++++++--
> > 1 file changed, 6 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 9ca56bab281f..9718062d8d6c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -2703,8 +2703,10 @@ static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
> > * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK,
> > * which basically means we choose the maximum of old and new CDCLK, if we know both
> > */
> > - if (change_cdclk)
> > + if (change_cdclk) {
> > cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk);
> > + cdclk = DIV_ROUND_UP(cdclk, 1000);
> > + }
>
> I'd consider s/cdclk/cdclk_mhz/g here and in intel_pcode_notify() to
> emphasize it's not kHz.
>
> > /*
> > * According to "Sequence For Pipe Count Change",
> > @@ -2740,8 +2742,10 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
> > * According to "Sequence After Frequency Change",
> > * set bits 25:16 to current CDCLK
> > */
> > - if (update_cdclk)
> > + if (update_cdclk) {
> > cdclk = new_cdclk_state->actual.cdclk;
> > + cdclk = DIV_ROUND_UP(cdclk, 1000);
> > + }
>
> Ditto.
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> >
> > /*
> > * According to "Sequence For Pipe Count Change",
>
> --
> Jani Nikula, Intel
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2026-06-10 18:54 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-10 17:06 [PATCH 00/14] drm/i915/cdclk: cdclk pcode related fixes and refactoring Ville Syrjala
2026-06-10 17:06 ` [PATCH 01/14] drm/i915/cdclk: Don't bail if pcode post nofify fails Ville Syrjala
2026-06-10 17:32 ` Jani Nikula
2026-06-10 17:06 ` [PATCH 02/14] drm/i915/cdclk: Pass CDCLK in MHz to pcode on DG2 Ville Syrjala
2026-06-10 17:31 ` Jani Nikula
2026-06-10 18:54 ` Ville Syrjälä [this message]
2026-06-10 17:06 ` [PATCH 03/14] drm/i915/cdclk: Do the DG2 CDCLK/pipe power well notify properly Ville Syrjala
2026-06-11 7:23 ` Jani Nikula
2026-06-10 17:06 ` [PATCH 04/14] drm/i915/cdclk: Notify DG2 pcode about pipe power wells regardless of CDCLK Ville Syrjala
2026-06-11 7:31 ` Jani Nikula
2026-06-10 17:06 ` [PATCH 05/14] drm/i915/cdclk: Stop forcing voltage level to 3 all the time on DG2 Ville Syrjala
2026-06-11 7:35 ` Jani Nikula
2026-06-10 17:06 ` [PATCH 06/14] drm/i915/cdclk: Drop pointless platform check from bxt_set_cdclk() Ville Syrjala
2026-06-11 7:37 ` Jani Nikula
2026-06-10 17:06 ` [PATCH 07/14] drm/i915/dg2: s/intel_/dg2_/ for DG2 specific stuff Ville Syrjala
2026-06-10 17:34 ` Jani Nikula
2026-06-10 17:06 ` [PATCH 08/14] drm/i915/cdclk: Unify the pcode pre/post notify in bxt_set_cdclk() Ville Syrjala
2026-06-10 17:06 ` [PATCH 09/14] drm/i915/cdclk: Unify pcode related debugs Ville Syrjala
2026-06-10 17:37 ` Jani Nikula
2026-06-10 17:06 ` [PATCH 10/14] drm/i915/cdclk: Extract bdw_cdclk_pcode_{pre, post}_notify() Ville Syrjala
2026-06-10 17:38 ` Jani Nikula
2026-06-10 17:06 ` [PATCH 11/14] drm/i915/cdclk: Extract skl_cdclk_pcode_{pre, post}_notify() Ville Syrjala
2026-06-10 17:38 ` Jani Nikula
2026-06-10 17:06 ` [PATCH 12/14] drm/i915/cdclk: Extract bxt_cdclk_pcode_{pre, post}_notify() Ville Syrjala
2026-06-10 17:39 ` Jani Nikula
2026-06-10 17:06 ` [PATCH 13/14] drm/i915/cdclk: Introduce CDCLK .{pre, post}_notify() vfuncs Ville Syrjala
2026-06-10 17:06 ` [PATCH 14/14] drm/i915/cdclk: Hoist intel_cdclk_{pre, post}_notify() calls upwards Ville Syrjala
2026-06-10 17:17 ` ✓ CI.KUnit: success for drm/i915/cdclk: cdclk pcode related fixes and refactoring Patchwork
2026-06-10 18:11 ` ✓ Xe.CI.BAT: " Patchwork
2026-06-10 22:49 ` ✗ Xe.CI.FULL: failure " Patchwork
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