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* [PATCH 0/3] drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs
@ 2026-06-10 17:44 Alexander Kaplan
  2026-06-10 17:44 ` [PATCH 1/3] drm/i915/dp: Prefer DSC over a 6 bpc uncompressed output Alexander Kaplan
                   ` (7 more replies)
  0 siblings, 8 replies; 14+ messages in thread
From: Alexander Kaplan @ 2026-06-10 17:44 UTC (permalink / raw)
  To: intel-gfx, intel-xe
  Cc: Ankit Nautiyal, Ville Syrjälä, Imre Deak,
	Chaitanya Kumar Borah, Nicolas Frattaroli, Jani Nikula,
	Rodrigo Vivi, alexander.kaplan

HDMI 2.1 sinks behind a DP to HDMI 2.1 PCON are currently limited to
8bpc, and the FRL link often trains below what the hardware supports,
because

 1) the sink's DSC max FRL rate caps the trained FRL rate even when
    the PCON has no DSC encoder and thus never produces compressed
    transport, and

 2) the bpc computation validates HDMI sinks behind a branch device
    against the sink's TMDS character rate limits even when the video
    is transmitted over FRL.

On a Panther Lake NUC (xe) with a Synaptics VMM7100 PCON and an LG
OLED G4 (Max_FRL_Rate 48 Gbps, DSC_Max_FRL_Rate 24 Gbps, max TMDS
character rate 600 MHz) this means: FRL trains at 24 instead of
48 Gbps and 4k60 is limited to RGB 8bpc, while Windows (RGB 10bpc,
FRL 40G) and macOS (RGB 12bpc, FRL 48G) drive the same hardware with
deep color.

Patch 2 applies the sink's DSC max FRL rate only when the PCON
actually has a DSC 1.2 encoder (the gate intel_dp_pcon_dsc_configure()
already uses).
Patch 3 makes intel_dp_hdmi_compute_bpc() validate the required
bandwidth against the FRL bandwidth the link will be trained with,
instead of the TMDS limits, for FRL-capable PCON+sink combos.

Patch 1 makes the link config prefer DSC over a dithered 6 bpc
uncompressed output.
This is a quality improvement on its own, but it is also ordered
first for bisectability.
Patches 2 and 3 open up RGB configurations on FRL links for which
previously only the YCbCr 4:2:0 fallback existed, and modes which fit
such a link uncompressed only with 6 bpc (e.g. 4k120 on a 4 lane HBR3
link) would then select an RGB 6 bpc output.
The tested Synaptics PCONs (two device families) cannot display a
6 bpc stream at such pixel clocks, so without patch 1 this would
trade the previous 4:2:0 picture for a black screen.

With the full series the setup above runs 4k60 at RGB 12bpc with HDR
at FRL 48G, and 4k120 at RGB 12bpc (DSC, both SDR and HDR), stable
across modesets, hotplugs and suspend/resume.
This was also verified on a second Synaptics PCON device family (a
TBT4 dock, SYNAa) and against a VMM7100 with a DP branch ID (where
the HDMI paths stay inert).

A related observation, left for a separate change:
intel_dp_mode_valid_downstream() checks the FRL bandwidth only
against the PCON's limit (not the sink's max FRL rate from the EDID)
and skips the TMDS/dotclock checks even for non-FRL sinks behind an
FRL capable PCON.
Aligning it with the limit used in patch 3 would make .mode_valid()
pruning consistent with the compute path.

This series is the first part of a set of independent fixes for the
USB-C to DP to HDMI 2.1 protocol converter (PCON) path, found and
verified on an ASUS NUC 16 Pro (Panther Lake, xe driver) driving an
LG OLED TV through Synaptics VMM7100 based adapters.
Two dongle firmware lines and a TB4 dock were tested.
Each series/patch stands on its own and can be merged independently.
This series targets drm-intel, the DP helper patches of the set
target drm-misc.

The other parts, to follow shortly:
  drm/dp: Avoid RBR on Synaptics VMM7100 PCONs failing channel EQ
  drm/dp: Read the PCON max FRL bandwidth only for HDMI DFPs
  drm/dp: Service the CEC tunneling IRQ flags without CEC_IRQ in ESI1

Alexander Kaplan (3):
  drm/i915/dp: Prefer DSC over a 6 bpc uncompressed output
  drm/i915/dp: Ignore the sink's DSC max FRL rate without a PCON DSC
    encoder
  drm/i915/dp: Check FRL bandwidth limits in the HDMI bpc computation

 drivers/gpu/drm/i915/display/intel_dp.c | 58 ++++++++++++++++++++++++-
 1 file changed, 56 insertions(+), 2 deletions(-)

-- 
2.54.0



^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 1/3] drm/i915/dp: Prefer DSC over a 6 bpc uncompressed output
  2026-06-10 17:44 [PATCH 0/3] drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs Alexander Kaplan
@ 2026-06-10 17:44 ` Alexander Kaplan
  2026-06-12 16:32   ` Imre Deak
  2026-06-10 17:44 ` [PATCH 2/3] drm/i915/dp: Ignore the sink's DSC max FRL rate without a PCON DSC encoder Alexander Kaplan
                   ` (6 subsequent siblings)
  7 siblings, 1 reply; 14+ messages in thread
From: Alexander Kaplan @ 2026-06-10 17:44 UTC (permalink / raw)
  To: intel-gfx, intel-xe
  Cc: Ankit Nautiyal, Ville Syrjälä, Imre Deak,
	Chaitanya Kumar Borah, Nicolas Frattaroli, Jani Nikula,
	Rodrigo Vivi, alexander.kaplan

For modes which fit through the link uncompressed only with a 6 bpc
pipe BPP, the link config currently selects 6 bpc with dithering even
if the sink supports DSC.
DSC with an at least 8 bpc input provides a better output quality
than a dithered 6 bpc output, so prefer it, following the pattern
commit ba49a4643cf5 ("drm/i915/dp: Set min_bpp limit to 30 in HDR
mode") uses for HDR: keep the uncompressed minimum pipe BPP at 8 bpc
if the sink supports DSC, making the uncompressed link config fail
for such modes and the mode fall back to DSC.
As there, if the DSC computation fails, the mode falls back to YCbCr
4:2:0 where supported, or gets rejected.

Besides the output quality, some sinks can't even display a 6 bpc
stream at high pixel clocks.
Synaptics VMM PCON based DP to HDMI 2.1 adapters from two device
families (branch device IDs SYNAq and SYNAa) output corrupted FRL
timings for an uncompressed RGB 6 bpc 4k120 (1188 MHz) stream,
resulting in a black screen, while the same mode works with DSC
(12 bpc input) and 6 bpc works at lower pixel clocks.
Windows and macOS drive 4k120 on these devices only via DSC.

A lower bpc limit explicitly requested via the max bpc connector
property is still honored.
This keeps the current uAPI behavior (exercised by IGT kms_dither)
and provides an escape hatch for sinks with a broken DSC
implementation.
Sinks without DSC support keep falling back to 6 bpc.

Tested on PTL (xe) with the above PCONs and an LG OLED G4.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Alexander Kaplan <alexander.kaplan@sms-medipool.de>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 85d3aa3b9894..13cfccf60490 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2839,6 +2839,18 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 								     crtc_state)));
 	}
 
+	/*
+	 * Prefer DSC with an at least 8 bpc input over a dithered 6 bpc
+	 * uncompressed output, by failing the uncompressed link config for
+	 * modes which would fit only with a 6 bpc pipe BPP. Honor a lower
+	 * limit set via the max bpc connector property.
+	 */
+	if (!dsc &&
+	    intel_dp_supports_dsc(intel_dp, connector, crtc_state) &&
+	    limits->pipe.max_bpp >= 24 &&
+	    crtc_state->pipe_bpp >= 24)
+		limits->pipe.min_bpp = max(limits->pipe.min_bpp, 24);
+
 	if (limits->pipe.min_bpp <= 0 ||
 	    limits->pipe.min_bpp > limits->pipe.max_bpp) {
 		drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Invalid pipe bpp range: %d-%d\n",
-- 
2.54.0



^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [PATCH 2/3] drm/i915/dp: Ignore the sink's DSC max FRL rate without a PCON DSC encoder
  2026-06-10 17:44 [PATCH 0/3] drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs Alexander Kaplan
  2026-06-10 17:44 ` [PATCH 1/3] drm/i915/dp: Prefer DSC over a 6 bpc uncompressed output Alexander Kaplan
@ 2026-06-10 17:44 ` Alexander Kaplan
  2026-06-29  4:01   ` Nautiyal, Ankit K
  2026-06-10 17:44 ` [PATCH 3/3] drm/i915/dp: Check FRL bandwidth limits in the HDMI bpc computation Alexander Kaplan
                   ` (5 subsequent siblings)
  7 siblings, 1 reply; 14+ messages in thread
From: Alexander Kaplan @ 2026-06-10 17:44 UTC (permalink / raw)
  To: intel-gfx, intel-xe
  Cc: Ankit Nautiyal, Ville Syrjälä, Imre Deak,
	Chaitanya Kumar Borah, Nicolas Frattaroli, Jani Nikula,
	Rodrigo Vivi, alexander.kaplan

intel_dp_hdmi_sink_max_frl() limits the sink's max FRL rate by its
DSC max FRL rate whenever the sink supports DSC 1.2.
However, the DSC max FRL rate (HF-VSDB DSC_Max_FRL_Rate) only applies
to compressed video transport, which requires a DSC 1.2 encoder in
the PCON (configured via intel_dp_pcon_dsc_configure()).
Without such an encoder the HDMI link always carries uncompressed
video, for which the regular Max_FRL_Rate is the correct limit.

Applying the DSC limit unconditionally trains the FRL link at a lower
rate than both the PCON and the sink support.
E.g. an LG OLED G4 (Max_FRL_Rate 48 Gbps, DSC_Max_FRL_Rate 24 Gbps)
behind a Synaptics VMM7100 PCON (PCON max FRL bw 48 Gbps, no DSC
encoder):

  Sink max rate from EDID = 24 Gbps
  FRL trained with : 24 Gbps

while Windows/macOS train the same hardware at 40/48 Gbps.
The too low FRL rate needlessly constrains the formats available to
the sink.

Only apply the sink's DSC max FRL rate if the PCON has a DSC 1.2
encoder, matching the gate in intel_dp_pcon_dsc_configure().
PCONs with a DSC encoder keep the current conservative behavior,
since the link is trained once and compressed transport may be used
for any subsequent mode.
With this the setup above trains at 48 Gbps.

Tested on PTL (xe) with the above PCON/sink combo.

Fixes: 10fec80b48c5 ("drm/i915/display: Configure PCON for DSC1.1 to DSC1.2 encoding")
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Alexander Kaplan <alexander.kaplan@sms-medipool.de>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 13cfccf60490..2831b274d88a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4254,7 +4254,14 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
 	rate_per_lane = info->hdmi.max_frl_rate_per_lane;
 	max_frl_rate = max_lanes * rate_per_lane;
 
-	if (info->hdmi.dsc_cap.v_1p2) {
+	/*
+	 * The sink's DSC max FRL rate only applies to compressed video
+	 * transport, which requires a DSC 1.2 encoder in the PCON. Without
+	 * one the HDMI link always carries uncompressed video, for which
+	 * the regular max FRL rate is the limit.
+	 */
+	if (drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) &&
+	    info->hdmi.dsc_cap.v_1p2) {
 		max_dsc_lanes = info->hdmi.dsc_cap.max_lanes;
 		dsc_rate_per_lane = info->hdmi.dsc_cap.max_frl_rate_per_lane;
 		if (max_dsc_lanes && dsc_rate_per_lane)
-- 
2.54.0



^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [PATCH 3/3] drm/i915/dp: Check FRL bandwidth limits in the HDMI bpc computation
  2026-06-10 17:44 [PATCH 0/3] drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs Alexander Kaplan
  2026-06-10 17:44 ` [PATCH 1/3] drm/i915/dp: Prefer DSC over a 6 bpc uncompressed output Alexander Kaplan
  2026-06-10 17:44 ` [PATCH 2/3] drm/i915/dp: Ignore the sink's DSC max FRL rate without a PCON DSC encoder Alexander Kaplan
@ 2026-06-10 17:44 ` Alexander Kaplan
  2026-06-29  4:16   ` Nautiyal, Ankit K
  2026-06-10 17:49 ` [PATCH 0/3] drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs Alexander Kaplan
                   ` (4 subsequent siblings)
  7 siblings, 1 reply; 14+ messages in thread
From: Alexander Kaplan @ 2026-06-10 17:44 UTC (permalink / raw)
  To: intel-gfx, intel-xe
  Cc: Ankit Nautiyal, Ville Syrjälä, Imre Deak,
	Chaitanya Kumar Borah, Nicolas Frattaroli, Jani Nikula,
	Rodrigo Vivi, alexander.kaplan

The bpc computation for HDMI sinks behind a DP branch device
(intel_dp_hdmi_compute_bpc()) validates each bpc candidate against
the sink's TMDS character rate limits, even if the video will be
transmitted over an FRL link, where those limits don't apply.

This caps such sinks at 8bpc whenever a deep color mode's
TMDS-equivalent character rate exceeds the TMDS limit, although the
FRL link has plenty of bandwidth.
E.g. 4k60 RGB 10bpc corresponds to a ~742 MHz TMDS character rate,
above the typical 600 MHz limit, but only needs ~17.8 Gbps of e.g. a
48 Gbps FRL link.
Modes whose rate exceeds the TMDS limit already at 8bpc (e.g. 4k120)
are additionally forced from RGB to YCbCr 4:2:0 output.

If both the PCON and the sink support FRL, validate the required
bandwidth against the FRL bandwidth the link will be trained with
(the same min() of the PCON's and the sink's max FRL rate that
intel_dp_pcon_start_frl_training() uses) instead of the TMDS limits.
This mirrors how intel_dp_mode_valid_downstream() already validates
modes against the FRL bandwidth for such sinks.
Sinks without FRL support behind an FRL capable PCON keep using the
TMDS limits, since the PCON transmits to them in TMDS mode.

The sink's deep color EDID capabilities still apply via
intel_hdmi_bpc_possible(), and the DP link side limits are handled
separately, as before.

intel_dp_mode_valid_downstream() currently checks the FRL bandwidth
only against the PCON's limit and also skips the TMDS checks for
non-FRL sinks behind an FRL capable PCON.
Aligning it with the limit used here is left for a separate change.

Tested on PTL (xe) with a Synaptics VMM7100 PCON and an LG OLED G4:
4k60 goes from RGB 8bpc (dithered 6bpc pipe) to RGB 12bpc with HDR,
matching macOS (12bpc) and Windows (10bpc) on the same hardware.

Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Alexander Kaplan <alexander.kaplan@sms-medipool.de>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 37 ++++++++++++++++++++++++-
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2831b274d88a..511d99326af4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -124,6 +124,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
 }
 
 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
+static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp);
 
 /* Is link rate UHBR and thus 128b/132b? */
 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -1347,6 +1348,40 @@ static int frl_required_bw(int clock, int bpc,
 	return clock * bpc * 3;
 }
 
+static enum drm_mode_status
+intel_dp_hdmi_clock_valid(struct intel_dp *intel_dp,
+			  int clock, int bpc,
+			  enum intel_output_format sink_format,
+			  bool respect_downstream_limits)
+{
+	int max_frl_bw;
+
+	if (!respect_downstream_limits)
+		return MODE_OK;
+
+	/* The FRL bandwidth the link will be trained with */
+	max_frl_bw = min(intel_dp->dfp.pcon_max_frl_bw,
+			 intel_dp_hdmi_sink_max_frl(intel_dp));
+
+	/*
+	 * If both the PCON and the sink support FRL, the PCON transmits
+	 * to the sink in FRL mode, where the TMDS character rate limits
+	 * don't apply.
+	 */
+	if (max_frl_bw > 0) {
+		/* converting bw from Gbps to Kbps */
+		max_frl_bw = max_frl_bw * 1000000;
+
+		if (frl_required_bw(clock, bpc, sink_format) > max_frl_bw)
+			return MODE_CLOCK_HIGH;
+
+		return MODE_OK;
+	}
+
+	return intel_dp_tmds_clock_valid(intel_dp, clock, bpc,
+					 sink_format, respect_downstream_limits);
+}
+
 static enum drm_mode_status
 intel_dp_mode_valid_downstream(struct intel_connector *connector,
 			       const struct drm_display_mode *mode,
@@ -1831,7 +1866,7 @@ static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
 	for (; bpc >= 8; bpc -= 2) {
 		if (intel_hdmi_bpc_possible(crtc_state, bpc,
 					    intel_dp_has_hdmi_sink(intel_dp)) &&
-		    intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
+		    intel_dp_hdmi_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
 					      respect_downstream_limits) == MODE_OK)
 			return bpc;
 	}
-- 
2.54.0



^ permalink raw reply related	[flat|nested] 14+ messages in thread

* Re: [PATCH 0/3] drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs
  2026-06-10 17:44 [PATCH 0/3] drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs Alexander Kaplan
                   ` (2 preceding siblings ...)
  2026-06-10 17:44 ` [PATCH 3/3] drm/i915/dp: Check FRL bandwidth limits in the HDMI bpc computation Alexander Kaplan
@ 2026-06-10 17:49 ` Alexander Kaplan
  2026-06-10 18:45 ` ✗ LGCI.VerificationFailed: failure for " Patchwork
                   ` (3 subsequent siblings)
  7 siblings, 0 replies; 14+ messages in thread
From: Alexander Kaplan @ 2026-06-10 17:49 UTC (permalink / raw)
  To: intel-gfx, intel-xe
  Cc: Ankit Nautiyal, Ville Syrjälä, Imre Deak,
	Chaitanya Kumar Borah, Nicolas Frattaroli, Jani Nikula,
	Rodrigo Vivi, alexander.kaplan

All parts of this fix set are now on the lists, for reference:

[1] this series
[2] drm/dp: Avoid RBR on Synaptics VMM7100 PCONs failing channel EQ
    https://lore.kernel.org/r/20260610174807.6231-1-alexander.kaplan@sms-medipool.de
[3] drm/dp: Read the PCON max FRL bandwidth only for HDMI DFPs
    https://lore.kernel.org/r/20260610174819.6258-1-alexander.kaplan@sms-medipool.de
[4] drm/dp: Service the CEC tunneling IRQ flags without CEC_IRQ in ESI1
    https://lore.kernel.org/r/20260610174833.6284-1-alexander.kaplan@sms-medipool.de

Each part can be merged independently.

Alexander


^ permalink raw reply	[flat|nested] 14+ messages in thread

* ✗ LGCI.VerificationFailed: failure for drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs
  2026-06-10 17:44 [PATCH 0/3] drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs Alexander Kaplan
                   ` (3 preceding siblings ...)
  2026-06-10 17:49 ` [PATCH 0/3] drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs Alexander Kaplan
@ 2026-06-10 18:45 ` Patchwork
  2026-06-30  0:16 ` ✓ CI.KUnit: success for drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs (rev2) Patchwork
                   ` (2 subsequent siblings)
  7 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2026-06-10 18:45 UTC (permalink / raw)
  To: Alexander Kaplan; +Cc: intel-xe

== Series Details ==

Series: drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs
URL   : https://patchwork.freedesktop.org/series/168276/
State : failure

== Summary ==

Series author address 'alexander.kaplan@sms-medipool.de' is not on the allowlist, which prevents CI from being automatically triggered.
If you want CI to run for this series, ask Patchwork project owners to click 'retest' on the series in Patchwork.
Exception occurred during validation, bailing out!
Build URL: http://intel-gfx-ci-public.igk.intel.com:8080/job/xe_pw_trigger/1185532/ (on master)



^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 1/3] drm/i915/dp: Prefer DSC over a 6 bpc uncompressed output
  2026-06-10 17:44 ` [PATCH 1/3] drm/i915/dp: Prefer DSC over a 6 bpc uncompressed output Alexander Kaplan
@ 2026-06-12 16:32   ` Imre Deak
  2026-06-12 18:46     ` Alexander Kaplan
  0 siblings, 1 reply; 14+ messages in thread
From: Imre Deak @ 2026-06-12 16:32 UTC (permalink / raw)
  To: Alexander Kaplan
  Cc: intel-gfx, intel-xe, Ankit Nautiyal, Ville Syrjälä,
	Chaitanya Kumar Borah, Nicolas Frattaroli, Jani Nikula,
	Rodrigo Vivi

On Wed, Jun 10, 2026 at 07:44:11PM +0200, Alexander Kaplan wrote:
> For modes which fit through the link uncompressed only with a 6 bpc
> pipe BPP, the link config currently selects 6 bpc with dithering even
> if the sink supports DSC.
> DSC with an at least 8 bpc input provides a better output quality
> than a dithered 6 bpc output, so prefer it, following the pattern
> commit ba49a4643cf5 ("drm/i915/dp: Set min_bpp limit to 30 in HDR
> mode") uses for HDR: keep the uncompressed minimum pipe BPP at 8 bpc
> if the sink supports DSC, making the uncompressed link config fail
> for such modes and the mode fall back to DSC.
> As there, if the DSC computation fails, the mode falls back to YCbCr
> 4:2:0 where supported, or gets rejected.
> 
> Besides the output quality, some sinks can't even display a 6 bpc
> stream at high pixel clocks.
> Synaptics VMM PCON based DP to HDMI 2.1 adapters from two device
> families (branch device IDs SYNAq and SYNAa) output corrupted FRL
> timings for an uncompressed RGB 6 bpc 4k120 (1188 MHz) stream,
> resulting in a black screen, while the same mode works with DSC
> (12 bpc input) and 6 bpc works at lower pixel clocks.
> Windows and macOS drive 4k120 on these devices only via DSC.
> 
> A lower bpc limit explicitly requested via the max bpc connector
> property is still honored.
> This keeps the current uAPI behavior (exercised by IGT kms_dither)
> and provides an escape hatch for sinks with a broken DSC
> implementation.
> Sinks without DSC support keep falling back to 6 bpc.
> 
> Tested on PTL (xe) with the above PCONs and an LG OLED G4.
> 
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Alexander Kaplan <alexander.kaplan@sms-medipool.de>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 85d3aa3b9894..13cfccf60490 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2839,6 +2839,18 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
>  								     crtc_state)));
>  	}
>  
> +	/*
> +	 * Prefer DSC with an at least 8 bpc input over a dithered 6 bpc
> +	 * uncompressed output, by failing the uncompressed link config for
> +	 * modes which would fit only with a 6 bpc pipe BPP. Honor a lower
> +	 * limit set via the max bpc connector property.
> +	 */
> +	if (!dsc &&
> +	    intel_dp_supports_dsc(intel_dp, connector, crtc_state) &&
> +	    limits->pipe.max_bpp >= 24 &&
> +	    crtc_state->pipe_bpp >= 24)
> +		limits->pipe.min_bpp = max(limits->pipe.min_bpp, 24);

So, this would be a generalization for/instead of the HDR logic above
using a intel_dp_in_hdr_mode() ? 30 : 24 limit (which would also apply a
lower max-bpc limit for HDR as well).

Agree that DSC vs. dithering would probably produce a better image.

There could be other reasons to prefer DSC, like a more finegrained BW
allocation on MST links. But there are also reasons to prefer non-DSC
mode like power saving (no need to enable either a DSC encoder in the
source or a DSC decoder downstream), or reliability issues related to
DSC.

There's been a lot of talk internally about the above aspects and how to
handle them in a way suitable in all scenarios. Hence, I'm not sure if
adding more policies to the driver like the above bpp limit/DSC
preference is too ad-hoc/early or not at this point. At some point we
will need a better logic for sure to decide between DSC or non-DSC, but
that could be based on userspace tunable knobs for instance. Maybe
someone else could also weigh in on this.

> +
>  	if (limits->pipe.min_bpp <= 0 ||
>  	    limits->pipe.min_bpp > limits->pipe.max_bpp) {
>  		drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Invalid pipe bpp range: %d-%d\n",
> -- 
> 2.54.0
> 
> 

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 1/3] drm/i915/dp: Prefer DSC over a 6 bpc uncompressed output
  2026-06-12 16:32   ` Imre Deak
@ 2026-06-12 18:46     ` Alexander Kaplan
  2026-06-29  3:59       ` Nautiyal, Ankit K
  0 siblings, 1 reply; 14+ messages in thread
From: Alexander Kaplan @ 2026-06-12 18:46 UTC (permalink / raw)
  To: Imre Deak
  Cc: intel-gfx, intel-xe, Ankit Nautiyal, Ville Syrjälä,
	Chaitanya Kumar Borah, Nicolas Frattaroli, Jani Nikula,
	Rodrigo Vivi, alexander.kaplan

On Fri, Jun 12, 2026 at 07:32:33PM +0300, Imre Deak wrote:
> So, this would be a generalization for/instead of the HDR logic above
> using a intel_dp_in_hdr_mode() ? 30 : 24 limit (which would also apply a
> lower max-bpc limit for HDR as well).

Hi Imre,

yes, it follows the same pattern as the HDR logic, with one deliberate
difference.
The extra crtc_state->pipe_bpp check makes an explicit max bpc property
request below 8 win over the new limit, so the uncompressed 6 bpc path
stays reachable.
That keeps the current uAPI behavior under IGT kms_dither and leaves an
escape hatch for sinks with a broken DSC implementation.
The HDR limit currently wins over a lower property request, so a merge
into an intel_dp_in_hdr_mode() ? 30 : 24 block would, as you say, make
HDR honor such a request as well.
If that behavior change for HDR is acceptable I am happy to merge the
two blocks in a v2, otherwise I would keep them separate.

> There could be other reasons to prefer DSC, like a more finegrained BW
> allocation on MST links. But there are also reasons to prefer non-DSC
> mode like power saving (no need to enable either a DSC encoder in the
> source or a DSC decoder downstream), or reliability issues related to
> DSC.
>
> There's been a lot of talk internally about the above aspects and how to
> handle them in a way suitable in all scenarios. Hence, I'm not sure if
> adding more policies to the driver like the above bpp limit/DSC
> preference is too ad-hoc/early or not at this point.

I understand the hesitation about adding more policy, but for this
series the patch is less a quality preference and more a dependency of
patches 2 and 3.
Those open up RGB configurations on FRL links where previously only the
4:2:0 fallback existed, and for modes like 4k120 on a 4 lane HBR3 link
the only uncompressed fit is 6 bpc.
Both tested Synaptics PCON device families output corrupted FRL timings
for exactly that configuration and the TV shows a black screen, while
the same mode works with DSC.
So without patch 1 the series would trade the previous 4:2:0 picture
for a black screen on this hardware.

I also think the 6 bpc case is narrow enough that it does not really
open the general DSC versus non-DSC question.
6 bpc is a DP and eDP panel concept, HDMI only defines 8, 10, 12 and 16
bpc output depths.
A PCON that has to forward an 18 bpp stream to an HDMI sink has no
valid HDMI output format for it, which would explain why both device
families fail in the same way.
Windows and macOS drive 4k120 on these devices via DSC, and they have
no other choice, RGB 8 bpc at a 1188 MHz pixel clock needs 28.5 Gbps
against the 25.92 Gbps payload of a 4 lane HBR3 link.
There is also precedent for forcing DSC where the uncompressed 18 bpp
path is broken, commit 55eaef164174 ("drm/i915/dp_mst: Handle the
Synaptics HBlank expansion quirk") does the same for the affected MST
docks.
And only modes which do not fit through the link at 8 bpc are affected
at all, so in the uncompressed case the link already runs at the top of
its capability.
For the power and reliability concerns the max bpc property acts as the
userspace override, setting it to 6 restores today's behavior.

If the general form is still considered too early, I could narrow the
limit to HDMI sinks behind a PCON, gating it on
intel_dp_has_hdmi_sink().
There 6 bpc is not a valid output format on the HDMI side, so the
change is a correctness fix rather than a preference, and it would
still unblock patches 2 and 3.
Just let me know which shape you prefer.

Thanks,
Alex


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 1/3] drm/i915/dp: Prefer DSC over a 6 bpc uncompressed output
  2026-06-12 18:46     ` Alexander Kaplan
@ 2026-06-29  3:59       ` Nautiyal, Ankit K
  0 siblings, 0 replies; 14+ messages in thread
From: Nautiyal, Ankit K @ 2026-06-29  3:59 UTC (permalink / raw)
  To: Alexander Kaplan, Imre Deak
  Cc: intel-gfx, intel-xe, Ville Syrjälä,
	Chaitanya Kumar Borah, Nicolas Frattaroli, Jani Nikula,
	Rodrigo Vivi


On 6/13/2026 12:16 AM, Alexander Kaplan wrote:
> On Fri, Jun 12, 2026 at 07:32:33PM +0300, Imre Deak wrote:
>> So, this would be a generalization for/instead of the HDR logic above
>> using a intel_dp_in_hdr_mode() ? 30 : 24 limit (which would also apply a
>> lower max-bpc limit for HDR as well).
> Hi Imre,
>
> yes, it follows the same pattern as the HDR logic, with one deliberate
> difference.
> The extra crtc_state->pipe_bpp check makes an explicit max bpc property
> request below 8 win over the new limit, so the uncompressed 6 bpc path
> stays reachable.
> That keeps the current uAPI behavior under IGT kms_dither and leaves an
> escape hatch for sinks with a broken DSC implementation.
> The HDR limit currently wins over a lower property request, so a merge
> into an intel_dp_in_hdr_mode() ? 30 : 24 block would, as you say, make
> HDR honor such a request as well.
> If that behavior change for HDR is acceptable I am happy to merge the
> two blocks in a v2, otherwise I would keep them separate.
>
>> There could be other reasons to prefer DSC, like a more finegrained BW
>> allocation on MST links. But there are also reasons to prefer non-DSC
>> mode like power saving (no need to enable either a DSC encoder in the
>> source or a DSC decoder downstream), or reliability issues related to
>> DSC.
>>
>> There's been a lot of talk internally about the above aspects and how to
>> handle them in a way suitable in all scenarios. Hence, I'm not sure if
>> adding more policies to the driver like the above bpp limit/DSC
>> preference is too ad-hoc/early or not at this point.
> I understand the hesitation about adding more policy, but for this
> series the patch is less a quality preference and more a dependency of
> patches 2 and 3.
> Those open up RGB configurations on FRL links where previously only the
> 4:2:0 fallback existed, and for modes like 4k120 on a 4 lane HBR3 link
> the only uncompressed fit is 6 bpc.
> Both tested Synaptics PCON device families output corrupted FRL timings
> for exactly that configuration and the TV shows a black screen, while
> the same mode works with DSC.
> So without patch 1 the series would trade the previous 4:2:0 picture
> for a black screen on this hardware.
>
> I also think the 6 bpc case is narrow enough that it does not really
> open the general DSC versus non-DSC question.
> 6 bpc is a DP and eDP panel concept, HDMI only defines 8, 10, 12 and 16
> bpc output depths.
> A PCON that has to forward an 18 bpp stream to an HDMI sink has no
> valid HDMI output format for it, which would explain why both device
> families fail in the same way.
> Windows and macOS drive 4k120 on these devices via DSC, and they have
> no other choice, RGB 8 bpc at a 1188 MHz pixel clock needs 28.5 Gbps
> against the 25.92 Gbps payload of a 4 lane HBR3 link.
> There is also precedent for forcing DSC where the uncompressed 18 bpp
> path is broken, commit 55eaef164174 ("drm/i915/dp_mst: Handle the
> Synaptics HBlank expansion quirk") does the same for the affected MST
> docks.
> And only modes which do not fit through the link at 8 bpc are affected
> at all, so in the uncompressed case the link already runs at the top of
> its capability.
> For the power and reliability concerns the max bpc property acts as the
> userspace override, setting it to 6 restores today's behavior.
>
> If the general form is still considered too early, I could narrow the
> limit to HDMI sinks behind a PCON, gating it on
> intel_dp_has_hdmi_sink().
> There 6 bpc is not a valid output format on the HDMI side, so the
> change is a correctness fix rather than a preference, and it would
> still unblock patches 2 and 3.

I agree to this part. As you have noted, since HDMI does not accept 6 
bpc, we should narrow down the check to HDMI sinks behind a DFP.

Regards,

Ankit


> Just let me know which shape you prefer.
>
> Thanks,
> Alex
>

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 2/3] drm/i915/dp: Ignore the sink's DSC max FRL rate without a PCON DSC encoder
  2026-06-10 17:44 ` [PATCH 2/3] drm/i915/dp: Ignore the sink's DSC max FRL rate without a PCON DSC encoder Alexander Kaplan
@ 2026-06-29  4:01   ` Nautiyal, Ankit K
  0 siblings, 0 replies; 14+ messages in thread
From: Nautiyal, Ankit K @ 2026-06-29  4:01 UTC (permalink / raw)
  To: Alexander Kaplan, intel-gfx, intel-xe
  Cc: Ville Syrjälä, Imre Deak, Chaitanya Kumar Borah,
	Nicolas Frattaroli, Jani Nikula, Rodrigo Vivi


On 6/10/2026 11:14 PM, Alexander Kaplan wrote:
> intel_dp_hdmi_sink_max_frl() limits the sink's max FRL rate by its
> DSC max FRL rate whenever the sink supports DSC 1.2.
> However, the DSC max FRL rate (HF-VSDB DSC_Max_FRL_Rate) only applies
> to compressed video transport, which requires a DSC 1.2 encoder in
> the PCON (configured via intel_dp_pcon_dsc_configure()).
> Without such an encoder the HDMI link always carries uncompressed
> video, for which the regular Max_FRL_Rate is the correct limit.
>
> Applying the DSC limit unconditionally trains the FRL link at a lower
> rate than both the PCON and the sink support.
> E.g. an LG OLED G4 (Max_FRL_Rate 48 Gbps, DSC_Max_FRL_Rate 24 Gbps)
> behind a Synaptics VMM7100 PCON (PCON max FRL bw 48 Gbps, no DSC
> encoder):
>
>    Sink max rate from EDID = 24 Gbps
>    FRL trained with : 24 Gbps
>
> while Windows/macOS train the same hardware at 40/48 Gbps.
> The too low FRL rate needlessly constrains the formats available to
> the sink.
>
> Only apply the sink's DSC max FRL rate if the PCON has a DSC 1.2
> encoder, matching the gate in intel_dp_pcon_dsc_configure().
> PCONs with a DSC encoder keep the current conservative behavior,
> since the link is trained once and compressed transport may be used
> for any subsequent mode.
> With this the setup above trains at 48 Gbps.
>
> Tested on PTL (xe) with the above PCON/sink combo.
>
> Fixes: 10fec80b48c5 ("drm/i915/display: Configure PCON for DSC1.1 to DSC1.2 encoding")
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Alexander Kaplan <alexander.kaplan@sms-medipool.de>
> ---
>   drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++++-
>   1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 13cfccf60490..2831b274d88a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4254,7 +4254,14 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
>   	rate_per_lane = info->hdmi.max_frl_rate_per_lane;
>   	max_frl_rate = max_lanes * rate_per_lane;
>   
> -	if (info->hdmi.dsc_cap.v_1p2) {
> +	/*
> +	 * The sink's DSC max FRL rate only applies to compressed video
> +	 * transport, which requires a DSC 1.2 encoder in the PCON. Without
> +	 * one the HDMI link always carries uncompressed video, for which
> +	 * the regular max FRL rate is the limit.
> +	 */
> +	if (drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) &&
> +	    info->hdmi.dsc_cap.v_1p2) {

Yes, this is very much needed.

This condition could be factored into a separate helper, but that can be 
a separate patch.

Patch looks good to me as it is.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


>   		max_dsc_lanes = info->hdmi.dsc_cap.max_lanes;
>   		dsc_rate_per_lane = info->hdmi.dsc_cap.max_frl_rate_per_lane;
>   		if (max_dsc_lanes && dsc_rate_per_lane)

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 3/3] drm/i915/dp: Check FRL bandwidth limits in the HDMI bpc computation
  2026-06-10 17:44 ` [PATCH 3/3] drm/i915/dp: Check FRL bandwidth limits in the HDMI bpc computation Alexander Kaplan
@ 2026-06-29  4:16   ` Nautiyal, Ankit K
  0 siblings, 0 replies; 14+ messages in thread
From: Nautiyal, Ankit K @ 2026-06-29  4:16 UTC (permalink / raw)
  To: Alexander Kaplan, intel-gfx, intel-xe
  Cc: Ville Syrjälä, Imre Deak, Chaitanya Kumar Borah,
	Nicolas Frattaroli, Jani Nikula, Rodrigo Vivi


On 6/10/2026 11:14 PM, Alexander Kaplan wrote:
> The bpc computation for HDMI sinks behind a DP branch device
> (intel_dp_hdmi_compute_bpc()) validates each bpc candidate against
> the sink's TMDS character rate limits, even if the video will be
> transmitted over an FRL link, where those limits don't apply.
>
> This caps such sinks at 8bpc whenever a deep color mode's
> TMDS-equivalent character rate exceeds the TMDS limit, although the
> FRL link has plenty of bandwidth.
> E.g. 4k60 RGB 10bpc corresponds to a ~742 MHz TMDS character rate,
> above the typical 600 MHz limit, but only needs ~17.8 Gbps of e.g. a
> 48 Gbps FRL link.
> Modes whose rate exceeds the TMDS limit already at 8bpc (e.g. 4k120)
> are additionally forced from RGB to YCbCr 4:2:0 output.
>
> If both the PCON and the sink support FRL, validate the required
> bandwidth against the FRL bandwidth the link will be trained with
> (the same min() of the PCON's and the sink's max FRL rate that
> intel_dp_pcon_start_frl_training() uses) instead of the TMDS limits.
> This mirrors how intel_dp_mode_valid_downstream() already validates
> modes against the FRL bandwidth for such sinks.
> Sinks without FRL support behind an FRL capable PCON keep using the
> TMDS limits, since the PCON transmits to them in TMDS mode.
>
> The sink's deep color EDID capabilities still apply via
> intel_hdmi_bpc_possible(), and the DP link side limits are handled
> separately, as before.
>
> intel_dp_mode_valid_downstream() currently checks the FRL bandwidth
> only against the PCON's limit and also skips the TMDS checks for
> non-FRL sinks behind an FRL capable PCON.
> Aligning it with the limit used here is left for a separate change.
>
> Tested on PTL (xe) with a Synaptics VMM7100 PCON and an LG OLED G4:
> 4k60 goes from RGB 8bpc (dithered 6bpc pipe) to RGB 12bpc with HDR,
> matching macOS (12bpc) and Windows (10bpc) on the same hardware.

Thanks for the patches, and for the testing on real PCON hardware.

Yeah, the PCON mode_valid/bpc path needs an overhaul here.

The fix is correct i.e. the compute_bpc shouldn't apply TMDS limits on 
an FRL link.

But it covers only part of the problem:

  - It fixes only intel_dp_hdmi_compute_bpc() and leaves

    intel_dp_mode_valid_downstream() on the old PCON-only FRL check

   (as you have also mentioned in the commit message).

- frl_required_bw() is uncompressed-only, so modes that would only

   fit via PCON DSC (where both PCON and sink support it) still get 
rejected.


I had sent a few patches to address these sometime ago, but didnt go 
through [1] [2].

This patch overlaps with my earlier 2023 series [1] which fixes both 
compute_bpc and mode_valid via a common wrapper.

I've since extended these with the PCON DSC bandwidth handling [3] and 
I'm about to post the updated series once I'm done testing, I'll Cc you.

Since these touch the same paths, it'd be good to converge there rather 
than land overlapping changes.

Feel free to take a look once it's out. A Tested-by from you on the PCON 
hardware would be very welcome.


[1] https://patchwork.freedesktop.org/series/107550/

[2] https://patchwork.freedesktop.org/series/99311/

[3] https://patchwork.freedesktop.org/series/169372/ (trybot)


Thanks & Regards,

Ankit

>
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Alexander Kaplan <alexander.kaplan@sms-medipool.de>
> ---
>   drivers/gpu/drm/i915/display/intel_dp.c | 37 ++++++++++++++++++++++++-
>   1 file changed, 36 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2831b274d88a..511d99326af4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -124,6 +124,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
>   }
>   
>   static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> +static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp);
>   
>   /* Is link rate UHBR and thus 128b/132b? */
>   bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
> @@ -1347,6 +1348,40 @@ static int frl_required_bw(int clock, int bpc,
>   	return clock * bpc * 3;
>   }
>   
> +static enum drm_mode_status
> +intel_dp_hdmi_clock_valid(struct intel_dp *intel_dp,
> +			  int clock, int bpc,
> +			  enum intel_output_format sink_format,
> +			  bool respect_downstream_limits)
> +{
> +	int max_frl_bw;
> +
> +	if (!respect_downstream_limits)
> +		return MODE_OK;
> +
> +	/* The FRL bandwidth the link will be trained with */
> +	max_frl_bw = min(intel_dp->dfp.pcon_max_frl_bw,
> +			 intel_dp_hdmi_sink_max_frl(intel_dp));
> +
> +	/*
> +	 * If both the PCON and the sink support FRL, the PCON transmits
> +	 * to the sink in FRL mode, where the TMDS character rate limits
> +	 * don't apply.
> +	 */
> +	if (max_frl_bw > 0) {
> +		/* converting bw from Gbps to Kbps */
> +		max_frl_bw = max_frl_bw * 1000000;
> +
> +		if (frl_required_bw(clock, bpc, sink_format) > max_frl_bw)
> +			return MODE_CLOCK_HIGH;
> +
> +		return MODE_OK;
> +	}
> +
> +	return intel_dp_tmds_clock_valid(intel_dp, clock, bpc,
> +					 sink_format, respect_downstream_limits);
> +}
> +
>   static enum drm_mode_status
>   intel_dp_mode_valid_downstream(struct intel_connector *connector,
>   			       const struct drm_display_mode *mode,
> @@ -1831,7 +1866,7 @@ static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
>   	for (; bpc >= 8; bpc -= 2) {
>   		if (intel_hdmi_bpc_possible(crtc_state, bpc,
>   					    intel_dp_has_hdmi_sink(intel_dp)) &&
> -		    intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
> +		    intel_dp_hdmi_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
>   					      respect_downstream_limits) == MODE_OK)
>   			return bpc;
>   	}

^ permalink raw reply	[flat|nested] 14+ messages in thread

* ✓ CI.KUnit: success for drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs (rev2)
  2026-06-10 17:44 [PATCH 0/3] drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs Alexander Kaplan
                   ` (4 preceding siblings ...)
  2026-06-10 18:45 ` ✗ LGCI.VerificationFailed: failure for " Patchwork
@ 2026-06-30  0:16 ` Patchwork
  2026-06-30  0:53 ` ✓ Xe.CI.BAT: " Patchwork
  2026-06-30 13:18 ` ✓ Xe.CI.FULL: " Patchwork
  7 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2026-06-30  0:16 UTC (permalink / raw)
  To: Alexander Kaplan; +Cc: intel-xe

== Series Details ==

Series: drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs (rev2)
URL   : https://patchwork.freedesktop.org/series/168276/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[00:15:06] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[00:15:10] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[00:15:42] Starting KUnit Kernel (1/1)...
[00:15:42] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[00:15:42] ================== guc_buf (11 subtests) ===================
[00:15:42] [PASSED] test_smallest
[00:15:42] [PASSED] test_largest
[00:15:42] [PASSED] test_granular
[00:15:42] [PASSED] test_unique
[00:15:42] [PASSED] test_overlap
[00:15:42] [PASSED] test_reusable
[00:15:42] [PASSED] test_too_big
[00:15:42] [PASSED] test_flush
[00:15:42] [PASSED] test_lookup
[00:15:42] [PASSED] test_data
[00:15:42] [PASSED] test_class
[00:15:42] ===================== [PASSED] guc_buf =====================
[00:15:42] =================== guc_dbm (7 subtests) ===================
[00:15:42] [PASSED] test_empty
[00:15:42] [PASSED] test_default
[00:15:42] ======================== test_size  ========================
[00:15:42] [PASSED] 4
[00:15:42] [PASSED] 8
[00:15:42] [PASSED] 32
[00:15:42] [PASSED] 256
[00:15:42] ==================== [PASSED] test_size ====================
[00:15:42] ======================= test_reuse  ========================
[00:15:42] [PASSED] 4
[00:15:42] [PASSED] 8
[00:15:42] [PASSED] 32
[00:15:42] [PASSED] 256
[00:15:42] =================== [PASSED] test_reuse ====================
[00:15:42] =================== test_range_overlap  ====================
[00:15:42] [PASSED] 4
[00:15:42] [PASSED] 8
[00:15:42] [PASSED] 32
[00:15:42] [PASSED] 256
[00:15:42] =============== [PASSED] test_range_overlap ================
[00:15:42] =================== test_range_compact  ====================
[00:15:42] [PASSED] 4
[00:15:42] [PASSED] 8
[00:15:42] [PASSED] 32
[00:15:42] [PASSED] 256
[00:15:42] =============== [PASSED] test_range_compact ================
[00:15:42] ==================== test_range_spare  =====================
[00:15:42] [PASSED] 4
[00:15:42] [PASSED] 8
[00:15:42] [PASSED] 32
[00:15:42] [PASSED] 256
[00:15:42] ================ [PASSED] test_range_spare =================
[00:15:42] ===================== [PASSED] guc_dbm =====================
[00:15:42] =================== guc_idm (6 subtests) ===================
[00:15:42] [PASSED] bad_init
[00:15:42] [PASSED] no_init
[00:15:42] [PASSED] init_fini
[00:15:42] [PASSED] check_used
[00:15:42] [PASSED] check_quota
[00:15:42] [PASSED] check_all
[00:15:42] ===================== [PASSED] guc_idm =====================
[00:15:42] ================== no_relay (3 subtests) ===================
[00:15:42] [PASSED] xe_drops_guc2pf_if_not_ready
[00:15:42] [PASSED] xe_drops_guc2vf_if_not_ready
[00:15:42] [PASSED] xe_rejects_send_if_not_ready
[00:15:42] ==================== [PASSED] no_relay =====================
[00:15:42] ================== pf_relay (14 subtests) ==================
[00:15:42] [PASSED] pf_rejects_guc2pf_too_short
[00:15:42] [PASSED] pf_rejects_guc2pf_too_long
[00:15:42] [PASSED] pf_rejects_guc2pf_no_payload
[00:15:42] [PASSED] pf_fails_no_payload
[00:15:42] [PASSED] pf_fails_bad_origin
[00:15:42] [PASSED] pf_fails_bad_type
[00:15:42] [PASSED] pf_txn_reports_error
[00:15:42] [PASSED] pf_txn_sends_pf2guc
[00:15:42] [PASSED] pf_sends_pf2guc
[00:15:42] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[00:15:42] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[00:15:42] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[00:15:42] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[00:15:42] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[00:15:42] ==================== [PASSED] pf_relay =====================
[00:15:42] ================== vf_relay (3 subtests) ===================
[00:15:42] [PASSED] vf_rejects_guc2vf_too_short
[00:15:42] [PASSED] vf_rejects_guc2vf_too_long
[00:15:42] [PASSED] vf_rejects_guc2vf_no_payload
[00:15:42] ==================== [PASSED] vf_relay =====================
[00:15:42] ================ pf_gt_config (9 subtests) =================
[00:15:42] [PASSED] fair_contexts_1vf
[00:15:42] [PASSED] fair_doorbells_1vf
[00:15:42] [PASSED] fair_ggtt_1vf
[00:15:42] ====================== fair_vram_1vf  ======================
[00:15:42] [PASSED] 3.50 GiB
[00:15:42] [PASSED] 11.5 GiB
[00:15:42] [PASSED] 15.5 GiB
[00:15:42] [PASSED] 31.5 GiB
[00:15:42] [PASSED] 63.5 GiB
[00:15:42] [PASSED] 1.91 GiB
[00:15:42] ================== [PASSED] fair_vram_1vf ==================
[00:15:42] ================ fair_vram_1vf_admin_only  =================
[00:15:42] [PASSED] 3.50 GiB
[00:15:42] [PASSED] 11.5 GiB
[00:15:42] [PASSED] 15.5 GiB
[00:15:42] [PASSED] 31.5 GiB
[00:15:42] [PASSED] 63.5 GiB
[00:15:42] [PASSED] 1.91 GiB
[00:15:42] ============ [PASSED] fair_vram_1vf_admin_only =============
[00:15:42] ====================== fair_contexts  ======================
[00:15:42] [PASSED] 1 VF
[00:15:42] [PASSED] 2 VFs
[00:15:42] [PASSED] 3 VFs
[00:15:42] [PASSED] 4 VFs
[00:15:42] [PASSED] 5 VFs
[00:15:42] [PASSED] 6 VFs
[00:15:42] [PASSED] 7 VFs
[00:15:42] [PASSED] 8 VFs
[00:15:42] [PASSED] 9 VFs
[00:15:42] [PASSED] 10 VFs
[00:15:42] [PASSED] 11 VFs
[00:15:42] [PASSED] 12 VFs
[00:15:42] [PASSED] 13 VFs
[00:15:42] [PASSED] 14 VFs
[00:15:42] [PASSED] 15 VFs
[00:15:42] [PASSED] 16 VFs
[00:15:42] [PASSED] 17 VFs
[00:15:42] [PASSED] 18 VFs
[00:15:42] [PASSED] 19 VFs
[00:15:42] [PASSED] 20 VFs
[00:15:42] [PASSED] 21 VFs
[00:15:42] [PASSED] 22 VFs
[00:15:42] [PASSED] 23 VFs
[00:15:42] [PASSED] 24 VFs
[00:15:42] [PASSED] 25 VFs
[00:15:42] [PASSED] 26 VFs
[00:15:42] [PASSED] 27 VFs
[00:15:42] [PASSED] 28 VFs
[00:15:42] [PASSED] 29 VFs
[00:15:42] [PASSED] 30 VFs
[00:15:42] [PASSED] 31 VFs
[00:15:42] [PASSED] 32 VFs
[00:15:42] [PASSED] 33 VFs
[00:15:42] [PASSED] 34 VFs
[00:15:42] [PASSED] 35 VFs
[00:15:42] [PASSED] 36 VFs
[00:15:42] [PASSED] 37 VFs
[00:15:42] [PASSED] 38 VFs
[00:15:42] [PASSED] 39 VFs
[00:15:42] [PASSED] 40 VFs
[00:15:42] [PASSED] 41 VFs
[00:15:42] [PASSED] 42 VFs
[00:15:42] [PASSED] 43 VFs
[00:15:42] [PASSED] 44 VFs
[00:15:42] [PASSED] 45 VFs
[00:15:42] [PASSED] 46 VFs
[00:15:42] [PASSED] 47 VFs
[00:15:42] [PASSED] 48 VFs
[00:15:42] [PASSED] 49 VFs
[00:15:42] [PASSED] 50 VFs
[00:15:42] [PASSED] 51 VFs
[00:15:42] [PASSED] 52 VFs
[00:15:42] [PASSED] 53 VFs
[00:15:42] [PASSED] 54 VFs
[00:15:42] [PASSED] 55 VFs
[00:15:42] [PASSED] 56 VFs
[00:15:42] [PASSED] 57 VFs
[00:15:42] [PASSED] 58 VFs
[00:15:42] [PASSED] 59 VFs
[00:15:42] [PASSED] 60 VFs
[00:15:42] [PASSED] 61 VFs
[00:15:42] [PASSED] 62 VFs
[00:15:42] [PASSED] 63 VFs
[00:15:42] ================== [PASSED] fair_contexts ==================
[00:15:42] ===================== fair_doorbells  ======================
[00:15:42] [PASSED] 1 VF
[00:15:42] [PASSED] 2 VFs
[00:15:42] [PASSED] 3 VFs
[00:15:42] [PASSED] 4 VFs
[00:15:42] [PASSED] 5 VFs
[00:15:42] [PASSED] 6 VFs
[00:15:42] [PASSED] 7 VFs
[00:15:42] [PASSED] 8 VFs
[00:15:42] [PASSED] 9 VFs
[00:15:42] [PASSED] 10 VFs
[00:15:42] [PASSED] 11 VFs
[00:15:42] [PASSED] 12 VFs
[00:15:42] [PASSED] 13 VFs
[00:15:42] [PASSED] 14 VFs
[00:15:42] [PASSED] 15 VFs
[00:15:42] [PASSED] 16 VFs
[00:15:42] [PASSED] 17 VFs
[00:15:42] [PASSED] 18 VFs
[00:15:42] [PASSED] 19 VFs
[00:15:42] [PASSED] 20 VFs
[00:15:42] [PASSED] 21 VFs
[00:15:42] [PASSED] 22 VFs
[00:15:42] [PASSED] 23 VFs
[00:15:42] [PASSED] 24 VFs
[00:15:42] [PASSED] 25 VFs
[00:15:42] [PASSED] 26 VFs
[00:15:42] [PASSED] 27 VFs
[00:15:42] [PASSED] 28 VFs
[00:15:42] [PASSED] 29 VFs
[00:15:42] [PASSED] 30 VFs
[00:15:42] [PASSED] 31 VFs
[00:15:42] [PASSED] 32 VFs
[00:15:42] [PASSED] 33 VFs
[00:15:42] [PASSED] 34 VFs
[00:15:42] [PASSED] 35 VFs
[00:15:42] [PASSED] 36 VFs
[00:15:42] [PASSED] 37 VFs
[00:15:42] [PASSED] 38 VFs
[00:15:42] [PASSED] 39 VFs
[00:15:42] [PASSED] 40 VFs
[00:15:42] [PASSED] 41 VFs
[00:15:42] [PASSED] 42 VFs
[00:15:42] [PASSED] 43 VFs
[00:15:42] [PASSED] 44 VFs
[00:15:42] [PASSED] 45 VFs
[00:15:42] [PASSED] 46 VFs
[00:15:42] [PASSED] 47 VFs
[00:15:42] [PASSED] 48 VFs
[00:15:42] [PASSED] 49 VFs
[00:15:42] [PASSED] 50 VFs
[00:15:42] [PASSED] 51 VFs
[00:15:42] [PASSED] 52 VFs
[00:15:42] [PASSED] 53 VFs
[00:15:42] [PASSED] 54 VFs
[00:15:42] [PASSED] 55 VFs
[00:15:42] [PASSED] 56 VFs
[00:15:42] [PASSED] 57 VFs
[00:15:42] [PASSED] 58 VFs
[00:15:42] [PASSED] 59 VFs
[00:15:42] [PASSED] 60 VFs
[00:15:42] [PASSED] 61 VFs
[00:15:42] [PASSED] 62 VFs
[00:15:42] [PASSED] 63 VFs
[00:15:42] ================= [PASSED] fair_doorbells ==================
[00:15:42] ======================== fair_ggtt  ========================
[00:15:42] [PASSED] 1 VF
[00:15:42] [PASSED] 2 VFs
[00:15:42] [PASSED] 3 VFs
[00:15:42] [PASSED] 4 VFs
[00:15:42] [PASSED] 5 VFs
[00:15:42] [PASSED] 6 VFs
[00:15:42] [PASSED] 7 VFs
[00:15:42] [PASSED] 8 VFs
[00:15:42] [PASSED] 9 VFs
[00:15:42] [PASSED] 10 VFs
[00:15:42] [PASSED] 11 VFs
[00:15:42] [PASSED] 12 VFs
[00:15:42] [PASSED] 13 VFs
[00:15:42] [PASSED] 14 VFs
[00:15:42] [PASSED] 15 VFs
[00:15:42] [PASSED] 16 VFs
[00:15:42] [PASSED] 17 VFs
[00:15:42] [PASSED] 18 VFs
[00:15:42] [PASSED] 19 VFs
[00:15:42] [PASSED] 20 VFs
[00:15:42] [PASSED] 21 VFs
[00:15:42] [PASSED] 22 VFs
[00:15:42] [PASSED] 23 VFs
[00:15:42] [PASSED] 24 VFs
[00:15:42] [PASSED] 25 VFs
[00:15:42] [PASSED] 26 VFs
[00:15:42] [PASSED] 27 VFs
[00:15:42] [PASSED] 28 VFs
[00:15:42] [PASSED] 29 VFs
[00:15:42] [PASSED] 30 VFs
[00:15:42] [PASSED] 31 VFs
[00:15:42] [PASSED] 32 VFs
[00:15:42] [PASSED] 33 VFs
[00:15:42] [PASSED] 34 VFs
[00:15:42] [PASSED] 35 VFs
[00:15:42] [PASSED] 36 VFs
[00:15:42] [PASSED] 37 VFs
[00:15:42] [PASSED] 38 VFs
[00:15:42] [PASSED] 39 VFs
[00:15:42] [PASSED] 40 VFs
[00:15:42] [PASSED] 41 VFs
[00:15:42] [PASSED] 42 VFs
[00:15:42] [PASSED] 43 VFs
[00:15:42] [PASSED] 44 VFs
[00:15:42] [PASSED] 45 VFs
[00:15:42] [PASSED] 46 VFs
[00:15:42] [PASSED] 47 VFs
[00:15:42] [PASSED] 48 VFs
[00:15:42] [PASSED] 49 VFs
[00:15:42] [PASSED] 50 VFs
[00:15:42] [PASSED] 51 VFs
[00:15:42] [PASSED] 52 VFs
[00:15:42] [PASSED] 53 VFs
[00:15:42] [PASSED] 54 VFs
[00:15:42] [PASSED] 55 VFs
[00:15:42] [PASSED] 56 VFs
[00:15:42] [PASSED] 57 VFs
[00:15:42] [PASSED] 58 VFs
[00:15:42] [PASSED] 59 VFs
[00:15:42] [PASSED] 60 VFs
[00:15:42] [PASSED] 61 VFs
[00:15:42] [PASSED] 62 VFs
[00:15:42] [PASSED] 63 VFs
[00:15:42] ==================== [PASSED] fair_ggtt ====================
[00:15:42] ======================== fair_vram  ========================
[00:15:42] [PASSED] 1 VF
[00:15:42] [PASSED] 2 VFs
[00:15:42] [PASSED] 3 VFs
[00:15:42] [PASSED] 4 VFs
[00:15:42] [PASSED] 5 VFs
[00:15:42] [PASSED] 6 VFs
[00:15:42] [PASSED] 7 VFs
[00:15:42] [PASSED] 8 VFs
[00:15:42] [PASSED] 9 VFs
[00:15:42] [PASSED] 10 VFs
[00:15:42] [PASSED] 11 VFs
[00:15:42] [PASSED] 12 VFs
[00:15:42] [PASSED] 13 VFs
[00:15:42] [PASSED] 14 VFs
[00:15:42] [PASSED] 15 VFs
[00:15:42] [PASSED] 16 VFs
[00:15:42] [PASSED] 17 VFs
[00:15:42] [PASSED] 18 VFs
[00:15:42] [PASSED] 19 VFs
[00:15:42] [PASSED] 20 VFs
[00:15:42] [PASSED] 21 VFs
[00:15:42] [PASSED] 22 VFs
[00:15:42] [PASSED] 23 VFs
[00:15:42] [PASSED] 24 VFs
[00:15:42] [PASSED] 25 VFs
[00:15:42] [PASSED] 26 VFs
[00:15:42] [PASSED] 27 VFs
[00:15:42] [PASSED] 28 VFs
[00:15:42] [PASSED] 29 VFs
[00:15:42] [PASSED] 30 VFs
[00:15:42] [PASSED] 31 VFs
[00:15:42] [PASSED] 32 VFs
[00:15:42] [PASSED] 33 VFs
[00:15:42] [PASSED] 34 VFs
[00:15:42] [PASSED] 35 VFs
[00:15:42] [PASSED] 36 VFs
[00:15:42] [PASSED] 37 VFs
[00:15:42] [PASSED] 38 VFs
[00:15:42] [PASSED] 39 VFs
[00:15:42] [PASSED] 40 VFs
[00:15:42] [PASSED] 41 VFs
[00:15:42] [PASSED] 42 VFs
[00:15:42] [PASSED] 43 VFs
[00:15:42] [PASSED] 44 VFs
[00:15:42] [PASSED] 45 VFs
[00:15:42] [PASSED] 46 VFs
[00:15:42] [PASSED] 47 VFs
[00:15:42] [PASSED] 48 VFs
[00:15:42] [PASSED] 49 VFs
[00:15:42] [PASSED] 50 VFs
[00:15:42] [PASSED] 51 VFs
[00:15:42] [PASSED] 52 VFs
[00:15:42] [PASSED] 53 VFs
[00:15:42] [PASSED] 54 VFs
[00:15:42] [PASSED] 55 VFs
[00:15:42] [PASSED] 56 VFs
[00:15:42] [PASSED] 57 VFs
[00:15:42] [PASSED] 58 VFs
[00:15:42] [PASSED] 59 VFs
[00:15:42] [PASSED] 60 VFs
[00:15:42] [PASSED] 61 VFs
[00:15:42] [PASSED] 62 VFs
[00:15:42] [PASSED] 63 VFs
[00:15:42] ==================== [PASSED] fair_vram ====================
[00:15:42] ================== [PASSED] pf_gt_config ===================
[00:15:42] ===================== lmtt (1 subtest) =====================
[00:15:42] ======================== test_ops  =========================
[00:15:42] [PASSED] 2-level
[00:15:42] [PASSED] multi-level
[00:15:42] ==================== [PASSED] test_ops =====================
[00:15:42] ====================== [PASSED] lmtt =======================
[00:15:42] ================= pf_service (11 subtests) =================
[00:15:42] [PASSED] pf_negotiate_any
[00:15:42] [PASSED] pf_negotiate_base_match
[00:15:42] [PASSED] pf_negotiate_base_newer
[00:15:42] [PASSED] pf_negotiate_base_next
[00:15:42] [SKIPPED] pf_negotiate_base_older (no older minor)
[00:15:42] [PASSED] pf_negotiate_base_prev
[00:15:42] [PASSED] pf_negotiate_latest_match
[00:15:42] [PASSED] pf_negotiate_latest_newer
[00:15:42] [PASSED] pf_negotiate_latest_next
[00:15:42] [SKIPPED] pf_negotiate_latest_older (no older minor)
[00:15:42] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[00:15:42] =================== [PASSED] pf_service ====================
[00:15:42] ================= xe_guc_g2g (2 subtests) ==================
[00:15:42] ============== xe_live_guc_g2g_kunit_default  ==============
[00:15:42] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[00:15:42] ============== xe_live_guc_g2g_kunit_allmem  ===============
[00:15:42] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[00:15:42] =================== [SKIPPED] xe_guc_g2g ===================
[00:15:42] =================== xe_mocs (2 subtests) ===================
[00:15:42] ================ xe_live_mocs_kernel_kunit  ================
[00:15:42] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[00:15:42] ================ xe_live_mocs_reset_kunit  =================
[00:15:42] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[00:15:42] ==================== [SKIPPED] xe_mocs =====================
[00:15:42] ================= xe_migrate (2 subtests) ==================
[00:15:42] ================= xe_migrate_sanity_kunit  =================
[00:15:42] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[00:15:42] ================== xe_validate_ccs_kunit  ==================
[00:15:42] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[00:15:42] =================== [SKIPPED] xe_migrate ===================
[00:15:42] ================== xe_dma_buf (1 subtest) ==================
[00:15:42] ==================== xe_dma_buf_kunit  =====================
[00:15:42] ================ [SKIPPED] xe_dma_buf_kunit ================
[00:15:42] =================== [SKIPPED] xe_dma_buf ===================
[00:15:42] ================= xe_bo_shrink (1 subtest) =================
[00:15:42] =================== xe_bo_shrink_kunit  ====================
[00:15:42] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[00:15:42] ================== [SKIPPED] xe_bo_shrink ==================
[00:15:42] ==================== xe_bo (2 subtests) ====================
[00:15:42] ================== xe_ccs_migrate_kunit  ===================
[00:15:42] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[00:15:42] ==================== xe_bo_evict_kunit  ====================
[00:15:42] =============== [SKIPPED] xe_bo_evict_kunit ================
[00:15:42] ===================== [SKIPPED] xe_bo ======================
[00:15:42] ==================== args (13 subtests) ====================
[00:15:42] [PASSED] count_args_test
[00:15:42] [PASSED] call_args_example
[00:15:42] [PASSED] call_args_test
[00:15:42] [PASSED] drop_first_arg_example
[00:15:42] [PASSED] drop_first_arg_test
[00:15:42] [PASSED] first_arg_example
[00:15:42] [PASSED] first_arg_test
[00:15:42] [PASSED] last_arg_example
[00:15:42] [PASSED] last_arg_test
[00:15:42] [PASSED] pick_arg_example
[00:15:42] [PASSED] if_args_example
[00:15:42] [PASSED] if_args_test
[00:15:42] [PASSED] sep_comma_example
[00:15:42] ====================== [PASSED] args =======================
[00:15:42] =================== xe_pci (3 subtests) ====================
[00:15:42] ==================== check_graphics_ip  ====================
[00:15:42] [PASSED] 12.00 Xe_LP
[00:15:42] [PASSED] 12.10 Xe_LP+
[00:15:42] [PASSED] 12.55 Xe_HPG
[00:15:42] [PASSED] 12.60 Xe_HPC
[00:15:42] [PASSED] 12.70 Xe_LPG
[00:15:42] [PASSED] 12.71 Xe_LPG
[00:15:42] [PASSED] 12.74 Xe_LPG+
[00:15:42] [PASSED] 20.01 Xe2_HPG
[00:15:42] [PASSED] 20.02 Xe2_HPG
[00:15:42] [PASSED] 20.04 Xe2_LPG
[00:15:42] [PASSED] 30.00 Xe3_LPG
[00:15:42] [PASSED] 30.01 Xe3_LPG
[00:15:42] [PASSED] 30.03 Xe3_LPG
[00:15:42] [PASSED] 30.04 Xe3_LPG
[00:15:42] [PASSED] 30.05 Xe3_LPG
[00:15:42] [PASSED] 35.10 Xe3p_LPG
[00:15:42] [PASSED] 35.11 Xe3p_XPC
[00:15:42] ================ [PASSED] check_graphics_ip ================
[00:15:42] ===================== check_media_ip  ======================
[00:15:42] [PASSED] 12.00 Xe_M
[00:15:42] [PASSED] 12.55 Xe_HPM
[00:15:42] [PASSED] 13.00 Xe_LPM+
[00:15:42] [PASSED] 13.01 Xe2_HPM
[00:15:42] [PASSED] 20.00 Xe2_LPM
[00:15:42] [PASSED] 30.00 Xe3_LPM
[00:15:42] [PASSED] 30.02 Xe3_LPM
[00:15:42] [PASSED] 35.00 Xe3p_LPM
[00:15:42] [PASSED] 35.03 Xe3p_HPM
[00:15:42] ================= [PASSED] check_media_ip ==================
[00:15:42] =================== check_platform_desc  ===================
[00:15:42] [PASSED] 0x9A60 (TIGERLAKE)
[00:15:42] [PASSED] 0x9A68 (TIGERLAKE)
[00:15:42] [PASSED] 0x9A70 (TIGERLAKE)
[00:15:42] [PASSED] 0x9A40 (TIGERLAKE)
[00:15:42] [PASSED] 0x9A49 (TIGERLAKE)
[00:15:42] [PASSED] 0x9A59 (TIGERLAKE)
[00:15:42] [PASSED] 0x9A78 (TIGERLAKE)
[00:15:42] [PASSED] 0x9AC0 (TIGERLAKE)
[00:15:42] [PASSED] 0x9AC9 (TIGERLAKE)
[00:15:42] [PASSED] 0x9AD9 (TIGERLAKE)
[00:15:42] [PASSED] 0x9AF8 (TIGERLAKE)
[00:15:42] [PASSED] 0x4C80 (ROCKETLAKE)
[00:15:42] [PASSED] 0x4C8A (ROCKETLAKE)
[00:15:42] [PASSED] 0x4C8B (ROCKETLAKE)
[00:15:42] [PASSED] 0x4C8C (ROCKETLAKE)
[00:15:42] [PASSED] 0x4C90 (ROCKETLAKE)
[00:15:42] [PASSED] 0x4C9A (ROCKETLAKE)
[00:15:42] [PASSED] 0x4680 (ALDERLAKE_S)
[00:15:42] [PASSED] 0x4682 (ALDERLAKE_S)
[00:15:42] [PASSED] 0x4688 (ALDERLAKE_S)
[00:15:42] [PASSED] 0x468A (ALDERLAKE_S)
[00:15:42] [PASSED] 0x468B (ALDERLAKE_S)
[00:15:42] [PASSED] 0x4690 (ALDERLAKE_S)
[00:15:42] [PASSED] 0x4692 (ALDERLAKE_S)
[00:15:42] [PASSED] 0x4693 (ALDERLAKE_S)
[00:15:42] [PASSED] 0x46A0 (ALDERLAKE_P)
[00:15:42] [PASSED] 0x46A1 (ALDERLAKE_P)
[00:15:42] [PASSED] 0x46A2 (ALDERLAKE_P)
[00:15:42] [PASSED] 0x46A3 (ALDERLAKE_P)
[00:15:42] [PASSED] 0x46A6 (ALDERLAKE_P)
[00:15:42] [PASSED] 0x46A8 (ALDERLAKE_P)
[00:15:42] [PASSED] 0x46AA (ALDERLAKE_P)
[00:15:42] [PASSED] 0x462A (ALDERLAKE_P)
[00:15:42] [PASSED] 0x4626 (ALDERLAKE_P)
[00:15:42] [PASSED] 0x4628 (ALDERLAKE_P)
[00:15:42] [PASSED] 0x46B0 (ALDERLAKE_P)
[00:15:42] [PASSED] 0x46B1 (ALDERLAKE_P)
[00:15:42] [PASSED] 0x46B2 (ALDERLAKE_P)
[00:15:42] [PASSED] 0x46B3 (ALDERLAKE_P)
[00:15:42] [PASSED] 0x46C0 (ALDERLAKE_P)
[00:15:42] [PASSED] 0x46C1 (ALDERLAKE_P)
[00:15:42] [PASSED] 0x46C2 (ALDERLAKE_P)
[00:15:42] [PASSED] 0x46C3 (ALDERLAKE_P)
[00:15:42] [PASSED] 0x46D0 (ALDERLAKE_N)
[00:15:42] [PASSED] 0x46D1 (ALDERLAKE_N)
[00:15:42] [PASSED] 0x46D2 (ALDERLAKE_N)
[00:15:42] [PASSED] 0x46D3 (ALDERLAKE_N)
[00:15:42] [PASSED] 0x46D4 (ALDERLAKE_N)
[00:15:42] [PASSED] 0xA721 (ALDERLAKE_P)
[00:15:42] [PASSED] 0xA7A1 (ALDERLAKE_P)
[00:15:42] [PASSED] 0xA7A9 (ALDERLAKE_P)
[00:15:42] [PASSED] 0xA7AC (ALDERLAKE_P)
[00:15:42] [PASSED] 0xA7AD (ALDERLAKE_P)
[00:15:42] [PASSED] 0xA720 (ALDERLAKE_P)
[00:15:42] [PASSED] 0xA7A0 (ALDERLAKE_P)
[00:15:42] [PASSED] 0xA7A8 (ALDERLAKE_P)
[00:15:42] [PASSED] 0xA7AA (ALDERLAKE_P)
[00:15:42] [PASSED] 0xA7AB (ALDERLAKE_P)
[00:15:42] [PASSED] 0xA780 (ALDERLAKE_S)
[00:15:42] [PASSED] 0xA781 (ALDERLAKE_S)
[00:15:42] [PASSED] 0xA782 (ALDERLAKE_S)
[00:15:42] [PASSED] 0xA783 (ALDERLAKE_S)
[00:15:42] [PASSED] 0xA788 (ALDERLAKE_S)
[00:15:42] [PASSED] 0xA789 (ALDERLAKE_S)
[00:15:42] [PASSED] 0xA78A (ALDERLAKE_S)
[00:15:42] [PASSED] 0xA78B (ALDERLAKE_S)
[00:15:42] [PASSED] 0x4905 (DG1)
[00:15:42] [PASSED] 0x4906 (DG1)
[00:15:42] [PASSED] 0x4907 (DG1)
[00:15:42] [PASSED] 0x4908 (DG1)
[00:15:42] [PASSED] 0x4909 (DG1)
[00:15:42] [PASSED] 0x56C0 (DG2)
[00:15:42] [PASSED] 0x56C2 (DG2)
[00:15:42] [PASSED] 0x56C1 (DG2)
[00:15:42] [PASSED] 0x7D51 (METEORLAKE)
[00:15:42] [PASSED] 0x7DD1 (METEORLAKE)
[00:15:42] [PASSED] 0x7D41 (METEORLAKE)
[00:15:42] [PASSED] 0x7D67 (METEORLAKE)
[00:15:42] [PASSED] 0xB640 (METEORLAKE)
[00:15:42] [PASSED] 0x56A0 (DG2)
[00:15:42] [PASSED] 0x56A1 (DG2)
[00:15:42] [PASSED] 0x56A2 (DG2)
[00:15:42] [PASSED] 0x56BE (DG2)
[00:15:42] [PASSED] 0x56BF (DG2)
[00:15:42] [PASSED] 0x5690 (DG2)
[00:15:42] [PASSED] 0x5691 (DG2)
[00:15:42] [PASSED] 0x5692 (DG2)
[00:15:42] [PASSED] 0x56A5 (DG2)
[00:15:42] [PASSED] 0x56A6 (DG2)
[00:15:42] [PASSED] 0x56B0 (DG2)
[00:15:42] [PASSED] 0x56B1 (DG2)
[00:15:42] [PASSED] 0x56BA (DG2)
[00:15:42] [PASSED] 0x56BB (DG2)
[00:15:42] [PASSED] 0x56BC (DG2)
[00:15:42] [PASSED] 0x56BD (DG2)
[00:15:42] [PASSED] 0x5693 (DG2)
[00:15:42] [PASSED] 0x5694 (DG2)
[00:15:42] [PASSED] 0x5695 (DG2)
[00:15:42] [PASSED] 0x56A3 (DG2)
[00:15:42] [PASSED] 0x56A4 (DG2)
[00:15:42] [PASSED] 0x56B2 (DG2)
[00:15:42] [PASSED] 0x56B3 (DG2)
[00:15:42] [PASSED] 0x5696 (DG2)
[00:15:42] [PASSED] 0x5697 (DG2)
[00:15:42] [PASSED] 0xB69 (PVC)
[00:15:42] [PASSED] 0xB6E (PVC)
[00:15:42] [PASSED] 0xBD4 (PVC)
[00:15:42] [PASSED] 0xBD5 (PVC)
[00:15:42] [PASSED] 0xBD6 (PVC)
[00:15:42] [PASSED] 0xBD7 (PVC)
[00:15:42] [PASSED] 0xBD8 (PVC)
[00:15:42] [PASSED] 0xBD9 (PVC)
[00:15:42] [PASSED] 0xBDA (PVC)
[00:15:42] [PASSED] 0xBDB (PVC)
[00:15:42] [PASSED] 0xBE0 (PVC)
[00:15:42] [PASSED] 0xBE1 (PVC)
[00:15:42] [PASSED] 0xBE5 (PVC)
[00:15:42] [PASSED] 0x7D40 (METEORLAKE)
[00:15:42] [PASSED] 0x7D45 (METEORLAKE)
[00:15:42] [PASSED] 0x7D55 (METEORLAKE)
[00:15:42] [PASSED] 0x7D60 (METEORLAKE)
[00:15:42] [PASSED] 0x7DD5 (METEORLAKE)
[00:15:42] [PASSED] 0x6420 (LUNARLAKE)
[00:15:42] [PASSED] 0x64A0 (LUNARLAKE)
[00:15:42] [PASSED] 0x64B0 (LUNARLAKE)
[00:15:42] [PASSED] 0xE202 (BATTLEMAGE)
[00:15:42] [PASSED] 0xE209 (BATTLEMAGE)
[00:15:42] [PASSED] 0xE20B (BATTLEMAGE)
[00:15:42] [PASSED] 0xE20C (BATTLEMAGE)
[00:15:42] [PASSED] 0xE20D (BATTLEMAGE)
[00:15:42] [PASSED] 0xE210 (BATTLEMAGE)
[00:15:42] [PASSED] 0xE211 (BATTLEMAGE)
[00:15:42] [PASSED] 0xE212 (BATTLEMAGE)
[00:15:42] [PASSED] 0xE216 (BATTLEMAGE)
[00:15:42] [PASSED] 0xE220 (BATTLEMAGE)
[00:15:42] [PASSED] 0xE221 (BATTLEMAGE)
[00:15:42] [PASSED] 0xE222 (BATTLEMAGE)
[00:15:42] [PASSED] 0xE223 (BATTLEMAGE)
[00:15:42] [PASSED] 0xB080 (PANTHERLAKE)
[00:15:42] [PASSED] 0xB081 (PANTHERLAKE)
[00:15:42] [PASSED] 0xB082 (PANTHERLAKE)
[00:15:42] [PASSED] 0xB083 (PANTHERLAKE)
[00:15:42] [PASSED] 0xB084 (PANTHERLAKE)
[00:15:42] [PASSED] 0xB085 (PANTHERLAKE)
[00:15:42] [PASSED] 0xB086 (PANTHERLAKE)
[00:15:42] [PASSED] 0xB087 (PANTHERLAKE)
[00:15:42] [PASSED] 0xB08F (PANTHERLAKE)
[00:15:42] [PASSED] 0xB090 (PANTHERLAKE)
[00:15:42] [PASSED] 0xB0A0 (PANTHERLAKE)
[00:15:42] [PASSED] 0xB0B0 (PANTHERLAKE)
[00:15:42] [PASSED] 0xFD80 (PANTHERLAKE)
[00:15:42] [PASSED] 0xFD81 (PANTHERLAKE)
[00:15:42] [PASSED] 0xD740 (NOVALAKE_S)
[00:15:42] [PASSED] 0xD741 (NOVALAKE_S)
[00:15:42] [PASSED] 0xD742 (NOVALAKE_S)
[00:15:42] [PASSED] 0xD743 (NOVALAKE_S)
[00:15:42] [PASSED] 0xD745 (NOVALAKE_S)
[00:15:42] [PASSED] 0xD74A (NOVALAKE_S)
[00:15:42] [PASSED] 0xD74B (NOVALAKE_S)
[00:15:42] [PASSED] 0x674C (CRESCENTISLAND)
[00:15:42] [PASSED] 0x674D (CRESCENTISLAND)
[00:15:42] [PASSED] 0x674E (CRESCENTISLAND)
[00:15:42] [PASSED] 0x674F (CRESCENTISLAND)
[00:15:42] [PASSED] 0x6750 (CRESCENTISLAND)
[00:15:42] [PASSED] 0xD750 (NOVALAKE_P)
[00:15:42] [PASSED] 0xD751 (NOVALAKE_P)
[00:15:42] [PASSED] 0xD752 (NOVALAKE_P)
[00:15:42] [PASSED] 0xD753 (NOVALAKE_P)
[00:15:42] [PASSED] 0xD754 (NOVALAKE_P)
[00:15:42] [PASSED] 0xD755 (NOVALAKE_P)
[00:15:42] [PASSED] 0xD756 (NOVALAKE_P)
[00:15:42] [PASSED] 0xD757 (NOVALAKE_P)
[00:15:42] [PASSED] 0xD75F (NOVALAKE_P)
[00:15:42] =============== [PASSED] check_platform_desc ===============
[00:15:42] ===================== [PASSED] xe_pci ======================
[00:15:42] ============= xe_rtp_tables_test (4 subtests) ==============
[00:15:42] ================== xe_rtp_table_gt_test  ===================
[00:15:42] [PASSED] gt_was/14011060649
[00:15:42] [PASSED] gt_was/14011059788
[00:15:42] [PASSED] gt_was/14015795083
[00:15:42] [PASSED] gt_was/16021867713
[00:15:42] [PASSED] gt_was/14019449301
[00:15:42] [PASSED] gt_was/16028005424
[00:15:42] [PASSED] gt_was/14026578760
[00:15:42] [PASSED] gt_was/1409420604
[00:15:42] [PASSED] gt_was/1408615072
[00:15:42] [PASSED] gt_was/22010523718
[00:15:42] [PASSED] gt_was/14011006942
[00:15:42] [PASSED] gt_was/14014830051
[00:15:42] [PASSED] gt_was/18018781329
[00:15:42] [PASSED] gt_was/1509235366
[00:15:42] [PASSED] gt_was/18018781329
[00:15:42] [PASSED] gt_was/16016694945
[00:15:42] [PASSED] gt_was/14018575942
[00:15:42] [PASSED] gt_was/22016670082
[00:15:42] [PASSED] gt_was/22016670082
[00:15:42] [PASSED] gt_was/14017421178
[00:15:42] [PASSED] gt_was/16025250150
[00:15:42] [PASSED] gt_was/14021871409
[00:15:42] [PASSED] gt_was/16021865536
[00:15:42] [PASSED] gt_was/14021486841
[00:15:42] [PASSED] gt_was/14025160223
[00:15:42] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[00:15:42] [PASSED] gt_was/14025635424
[00:15:42] [PASSED] gt_was/16028005424
[00:15:42] ============== [PASSED] xe_rtp_table_gt_test ===============
[00:15:42] ================== xe_rtp_table_gt_test  ===================
[00:15:42] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[00:15:42] [PASSED] gt_tunings/Tuning: 32B Access Enable
[00:15:42] [PASSED] gt_tunings/Tuning: L3 cache
[00:15:42] [PASSED] gt_tunings/Tuning: L3 cache - media
[00:15:42] [PASSED] gt_tunings/Tuning: Compression Overfetch
[00:15:42] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[00:15:42] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[00:15:42] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[00:15:42] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[00:15:42] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[00:15:42] [PASSED] gt_tunings/Tuning: Stateless compression control
[00:15:42] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[00:15:42] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[00:15:42] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[00:15:42] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[00:15:42] ============== [PASSED] xe_rtp_table_gt_test ===============
[00:15:42] ================== xe_rtp_table_oob_test  ==================
[00:15:42] [PASSED] oob_was/1607983814
[00:15:42] [PASSED] oob_was/16010904313
[00:15:42] [PASSED] oob_was/18022495364
[00:15:42] [PASSED] oob_was/22012773006
[00:15:42] [PASSED] oob_was/14014475959
[00:15:42] [PASSED] oob_was/22011391025
[00:15:42] [PASSED] oob_was/22012727170
[00:15:42] [PASSED] oob_was/22012727685
[00:15:42] [PASSED] oob_was/22016596838
[00:15:42] [PASSED] oob_was/18020744125
[00:15:42] [PASSED] oob_was/1409600907
[00:15:42] [PASSED] oob_was/22014953428
[00:15:42] [PASSED] oob_was/16017236439
[00:15:42] [PASSED] oob_was/14019821291
[00:15:42] [PASSED] oob_was/14015076503
[00:15:42] [PASSED] oob_was/14018913170
[00:15:42] [PASSED] oob_was/14018094691
[00:15:42] [PASSED] oob_was/18024947630
[00:15:42] [PASSED] oob_was/16022287689
[00:15:42] [PASSED] oob_was/13011645652
[00:15:42] [PASSED] oob_was/14022293748
[00:15:42] [PASSED] oob_was/22019794406
[00:15:42] [PASSED] oob_was/22019338487
[00:15:42] [PASSED] oob_was/16023588340
[00:15:42] [PASSED] oob_was/14019789679
[00:15:42] [PASSED] oob_was/14022866841
[00:15:42] [PASSED] oob_was/16021333562
[00:15:42] [PASSED] oob_was/14016712196
[00:15:42] [PASSED] oob_was/14015568240
[00:15:42] [PASSED] oob_was/18013179988
[00:15:42] [PASSED] oob_was/1508761755
[00:15:42] [PASSED] oob_was/16023105232
[00:15:42] [PASSED] oob_was/16026508708
[00:15:42] [PASSED] oob_was/14020001231
[00:15:42] [PASSED] oob_was/16023683509
[00:15:42] [PASSED] oob_was/14025515070
[00:15:42] [PASSED] oob_was/15015404425_disable
[00:15:42] [PASSED] oob_was/16026007364
[00:15:42] [PASSED] oob_was/14020316580
[00:15:42] [PASSED] oob_was/14025883347
[00:15:42] [PASSED] oob_was/16029380221
[00:15:42] ============== [PASSED] xe_rtp_table_oob_test ==============
[00:15:42] ================ xe_rtp_table_dev_oob_test  ================
[00:15:42] [PASSED] device_oob_was/22010954014
[00:15:42] [PASSED] device_oob_was/15015404425
[00:15:42] [PASSED] device_oob_was/22019338487_display
[00:15:42] [PASSED] device_oob_was/14022085890
[00:15:42] [PASSED] device_oob_was/14026539277
[00:15:42] [PASSED] device_oob_was/14026633728
[00:15:42] [PASSED] device_oob_was/14026746987
[00:15:42] [PASSED] device_oob_was/14026779378
[00:15:42] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[00:15:42] =============== [PASSED] xe_rtp_tables_test ================
[00:15:42] =================== xe_rtp (3 subtests) ====================
[00:15:42] =================== xe_rtp_rules_tests  ====================
[00:15:42] [PASSED] no
[00:15:42] [PASSED] yes
[00:15:42] [PASSED] no-and-no
[00:15:42] [PASSED] no-and-yes
[00:15:42] [PASSED] yes-and-no
[00:15:42] [PASSED] yes-and-yes
[00:15:42] [PASSED] no-or-no
[00:15:42] [PASSED] no-or-yes
[00:15:42] [PASSED] yes-or-no
[00:15:42] [PASSED] yes-or-yes
[00:15:42] [PASSED] no-yes-or-yes-no
[00:15:42] [PASSED] no-yes-or-yes-yes
[00:15:42] [PASSED] yes-yes-or-no-yes
[00:15:42] [PASSED] yes-yes-or-yes-yes
[00:15:42] [PASSED] no-no-or-yes-or-no
[00:15:42] [PASSED] or
[00:15:42] [PASSED] or-yes
[00:15:42] [PASSED] or-no
[00:15:42] [PASSED] yes-or
[00:15:42] [PASSED] no-or
[00:15:42] [PASSED] no-or-or-yes
[00:15:42] [PASSED] yes-or-or-no
[00:15:42] [PASSED] no-or-or-no
[00:15:42] [PASSED] missing-context-engine-class
[00:15:42] [PASSED] missing-context-engine-class-or-yes
[00:15:42] [PASSED] missing-context-engine-class-or-or-yes
[00:15:42] =============== [PASSED] xe_rtp_rules_tests ================
[00:15:42] =============== xe_rtp_process_to_sr_tests  ================
[00:15:42] [PASSED] coalesce-same-reg
[00:15:42] [PASSED] coalesce-same-reg-literal-and-func
[00:15:42] [PASSED] no-match-no-add
[00:15:42] [PASSED] two-regs-two-entries
[00:15:42] [PASSED] clr-one-set-other
[00:15:42] [PASSED] set-field
[00:15:42] [PASSED] conflict-duplicate
[00:15:42] [PASSED] conflict-not-disjoint
[00:15:42] [PASSED] conflict-not-disjoint-literal-and-func
[00:15:42] [PASSED] conflict-reg-type
[00:15:42] [PASSED] bad-mcr-reg-forced-to-regular
[00:15:42] [PASSED] bad-regular-reg-forced-to-mcr
[00:15:42] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[00:15:42] ================== xe_rtp_process_tests  ===================
[00:15:42] [PASSED] active1
[00:15:42] [PASSED] active2
[00:15:42] [PASSED] active-inactive
[00:15:42] [PASSED] inactive-active
[00:15:42] [PASSED] inactive-active-inactive
[00:15:42] [PASSED] inactive-inactive-inactive
[00:15:42] ============== [PASSED] xe_rtp_process_tests ===============
[00:15:42] ===================== [PASSED] xe_rtp ======================
[00:15:42] ==================== xe_wa (1 subtest) =====================
[00:15:42] ======================== xe_wa_gt  =========================
[00:15:42] [PASSED] TIGERLAKE B0
[00:15:42] [PASSED] DG1 A0
[00:15:42] [PASSED] DG1 B0
[00:15:42] [PASSED] ALDERLAKE_S A0
[00:15:42] [PASSED] ALDERLAKE_S B0
[00:15:42] [PASSED] ALDERLAKE_S C0
[00:15:42] [PASSED] ALDERLAKE_S D0
[00:15:42] [PASSED] ALDERLAKE_P A0
[00:15:42] [PASSED] ALDERLAKE_P B0
[00:15:42] [PASSED] ALDERLAKE_P C0
[00:15:42] [PASSED] ALDERLAKE_S RPLS D0
[00:15:42] [PASSED] ALDERLAKE_P RPLU E0
[00:15:42] [PASSED] DG2 G10 C0
[00:15:42] [PASSED] DG2 G11 B1
[00:15:42] [PASSED] DG2 G12 A1
[00:15:42] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[00:15:42] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[00:15:42] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[00:15:42] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[00:15:42] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[00:15:42] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[00:15:42] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[00:15:42] ==================== [PASSED] xe_wa_gt =====================
[00:15:42] ====================== [PASSED] xe_wa ======================
[00:15:42] ============================================================
[00:15:42] Testing complete. Ran 719 tests: passed: 701, skipped: 18
[00:15:42] Elapsed time: 36.800s total, 4.430s configuring, 31.704s building, 0.651s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[00:15:43] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[00:15:44] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[00:16:09] Starting KUnit Kernel (1/1)...
[00:16:09] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[00:16:09] ============ drm_test_pick_cmdline (2 subtests) ============
[00:16:09] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[00:16:09] =============== drm_test_pick_cmdline_named  ===============
[00:16:09] [PASSED] NTSC
[00:16:09] [PASSED] NTSC-J
[00:16:09] [PASSED] PAL
[00:16:09] [PASSED] PAL-M
[00:16:09] =========== [PASSED] drm_test_pick_cmdline_named ===========
[00:16:09] ============== [PASSED] drm_test_pick_cmdline ==============
[00:16:09] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[00:16:09] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[00:16:09] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[00:16:09] =========== drm_validate_clone_mode (2 subtests) ===========
[00:16:09] ============== drm_test_check_in_clone_mode  ===============
[00:16:09] [PASSED] in_clone_mode
[00:16:09] [PASSED] not_in_clone_mode
[00:16:09] ========== [PASSED] drm_test_check_in_clone_mode ===========
[00:16:09] =============== drm_test_check_valid_clones  ===============
[00:16:09] [PASSED] not_in_clone_mode
[00:16:09] [PASSED] valid_clone
[00:16:09] [PASSED] invalid_clone
[00:16:09] =========== [PASSED] drm_test_check_valid_clones ===========
[00:16:09] ============= [PASSED] drm_validate_clone_mode =============
[00:16:09] ============= drm_validate_modeset (1 subtest) =============
[00:16:09] [PASSED] drm_test_check_connector_changed_modeset
[00:16:09] ============== [PASSED] drm_validate_modeset ===============
[00:16:09] ====== drm_test_bridge_get_current_state (2 subtests) ======
[00:16:09] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[00:16:09] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[00:16:09] ======== [PASSED] drm_test_bridge_get_current_state ========
[00:16:09] ====== drm_test_bridge_helper_reset_crtc (4 subtests) ======
[00:16:09] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[00:16:09] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[00:16:09] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[00:16:09] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[00:16:09] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[00:16:09] ============== drm_bridge_alloc (2 subtests) ===============
[00:16:09] [PASSED] drm_test_drm_bridge_alloc_basic
[00:16:09] [PASSED] drm_test_drm_bridge_alloc_get_put
[00:16:09] ================ [PASSED] drm_bridge_alloc =================
[00:16:09] ============= drm_bridge_bus_fmt (5 subtests) ==============
[00:16:09] [PASSED] drm_test_bridge_rgb_yuv_rgb
[00:16:09] [PASSED] drm_test_bridge_must_convert_to_yuv444
[00:16:09] [PASSED] drm_test_bridge_hdmi_auto_rgb
[00:16:09] [PASSED] drm_test_bridge_auto_first
[00:16:09] [PASSED] drm_test_bridge_rgb_yuv_no_path
[00:16:09] =============== [PASSED] drm_bridge_bus_fmt ================
[00:16:09] ============= drm_cmdline_parser (40 subtests) =============
[00:16:09] [PASSED] drm_test_cmdline_force_d_only
[00:16:09] [PASSED] drm_test_cmdline_force_D_only_dvi
[00:16:09] [PASSED] drm_test_cmdline_force_D_only_hdmi
[00:16:09] [PASSED] drm_test_cmdline_force_D_only_not_digital
[00:16:09] [PASSED] drm_test_cmdline_force_e_only
[00:16:09] [PASSED] drm_test_cmdline_res
[00:16:09] [PASSED] drm_test_cmdline_res_vesa
[00:16:09] [PASSED] drm_test_cmdline_res_vesa_rblank
[00:16:09] [PASSED] drm_test_cmdline_res_rblank
[00:16:09] [PASSED] drm_test_cmdline_res_bpp
[00:16:09] [PASSED] drm_test_cmdline_res_refresh
[00:16:09] [PASSED] drm_test_cmdline_res_bpp_refresh
[00:16:09] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[00:16:09] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[00:16:09] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[00:16:09] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[00:16:09] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[00:16:09] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[00:16:09] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[00:16:09] [PASSED] drm_test_cmdline_res_margins_force_on
[00:16:09] [PASSED] drm_test_cmdline_res_vesa_margins
[00:16:09] [PASSED] drm_test_cmdline_name
[00:16:09] [PASSED] drm_test_cmdline_name_bpp
[00:16:09] [PASSED] drm_test_cmdline_name_option
[00:16:09] [PASSED] drm_test_cmdline_name_bpp_option
[00:16:09] [PASSED] drm_test_cmdline_rotate_0
[00:16:09] [PASSED] drm_test_cmdline_rotate_90
[00:16:09] [PASSED] drm_test_cmdline_rotate_180
[00:16:09] [PASSED] drm_test_cmdline_rotate_270
[00:16:09] [PASSED] drm_test_cmdline_hmirror
[00:16:09] [PASSED] drm_test_cmdline_vmirror
[00:16:09] [PASSED] drm_test_cmdline_margin_options
[00:16:09] [PASSED] drm_test_cmdline_multiple_options
[00:16:09] [PASSED] drm_test_cmdline_bpp_extra_and_option
[00:16:09] [PASSED] drm_test_cmdline_extra_and_option
[00:16:09] [PASSED] drm_test_cmdline_freestanding_options
[00:16:09] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[00:16:09] [PASSED] drm_test_cmdline_panel_orientation
[00:16:09] ================ drm_test_cmdline_invalid  =================
[00:16:09] [PASSED] margin_only
[00:16:09] [PASSED] interlace_only
[00:16:09] [PASSED] res_missing_x
[00:16:09] [PASSED] res_missing_y
[00:16:09] [PASSED] res_bad_y
[00:16:09] [PASSED] res_missing_y_bpp
[00:16:09] [PASSED] res_bad_bpp
[00:16:09] [PASSED] res_bad_refresh
[00:16:09] [PASSED] res_bpp_refresh_force_on_off
[00:16:09] [PASSED] res_invalid_mode
[00:16:09] [PASSED] res_bpp_wrong_place_mode
[00:16:09] [PASSED] name_bpp_refresh
[00:16:09] [PASSED] name_refresh
[00:16:09] [PASSED] name_refresh_wrong_mode
[00:16:09] [PASSED] name_refresh_invalid_mode
[00:16:09] [PASSED] rotate_multiple
[00:16:09] [PASSED] rotate_invalid_val
[00:16:09] [PASSED] rotate_truncated
[00:16:09] [PASSED] invalid_option
[00:16:09] [PASSED] invalid_tv_option
[00:16:09] [PASSED] truncated_tv_option
[00:16:09] ============ [PASSED] drm_test_cmdline_invalid =============
[00:16:09] =============== drm_test_cmdline_tv_options  ===============
[00:16:09] [PASSED] NTSC
[00:16:09] [PASSED] NTSC_443
[00:16:09] [PASSED] NTSC_J
[00:16:09] [PASSED] PAL
[00:16:09] [PASSED] PAL_M
[00:16:09] [PASSED] PAL_N
[00:16:09] [PASSED] SECAM
[00:16:09] [PASSED] MONO_525
[00:16:09] [PASSED] MONO_625
[00:16:09] =========== [PASSED] drm_test_cmdline_tv_options ===========
[00:16:09] =============== [PASSED] drm_cmdline_parser ================
[00:16:09] ========== drmm_connector_hdmi_init (20 subtests) ==========
[00:16:09] [PASSED] drm_test_connector_hdmi_init_valid
[00:16:09] [PASSED] drm_test_connector_hdmi_init_bpc_8
[00:16:09] [PASSED] drm_test_connector_hdmi_init_bpc_10
[00:16:09] [PASSED] drm_test_connector_hdmi_init_bpc_12
[00:16:09] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[00:16:09] [PASSED] drm_test_connector_hdmi_init_bpc_null
[00:16:09] [PASSED] drm_test_connector_hdmi_init_formats_empty
[00:16:09] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[00:16:09] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[00:16:09] [PASSED] supported_formats=0x9 yuv420_allowed=1
[00:16:09] [PASSED] supported_formats=0x9 yuv420_allowed=0
[00:16:09] [PASSED] supported_formats=0x5 yuv420_allowed=1
[00:16:09] [PASSED] supported_formats=0x5 yuv420_allowed=0
[00:16:09] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[00:16:09] [PASSED] drm_test_connector_hdmi_init_null_ddc
[00:16:09] [PASSED] drm_test_connector_hdmi_init_null_product
[00:16:09] [PASSED] drm_test_connector_hdmi_init_null_vendor
[00:16:09] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[00:16:09] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[00:16:09] [PASSED] drm_test_connector_hdmi_init_product_valid
[00:16:09] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[00:16:09] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[00:16:09] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[00:16:09] ========= drm_test_connector_hdmi_init_type_valid  =========
[00:16:09] [PASSED] HDMI-A
[00:16:09] [PASSED] HDMI-B
[00:16:09] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[00:16:09] ======== drm_test_connector_hdmi_init_type_invalid  ========
[00:16:09] [PASSED] Unknown
[00:16:09] [PASSED] VGA
[00:16:09] [PASSED] DVI-I
[00:16:09] [PASSED] DVI-D
[00:16:09] [PASSED] DVI-A
[00:16:09] [PASSED] Composite
[00:16:09] [PASSED] SVIDEO
[00:16:09] [PASSED] LVDS
[00:16:09] [PASSED] Component
[00:16:09] [PASSED] DIN
[00:16:09] [PASSED] DP
[00:16:09] [PASSED] TV
[00:16:09] [PASSED] eDP
[00:16:09] [PASSED] Virtual
[00:16:09] [PASSED] DSI
[00:16:09] [PASSED] DPI
[00:16:09] [PASSED] Writeback
[00:16:09] [PASSED] SPI
[00:16:09] [PASSED] USB
[00:16:09] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[00:16:09] ============ [PASSED] drmm_connector_hdmi_init =============
[00:16:09] ============= drmm_connector_init (3 subtests) =============
[00:16:09] [PASSED] drm_test_drmm_connector_init
[00:16:09] [PASSED] drm_test_drmm_connector_init_null_ddc
[00:16:09] ========= drm_test_drmm_connector_init_type_valid  =========
[00:16:09] [PASSED] Unknown
[00:16:09] [PASSED] VGA
[00:16:09] [PASSED] DVI-I
[00:16:09] [PASSED] DVI-D
[00:16:09] [PASSED] DVI-A
[00:16:09] [PASSED] Composite
[00:16:09] [PASSED] SVIDEO
[00:16:09] [PASSED] LVDS
[00:16:09] [PASSED] Component
[00:16:09] [PASSED] DIN
[00:16:09] [PASSED] DP
[00:16:09] [PASSED] HDMI-A
[00:16:09] [PASSED] HDMI-B
[00:16:09] [PASSED] TV
[00:16:09] [PASSED] eDP
[00:16:09] [PASSED] Virtual
[00:16:09] [PASSED] DSI
[00:16:09] [PASSED] DPI
[00:16:09] [PASSED] Writeback
[00:16:09] [PASSED] SPI
[00:16:09] [PASSED] USB
[00:16:09] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[00:16:09] =============== [PASSED] drmm_connector_init ===============
[00:16:09] ========= drm_connector_dynamic_init (6 subtests) ==========
[00:16:09] [PASSED] drm_test_drm_connector_dynamic_init
[00:16:09] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[00:16:09] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[00:16:09] [PASSED] drm_test_drm_connector_dynamic_init_properties
[00:16:09] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[00:16:09] [PASSED] Unknown
[00:16:09] [PASSED] VGA
[00:16:09] [PASSED] DVI-I
[00:16:09] [PASSED] DVI-D
[00:16:09] [PASSED] DVI-A
[00:16:09] [PASSED] Composite
[00:16:09] [PASSED] SVIDEO
[00:16:09] [PASSED] LVDS
[00:16:09] [PASSED] Component
[00:16:09] [PASSED] DIN
[00:16:09] [PASSED] DP
[00:16:09] [PASSED] HDMI-A
[00:16:09] [PASSED] HDMI-B
[00:16:09] [PASSED] TV
[00:16:09] [PASSED] eDP
[00:16:09] [PASSED] Virtual
[00:16:09] [PASSED] DSI
[00:16:09] [PASSED] DPI
[00:16:09] [PASSED] Writeback
[00:16:09] [PASSED] SPI
[00:16:09] [PASSED] USB
[00:16:09] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[00:16:09] ======== drm_test_drm_connector_dynamic_init_name  =========
[00:16:09] [PASSED] Unknown
[00:16:09] [PASSED] VGA
[00:16:09] [PASSED] DVI-I
[00:16:09] [PASSED] DVI-D
[00:16:09] [PASSED] DVI-A
[00:16:09] [PASSED] Composite
[00:16:09] [PASSED] SVIDEO
[00:16:09] [PASSED] LVDS
[00:16:09] [PASSED] Component
[00:16:09] [PASSED] DIN
[00:16:09] [PASSED] DP
[00:16:09] [PASSED] HDMI-A
[00:16:09] [PASSED] HDMI-B
[00:16:09] [PASSED] TV
[00:16:09] [PASSED] eDP
[00:16:09] [PASSED] Virtual
[00:16:09] [PASSED] DSI
[00:16:09] [PASSED] DPI
[00:16:09] [PASSED] Writeback
[00:16:09] [PASSED] SPI
[00:16:09] [PASSED] USB
[00:16:09] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[00:16:09] =========== [PASSED] drm_connector_dynamic_init ============
[00:16:09] ==== drm_connector_dynamic_register_early (4 subtests) =====
[00:16:09] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[00:16:09] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[00:16:09] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[00:16:09] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[00:16:09] ====== [PASSED] drm_connector_dynamic_register_early =======
[00:16:09] ======= drm_connector_dynamic_register (7 subtests) ========
[00:16:09] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[00:16:09] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[00:16:09] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[00:16:09] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[00:16:09] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[00:16:09] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[00:16:09] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[00:16:09] ========= [PASSED] drm_connector_dynamic_register ==========
[00:16:09] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[00:16:09] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[00:16:09] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[00:16:09] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[00:16:09] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[00:16:09] ========== drm_test_get_tv_mode_from_name_valid  ===========
[00:16:09] [PASSED] NTSC
[00:16:09] [PASSED] NTSC-443
[00:16:09] [PASSED] NTSC-J
[00:16:09] [PASSED] PAL
[00:16:09] [PASSED] PAL-M
[00:16:09] [PASSED] PAL-N
[00:16:09] [PASSED] SECAM
[00:16:09] [PASSED] Mono
[00:16:09] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[00:16:09] [PASSED] drm_test_get_tv_mode_from_name_truncated
[00:16:09] ============ [PASSED] drm_get_tv_mode_from_name ============
[00:16:09] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[00:16:09] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[00:16:09] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[00:16:09] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[00:16:09] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[00:16:09] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[00:16:09] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[00:16:09] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[00:16:09] [PASSED] VIC 96
[00:16:09] [PASSED] VIC 97
[00:16:09] [PASSED] VIC 101
[00:16:09] [PASSED] VIC 102
[00:16:09] [PASSED] VIC 106
[00:16:09] [PASSED] VIC 107
[00:16:09] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[00:16:09] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[00:16:09] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[00:16:09] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[00:16:09] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[00:16:09] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[00:16:09] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[00:16:09] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[00:16:09] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[00:16:09] [PASSED] Automatic
[00:16:09] [PASSED] Full
[00:16:09] [PASSED] Limited 16:235
[00:16:09] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[00:16:09] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[00:16:09] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[00:16:09] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[00:16:09] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[00:16:09] [PASSED] RGB
[00:16:09] [PASSED] YUV 4:2:0
[00:16:09] [PASSED] YUV 4:2:2
[00:16:09] [PASSED] YUV 4:4:4
[00:16:09] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[00:16:09] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[00:16:09] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[00:16:09] ============= drm_damage_helper (21 subtests) ==============
[00:16:09] [PASSED] drm_test_damage_iter_no_damage
[00:16:09] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[00:16:09] [PASSED] drm_test_damage_iter_no_damage_src_moved
[00:16:09] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[00:16:09] [PASSED] drm_test_damage_iter_no_damage_not_visible
[00:16:09] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[00:16:09] [PASSED] drm_test_damage_iter_no_damage_no_fb
[00:16:09] [PASSED] drm_test_damage_iter_simple_damage
[00:16:09] [PASSED] drm_test_damage_iter_single_damage
[00:16:09] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[00:16:09] [PASSED] drm_test_damage_iter_single_damage_outside_src
[00:16:09] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[00:16:09] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[00:16:09] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[00:16:09] [PASSED] drm_test_damage_iter_single_damage_src_moved
[00:16:09] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[00:16:09] [PASSED] drm_test_damage_iter_damage
[00:16:09] [PASSED] drm_test_damage_iter_damage_one_intersect
[00:16:09] [PASSED] drm_test_damage_iter_damage_one_outside
[00:16:09] [PASSED] drm_test_damage_iter_damage_src_moved
[00:16:09] [PASSED] drm_test_damage_iter_damage_not_visible
[00:16:09] ================ [PASSED] drm_damage_helper ================
[00:16:09] ============== drm_dp_mst_helper (3 subtests) ==============
[00:16:09] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[00:16:09] [PASSED] Clock 154000 BPP 30 DSC disabled
[00:16:09] [PASSED] Clock 234000 BPP 30 DSC disabled
[00:16:09] [PASSED] Clock 297000 BPP 24 DSC disabled
[00:16:09] [PASSED] Clock 332880 BPP 24 DSC enabled
[00:16:09] [PASSED] Clock 324540 BPP 24 DSC enabled
[00:16:09] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[00:16:09] ============== drm_test_dp_mst_calc_pbn_div  ===============
[00:16:09] [PASSED] Link rate 2000000 lane count 4
[00:16:09] [PASSED] Link rate 2000000 lane count 2
[00:16:09] [PASSED] Link rate 2000000 lane count 1
[00:16:09] [PASSED] Link rate 1350000 lane count 4
[00:16:09] [PASSED] Link rate 1350000 lane count 2
[00:16:09] [PASSED] Link rate 1350000 lane count 1
[00:16:09] [PASSED] Link rate 1000000 lane count 4
[00:16:09] [PASSED] Link rate 1000000 lane count 2
[00:16:09] [PASSED] Link rate 1000000 lane count 1
[00:16:09] [PASSED] Link rate 810000 lane count 4
[00:16:09] [PASSED] Link rate 810000 lane count 2
[00:16:09] [PASSED] Link rate 810000 lane count 1
[00:16:09] [PASSED] Link rate 540000 lane count 4
[00:16:09] [PASSED] Link rate 540000 lane count 2
[00:16:09] [PASSED] Link rate 540000 lane count 1
[00:16:09] [PASSED] Link rate 270000 lane count 4
[00:16:09] [PASSED] Link rate 270000 lane count 2
[00:16:09] [PASSED] Link rate 270000 lane count 1
[00:16:09] [PASSED] Link rate 162000 lane count 4
[00:16:09] [PASSED] Link rate 162000 lane count 2
[00:16:09] [PASSED] Link rate 162000 lane count 1
[00:16:09] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[00:16:09] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[00:16:09] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[00:16:09] [PASSED] DP_POWER_UP_PHY with port number
[00:16:09] [PASSED] DP_POWER_DOWN_PHY with port number
[00:16:09] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[00:16:09] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[00:16:09] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[00:16:09] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[00:16:09] [PASSED] DP_QUERY_PAYLOAD with port number
[00:16:09] [PASSED] DP_QUERY_PAYLOAD with VCPI
[00:16:09] [PASSED] DP_REMOTE_DPCD_READ with port number
[00:16:09] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[00:16:09] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[00:16:09] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[00:16:09] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[00:16:09] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[00:16:09] [PASSED] DP_REMOTE_I2C_READ with port number
[00:16:09] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[00:16:09] [PASSED] DP_REMOTE_I2C_READ with transactions array
[00:16:09] [PASSED] DP_REMOTE_I2C_WRITE with port number
[00:16:09] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[00:16:09] [PASSED] DP_REMOTE_I2C_WRITE with data array
[00:16:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[00:16:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[00:16:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[00:16:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[00:16:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[00:16:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[00:16:09] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[00:16:09] ================ [PASSED] drm_dp_mst_helper ================
[00:16:09] ================== drm_exec (7 subtests) ===================
[00:16:09] [PASSED] sanitycheck
[00:16:09] [PASSED] test_lock
[00:16:09] [PASSED] test_lock_unlock
[00:16:09] [PASSED] test_duplicates
[00:16:09] [PASSED] test_prepare
[00:16:09] [PASSED] test_prepare_array
[00:16:09] [PASSED] test_multiple_loops
[00:16:09] ==================== [PASSED] drm_exec =====================
[00:16:09] =========== drm_format_helper_test (17 subtests) ===========
[00:16:09] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[00:16:09] [PASSED] single_pixel_source_buffer
[00:16:09] [PASSED] single_pixel_clip_rectangle
[00:16:09] [PASSED] well_known_colors
[00:16:09] [PASSED] destination_pitch
[00:16:09] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[00:16:09] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[00:16:09] [PASSED] single_pixel_source_buffer
[00:16:09] [PASSED] single_pixel_clip_rectangle
[00:16:09] [PASSED] well_known_colors
[00:16:09] [PASSED] destination_pitch
[00:16:09] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[00:16:09] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[00:16:09] [PASSED] single_pixel_source_buffer
[00:16:09] [PASSED] single_pixel_clip_rectangle
[00:16:09] [PASSED] well_known_colors
[00:16:09] [PASSED] destination_pitch
[00:16:09] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[00:16:09] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[00:16:09] [PASSED] single_pixel_source_buffer
[00:16:09] [PASSED] single_pixel_clip_rectangle
[00:16:09] [PASSED] well_known_colors
[00:16:09] [PASSED] destination_pitch
[00:16:09] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[00:16:09] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[00:16:09] [PASSED] single_pixel_source_buffer
[00:16:09] [PASSED] single_pixel_clip_rectangle
[00:16:09] [PASSED] well_known_colors
[00:16:09] [PASSED] destination_pitch
[00:16:09] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[00:16:09] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[00:16:09] [PASSED] single_pixel_source_buffer
[00:16:09] [PASSED] single_pixel_clip_rectangle
[00:16:09] [PASSED] well_known_colors
[00:16:09] [PASSED] destination_pitch
[00:16:09] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[00:16:09] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[00:16:09] [PASSED] single_pixel_source_buffer
[00:16:09] [PASSED] single_pixel_clip_rectangle
[00:16:09] [PASSED] well_known_colors
[00:16:09] [PASSED] destination_pitch
[00:16:09] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[00:16:09] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[00:16:09] [PASSED] single_pixel_source_buffer
[00:16:09] [PASSED] single_pixel_clip_rectangle
[00:16:09] [PASSED] well_known_colors
[00:16:09] [PASSED] destination_pitch
[00:16:09] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[00:16:09] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[00:16:09] [PASSED] single_pixel_source_buffer
[00:16:09] [PASSED] single_pixel_clip_rectangle
[00:16:09] [PASSED] well_known_colors
[00:16:09] [PASSED] destination_pitch
[00:16:09] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[00:16:09] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[00:16:09] [PASSED] single_pixel_source_buffer
[00:16:09] [PASSED] single_pixel_clip_rectangle
[00:16:09] [PASSED] well_known_colors
[00:16:09] [PASSED] destination_pitch
[00:16:09] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[00:16:09] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[00:16:09] [PASSED] single_pixel_source_buffer
[00:16:09] [PASSED] single_pixel_clip_rectangle
[00:16:09] [PASSED] well_known_colors
[00:16:09] [PASSED] destination_pitch
[00:16:09] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[00:16:09] ============== drm_test_fb_xrgb8888_to_mono  ===============
[00:16:09] [PASSED] single_pixel_source_buffer
[00:16:09] [PASSED] single_pixel_clip_rectangle
[00:16:09] [PASSED] well_known_colors
[00:16:09] [PASSED] destination_pitch
[00:16:09] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[00:16:09] ==================== drm_test_fb_swab  =====================
[00:16:09] [PASSED] single_pixel_source_buffer
[00:16:09] [PASSED] single_pixel_clip_rectangle
[00:16:09] [PASSED] well_known_colors
[00:16:09] [PASSED] destination_pitch
[00:16:09] ================ [PASSED] drm_test_fb_swab =================
[00:16:09] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[00:16:09] [PASSED] single_pixel_source_buffer
[00:16:09] [PASSED] single_pixel_clip_rectangle
[00:16:09] [PASSED] well_known_colors
[00:16:09] [PASSED] destination_pitch
[00:16:09] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[00:16:09] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[00:16:09] [PASSED] single_pixel_source_buffer
[00:16:09] [PASSED] single_pixel_clip_rectangle
[00:16:09] [PASSED] well_known_colors
[00:16:09] [PASSED] destination_pitch
[00:16:09] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[00:16:09] ================= drm_test_fb_clip_offset  =================
[00:16:09] [PASSED] pass through
[00:16:09] [PASSED] horizontal offset
[00:16:09] [PASSED] vertical offset
[00:16:09] [PASSED] horizontal and vertical offset
[00:16:09] [PASSED] horizontal offset (custom pitch)
[00:16:09] [PASSED] vertical offset (custom pitch)
[00:16:09] [PASSED] horizontal and vertical offset (custom pitch)
[00:16:09] ============= [PASSED] drm_test_fb_clip_offset =============
[00:16:09] =================== drm_test_fb_memcpy  ====================
[00:16:09] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[00:16:09] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[00:16:09] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[00:16:09] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[00:16:09] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[00:16:09] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[00:16:09] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[00:16:09] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[00:16:09] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[00:16:09] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[00:16:09] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[00:16:09] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[00:16:09] =============== [PASSED] drm_test_fb_memcpy ================
[00:16:09] ============= [PASSED] drm_format_helper_test ==============
[00:16:09] ================= drm_format (18 subtests) =================
[00:16:09] [PASSED] drm_test_format_block_width_invalid
[00:16:09] [PASSED] drm_test_format_block_width_one_plane
[00:16:09] [PASSED] drm_test_format_block_width_two_plane
[00:16:09] [PASSED] drm_test_format_block_width_three_plane
[00:16:09] [PASSED] drm_test_format_block_width_tiled
[00:16:09] [PASSED] drm_test_format_block_height_invalid
[00:16:09] [PASSED] drm_test_format_block_height_one_plane
[00:16:09] [PASSED] drm_test_format_block_height_two_plane
[00:16:09] [PASSED] drm_test_format_block_height_three_plane
[00:16:09] [PASSED] drm_test_format_block_height_tiled
[00:16:09] [PASSED] drm_test_format_min_pitch_invalid
[00:16:09] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[00:16:09] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[00:16:09] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[00:16:09] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[00:16:09] [PASSED] drm_test_format_min_pitch_two_plane
[00:16:09] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[00:16:09] [PASSED] drm_test_format_min_pitch_tiled
[00:16:09] =================== [PASSED] drm_format ====================
[00:16:09] ============== drm_framebuffer (10 subtests) ===============
[00:16:09] ========== drm_test_framebuffer_check_src_coords  ==========
[00:16:09] [PASSED] Success: source fits into fb
[00:16:09] [PASSED] Fail: overflowing fb with x-axis coordinate
[00:16:09] [PASSED] Fail: overflowing fb with y-axis coordinate
[00:16:09] [PASSED] Fail: overflowing fb with source width
[00:16:09] [PASSED] Fail: overflowing fb with source height
[00:16:09] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[00:16:09] [PASSED] drm_test_framebuffer_cleanup
[00:16:09] =============== drm_test_framebuffer_create  ===============
[00:16:09] [PASSED] ABGR8888 normal sizes
[00:16:09] [PASSED] ABGR8888 max sizes
[00:16:09] [PASSED] ABGR8888 pitch greater than min required
[00:16:09] [PASSED] ABGR8888 pitch less than min required
[00:16:09] [PASSED] ABGR8888 Invalid width
[00:16:09] [PASSED] ABGR8888 Invalid buffer handle
[00:16:09] [PASSED] No pixel format
[00:16:09] [PASSED] ABGR8888 Width 0
[00:16:09] [PASSED] ABGR8888 Height 0
[00:16:09] [PASSED] ABGR8888 Out of bound height * pitch combination
[00:16:09] [PASSED] ABGR8888 Large buffer offset
[00:16:09] [PASSED] ABGR8888 Buffer offset for inexistent plane
[00:16:09] [PASSED] ABGR8888 Invalid flag
[00:16:09] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[00:16:09] [PASSED] ABGR8888 Valid buffer modifier
[00:16:09] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[00:16:09] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[00:16:09] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[00:16:09] [PASSED] NV12 Normal sizes
[00:16:09] [PASSED] NV12 Max sizes
[00:16:09] [PASSED] NV12 Invalid pitch
[00:16:09] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[00:16:09] [PASSED] NV12 different  modifier per-plane
[00:16:09] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[00:16:09] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[00:16:09] [PASSED] NV12 Modifier for inexistent plane
[00:16:09] [PASSED] NV12 Handle for inexistent plane
[00:16:09] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[00:16:09] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[00:16:09] [PASSED] YVU420 Normal sizes
[00:16:09] [PASSED] YVU420 Max sizes
[00:16:09] [PASSED] YVU420 Invalid pitch
[00:16:09] [PASSED] YVU420 Different pitches
[00:16:09] [PASSED] YVU420 Different buffer offsets/pitches
[00:16:09] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[00:16:09] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[00:16:09] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[00:16:09] [PASSED] YVU420 Valid modifier
[00:16:09] [PASSED] YVU420 Different modifiers per plane
[00:16:09] [PASSED] YVU420 Modifier for inexistent plane
[00:16:09] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[00:16:09] [PASSED] X0L2 Normal sizes
[00:16:09] [PASSED] X0L2 Max sizes
[00:16:09] [PASSED] X0L2 Invalid pitch
[00:16:09] [PASSED] X0L2 Pitch greater than minimum required
[00:16:09] [PASSED] X0L2 Handle for inexistent plane
[00:16:09] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[00:16:09] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[00:16:09] [PASSED] X0L2 Valid modifier
[00:16:09] [PASSED] X0L2 Modifier for inexistent plane
[00:16:09] =========== [PASSED] drm_test_framebuffer_create ===========
[00:16:09] [PASSED] drm_test_framebuffer_free
[00:16:09] [PASSED] drm_test_framebuffer_init
[00:16:09] [PASSED] drm_test_framebuffer_init_bad_format
[00:16:09] [PASSED] drm_test_framebuffer_init_dev_mismatch
[00:16:09] [PASSED] drm_test_framebuffer_lookup
[00:16:09] [PASSED] drm_test_framebuffer_lookup_inexistent
[00:16:09] [PASSED] drm_test_framebuffer_modifiers_not_supported
[00:16:09] ================= [PASSED] drm_framebuffer =================
[00:16:09] ================ drm_gem_shmem (8 subtests) ================
[00:16:09] [PASSED] drm_gem_shmem_test_obj_create
[00:16:09] [PASSED] drm_gem_shmem_test_obj_create_private
[00:16:09] [PASSED] drm_gem_shmem_test_pin_pages
[00:16:09] [PASSED] drm_gem_shmem_test_vmap
[00:16:09] [PASSED] drm_gem_shmem_test_get_sg_table
[00:16:09] [PASSED] drm_gem_shmem_test_get_pages_sgt
[00:16:09] [PASSED] drm_gem_shmem_test_madvise
[00:16:09] [PASSED] drm_gem_shmem_test_purge
[00:16:09] ================== [PASSED] drm_gem_shmem ==================
[00:16:09] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[00:16:09] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[00:16:09] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[00:16:09] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[00:16:09] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[00:16:09] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[00:16:09] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[00:16:09] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[00:16:09] [PASSED] Automatic
[00:16:09] [PASSED] Full
[00:16:09] [PASSED] Limited 16:235
[00:16:09] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[00:16:09] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[00:16:09] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[00:16:09] [PASSED] drm_test_check_disable_connector
[00:16:09] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[00:16:09] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[00:16:09] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[00:16:09] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[00:16:09] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[00:16:09] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[00:16:09] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[00:16:09] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[00:16:09] [PASSED] drm_test_check_output_bpc_dvi
[00:16:09] [PASSED] drm_test_check_output_bpc_format_vic_1
[00:16:09] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[00:16:09] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[00:16:09] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[00:16:09] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[00:16:09] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[00:16:09] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[00:16:09] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[00:16:09] ============ drm_test_check_hdmi_color_format  =============
[00:16:09] [PASSED] AUTO -> RGB
[00:16:09] [PASSED] YCBCR422 -> YUV422
[00:16:09] [PASSED] YCBCR420 -> YUV420
[00:16:09] [PASSED] YCBCR444 -> YUV444
[00:16:09] [PASSED] RGB -> RGB
[00:16:09] ======== [PASSED] drm_test_check_hdmi_color_format =========
[00:16:09] ======== drm_test_check_hdmi_color_format_420_only  ========
[00:16:09] [PASSED] RGB should fail
[00:16:09] [PASSED] YUV444 should fail
[00:16:09] [PASSED] YUV422 should fail
[00:16:09] [PASSED] YUV420 should work
[00:16:09] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[00:16:09] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[00:16:09] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[00:16:09] [PASSED] drm_test_check_broadcast_rgb_value
[00:16:09] [PASSED] drm_test_check_bpc_8_value
[00:16:09] [PASSED] drm_test_check_bpc_10_value
[00:16:09] [PASSED] drm_test_check_bpc_12_value
[00:16:09] [PASSED] drm_test_check_format_value
[00:16:09] [PASSED] drm_test_check_tmds_char_value
[00:16:09] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[00:16:09] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[00:16:09] [PASSED] drm_test_check_mode_valid
[00:16:09] [PASSED] drm_test_check_mode_valid_reject
[00:16:09] [PASSED] drm_test_check_mode_valid_reject_rate
[00:16:09] [PASSED] drm_test_check_mode_valid_reject_max_clock
[00:16:09] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[00:16:09] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[00:16:09] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[00:16:09] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[00:16:09] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[00:16:09] [PASSED] drm_test_check_infoframes
[00:16:09] [PASSED] drm_test_check_reject_avi_infoframe
[00:16:09] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[00:16:09] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[00:16:09] [PASSED] drm_test_check_reject_audio_infoframe
[00:16:09] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[00:16:09] ================= drm_managed (2 subtests) =================
[00:16:09] [PASSED] drm_test_managed_release_action
[00:16:09] [PASSED] drm_test_managed_run_action
[00:16:09] =================== [PASSED] drm_managed ===================
[00:16:09] =================== drm_mm (6 subtests) ====================
[00:16:09] [PASSED] drm_test_mm_init
[00:16:09] [PASSED] drm_test_mm_debug
[00:16:09] [PASSED] drm_test_mm_align32
[00:16:09] [PASSED] drm_test_mm_align64
[00:16:09] [PASSED] drm_test_mm_lowest
[00:16:09] [PASSED] drm_test_mm_highest
[00:16:09] ===================== [PASSED] drm_mm ======================
[00:16:09] ============= drm_modes_analog_tv (5 subtests) =============
[00:16:09] [PASSED] drm_test_modes_analog_tv_mono_576i
[00:16:09] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[00:16:09] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[00:16:09] [PASSED] drm_test_modes_analog_tv_pal_576i
[00:16:09] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[00:16:09] =============== [PASSED] drm_modes_analog_tv ===============
[00:16:09] ============== drm_plane_helper (2 subtests) ===============
[00:16:09] =============== drm_test_check_plane_state  ================
[00:16:09] [PASSED] clipping_simple
[00:16:09] [PASSED] clipping_rotate_reflect
[00:16:09] [PASSED] positioning_simple
[00:16:09] [PASSED] upscaling
[00:16:09] [PASSED] downscaling
[00:16:09] [PASSED] rounding1
[00:16:09] [PASSED] rounding2
[00:16:09] [PASSED] rounding3
[00:16:09] [PASSED] rounding4
[00:16:09] =========== [PASSED] drm_test_check_plane_state ============
[00:16:09] =========== drm_test_check_invalid_plane_state  ============
[00:16:09] [PASSED] positioning_invalid
[00:16:09] [PASSED] upscaling_invalid
[00:16:09] [PASSED] downscaling_invalid
[00:16:09] ======= [PASSED] drm_test_check_invalid_plane_state ========
[00:16:09] ================ [PASSED] drm_plane_helper =================
[00:16:09] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[00:16:09] ====== drm_test_connector_helper_tv_get_modes_check  =======
[00:16:09] [PASSED] None
[00:16:09] [PASSED] PAL
[00:16:09] [PASSED] NTSC
[00:16:09] [PASSED] Both, NTSC Default
[00:16:09] [PASSED] Both, PAL Default
[00:16:09] [PASSED] Both, NTSC Default, with PAL on command-line
[00:16:09] [PASSED] Both, PAL Default, with NTSC on command-line
[00:16:09] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[00:16:09] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[00:16:09] ================== drm_rect (9 subtests) ===================
[00:16:09] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[00:16:09] [PASSED] drm_test_rect_clip_scaled_not_clipped
[00:16:09] [PASSED] drm_test_rect_clip_scaled_clipped
[00:16:09] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[00:16:09] ================= drm_test_rect_intersect  =================
[00:16:09] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[00:16:09] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[00:16:09] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[00:16:09] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[00:16:09] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[00:16:09] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[00:16:09] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[00:16:09] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[00:16:09] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[00:16:09] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[00:16:09] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[00:16:09] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[00:16:09] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[00:16:09] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[00:16:09] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[00:16:09] ============= [PASSED] drm_test_rect_intersect =============
[00:16:09] ================ drm_test_rect_calc_hscale  ================
[00:16:09] [PASSED] normal use
[00:16:09] [PASSED] out of max range
[00:16:09] [PASSED] out of min range
[00:16:09] [PASSED] zero dst
[00:16:09] [PASSED] negative src
[00:16:09] [PASSED] negative dst
[00:16:09] ============ [PASSED] drm_test_rect_calc_hscale ============
[00:16:09] ================ drm_test_rect_calc_vscale  ================
[00:16:09] [PASSED] normal use
[00:16:09] [PASSED] out of max range
[00:16:09] [PASSED] out of min range
[00:16:09] [PASSED] zero dst
[00:16:09] [PASSED] negative src
[00:16:09] [PASSED] negative dst
[00:16:09] ============ [PASSED] drm_test_rect_calc_vscale ============
[00:16:09] ================== drm_test_rect_rotate  ===================
[00:16:09] [PASSED] reflect-x
[00:16:09] [PASSED] reflect-y
[00:16:09] [PASSED] rotate-0
[00:16:09] [PASSED] rotate-90
[00:16:09] [PASSED] rotate-180
[00:16:09] [PASSED] rotate-270
[00:16:09] ============== [PASSED] drm_test_rect_rotate ===============
[00:16:09] ================ drm_test_rect_rotate_inv  =================
[00:16:09] [PASSED] reflect-x
[00:16:09] [PASSED] reflect-y
[00:16:09] [PASSED] rotate-0
[00:16:09] [PASSED] rotate-90
[00:16:09] [PASSED] rotate-180
[00:16:09] [PASSED] rotate-270
[00:16:09] ============ [PASSED] drm_test_rect_rotate_inv =============
[00:16:09] ==================== [PASSED] drm_rect =====================
[00:16:09] ============ drm_sysfb_modeset_test (1 subtest) ============
[00:16:09] ============ drm_test_sysfb_build_fourcc_list  =============
[00:16:09] [PASSED] no native formats
[00:16:09] [PASSED] XRGB8888 as native format
[00:16:09] [PASSED] remove duplicates
[00:16:09] [PASSED] convert alpha formats
[00:16:09] [PASSED] random formats
[00:16:09] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[00:16:09] ============= [PASSED] drm_sysfb_modeset_test ==============
[00:16:09] ================== drm_fixp (2 subtests) ===================
[00:16:09] [PASSED] drm_test_int2fixp
[00:16:09] [PASSED] drm_test_sm2fixp
[00:16:09] ==================== [PASSED] drm_fixp =====================
[00:16:09] ============================================================
[00:16:09] Testing complete. Ran 639 tests: passed: 639
[00:16:09] Elapsed time: 26.496s total, 1.787s configuring, 24.542s building, 0.143s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[00:16:09] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[00:16:11] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[00:16:21] Starting KUnit Kernel (1/1)...
[00:16:21] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[00:16:21] ================= ttm_device (5 subtests) ==================
[00:16:21] [PASSED] ttm_device_init_basic
[00:16:21] [PASSED] ttm_device_init_multiple
[00:16:21] [PASSED] ttm_device_fini_basic
[00:16:21] [PASSED] ttm_device_init_no_vma_man
[00:16:21] ================== ttm_device_init_pools  ==================
[00:16:21] [PASSED] No DMA allocations, no DMA32 required
[00:16:21] [PASSED] DMA allocations, DMA32 required
[00:16:21] [PASSED] No DMA allocations, DMA32 required
[00:16:21] [PASSED] DMA allocations, no DMA32 required
[00:16:21] ============== [PASSED] ttm_device_init_pools ==============
[00:16:21] =================== [PASSED] ttm_device ====================
[00:16:21] ================== ttm_pool (8 subtests) ===================
[00:16:21] ================== ttm_pool_alloc_basic  ===================
[00:16:21] [PASSED] One page
[00:16:21] [PASSED] More than one page
[00:16:21] [PASSED] Above the allocation limit
[00:16:21] [PASSED] One page, with coherent DMA mappings enabled
[00:16:21] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[00:16:21] ============== [PASSED] ttm_pool_alloc_basic ===============
[00:16:21] ============== ttm_pool_alloc_basic_dma_addr  ==============
[00:16:21] [PASSED] One page
[00:16:21] [PASSED] More than one page
[00:16:21] [PASSED] Above the allocation limit
[00:16:21] [PASSED] One page, with coherent DMA mappings enabled
[00:16:21] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[00:16:21] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[00:16:21] [PASSED] ttm_pool_alloc_order_caching_match
[00:16:21] [PASSED] ttm_pool_alloc_caching_mismatch
[00:16:21] [PASSED] ttm_pool_alloc_order_mismatch
[00:16:21] [PASSED] ttm_pool_free_dma_alloc
[00:16:21] [PASSED] ttm_pool_free_no_dma_alloc
[00:16:21] [PASSED] ttm_pool_fini_basic
[00:16:21] ==================== [PASSED] ttm_pool =====================
[00:16:21] ================ ttm_resource (8 subtests) =================
[00:16:21] ================= ttm_resource_init_basic  =================
[00:16:21] [PASSED] Init resource in TTM_PL_SYSTEM
[00:16:21] [PASSED] Init resource in TTM_PL_VRAM
[00:16:21] [PASSED] Init resource in a private placement
[00:16:21] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[00:16:21] ============= [PASSED] ttm_resource_init_basic =============
[00:16:21] [PASSED] ttm_resource_init_pinned
[00:16:21] [PASSED] ttm_resource_fini_basic
[00:16:21] [PASSED] ttm_resource_manager_init_basic
[00:16:21] [PASSED] ttm_resource_manager_usage_basic
[00:16:21] [PASSED] ttm_resource_manager_set_used_basic
[00:16:21] [PASSED] ttm_sys_man_alloc_basic
[00:16:21] [PASSED] ttm_sys_man_free_basic
[00:16:21] ================== [PASSED] ttm_resource ===================
[00:16:21] =================== ttm_tt (15 subtests) ===================
[00:16:21] ==================== ttm_tt_init_basic  ====================
[00:16:21] [PASSED] Page-aligned size
[00:16:21] [PASSED] Extra pages requested
[00:16:21] ================ [PASSED] ttm_tt_init_basic ================
[00:16:21] [PASSED] ttm_tt_init_misaligned
[00:16:21] [PASSED] ttm_tt_fini_basic
[00:16:21] [PASSED] ttm_tt_fini_sg
[00:16:21] [PASSED] ttm_tt_fini_shmem
[00:16:21] [PASSED] ttm_tt_create_basic
[00:16:21] [PASSED] ttm_tt_create_invalid_bo_type
[00:16:21] [PASSED] ttm_tt_create_ttm_exists
[00:16:21] [PASSED] ttm_tt_create_failed
[00:16:21] [PASSED] ttm_tt_destroy_basic
[00:16:21] [PASSED] ttm_tt_populate_null_ttm
[00:16:21] [PASSED] ttm_tt_populate_populated_ttm
[00:16:21] [PASSED] ttm_tt_unpopulate_basic
[00:16:21] [PASSED] ttm_tt_unpopulate_empty_ttm
[00:16:21] [PASSED] ttm_tt_swapin_basic
[00:16:21] ===================== [PASSED] ttm_tt ======================
[00:16:21] =================== ttm_bo (14 subtests) ===================
[00:16:21] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[00:16:21] [PASSED] Cannot be interrupted and sleeps
[00:16:21] [PASSED] Cannot be interrupted, locks straight away
[00:16:21] [PASSED] Can be interrupted, sleeps
[00:16:21] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[00:16:21] [PASSED] ttm_bo_reserve_locked_no_sleep
[00:16:21] [PASSED] ttm_bo_reserve_no_wait_ticket
[00:16:21] [PASSED] ttm_bo_reserve_double_resv
[00:16:21] [PASSED] ttm_bo_reserve_interrupted
[00:16:21] [PASSED] ttm_bo_reserve_deadlock
[00:16:21] [PASSED] ttm_bo_unreserve_basic
[00:16:21] [PASSED] ttm_bo_unreserve_pinned
[00:16:21] [PASSED] ttm_bo_unreserve_bulk
[00:16:21] [PASSED] ttm_bo_fini_basic
[00:16:21] [PASSED] ttm_bo_fini_shared_resv
[00:16:21] [PASSED] ttm_bo_pin_basic
[00:16:21] [PASSED] ttm_bo_pin_unpin_resource
[00:16:21] [PASSED] ttm_bo_multiple_pin_one_unpin
[00:16:21] ===================== [PASSED] ttm_bo ======================
[00:16:21] ============== ttm_bo_validate (22 subtests) ===============
[00:16:21] ============== ttm_bo_init_reserved_sys_man  ===============
[00:16:21] [PASSED] Buffer object for userspace
[00:16:21] [PASSED] Kernel buffer object
[00:16:21] [PASSED] Shared buffer object
[00:16:21] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[00:16:21] ============== ttm_bo_init_reserved_mock_man  ==============
[00:16:21] [PASSED] Buffer object for userspace
[00:16:21] [PASSED] Kernel buffer object
[00:16:21] [PASSED] Shared buffer object
[00:16:21] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[00:16:21] [PASSED] ttm_bo_init_reserved_resv
[00:16:21] ================== ttm_bo_validate_basic  ==================
[00:16:21] [PASSED] Buffer object for userspace
[00:16:21] [PASSED] Kernel buffer object
[00:16:21] [PASSED] Shared buffer object
[00:16:21] ============== [PASSED] ttm_bo_validate_basic ==============
[00:16:21] [PASSED] ttm_bo_validate_invalid_placement
[00:16:21] ============= ttm_bo_validate_same_placement  ==============
[00:16:21] [PASSED] System manager
[00:16:21] [PASSED] VRAM manager
[00:16:21] ========= [PASSED] ttm_bo_validate_same_placement ==========
[00:16:21] [PASSED] ttm_bo_validate_failed_alloc
[00:16:21] [PASSED] ttm_bo_validate_pinned
[00:16:21] [PASSED] ttm_bo_validate_busy_placement
[00:16:21] ================ ttm_bo_validate_multihop  =================
[00:16:21] [PASSED] Buffer object for userspace
[00:16:21] [PASSED] Kernel buffer object
[00:16:21] [PASSED] Shared buffer object
[00:16:21] ============ [PASSED] ttm_bo_validate_multihop =============
[00:16:21] ========== ttm_bo_validate_no_placement_signaled  ==========
[00:16:21] [PASSED] Buffer object in system domain, no page vector
[00:16:21] [PASSED] Buffer object in system domain with an existing page vector
[00:16:21] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[00:16:21] ======== ttm_bo_validate_no_placement_not_signaled  ========
[00:16:21] [PASSED] Buffer object for userspace
[00:16:21] [PASSED] Kernel buffer object
[00:16:21] [PASSED] Shared buffer object
[00:16:21] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[00:16:21] [PASSED] ttm_bo_validate_move_fence_signaled
[00:16:21] ========= ttm_bo_validate_move_fence_not_signaled  =========
[00:16:21] [PASSED] Waits for GPU
[00:16:21] [PASSED] Tries to lock straight away
[00:16:21] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[00:16:21] [PASSED] ttm_bo_validate_swapout
[00:16:21] [PASSED] ttm_bo_validate_happy_evict
[00:16:21] [PASSED] ttm_bo_validate_all_pinned_evict
[00:16:21] [PASSED] ttm_bo_validate_allowed_only_evict
[00:16:21] [PASSED] ttm_bo_validate_deleted_evict
[00:16:21] [PASSED] ttm_bo_validate_busy_domain_evict
[00:16:21] [PASSED] ttm_bo_validate_evict_gutting
[00:16:21] [PASSED] ttm_bo_validate_recrusive_evict
[00:16:21] ================= [PASSED] ttm_bo_validate =================
[00:16:21] ============================================================
[00:16:21] Testing complete. Ran 102 tests: passed: 102
[00:16:21] Elapsed time: 11.925s total, 1.826s configuring, 9.884s building, 0.184s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel



^ permalink raw reply	[flat|nested] 14+ messages in thread

* ✓ Xe.CI.BAT: success for drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs (rev2)
  2026-06-10 17:44 [PATCH 0/3] drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs Alexander Kaplan
                   ` (5 preceding siblings ...)
  2026-06-30  0:16 ` ✓ CI.KUnit: success for drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs (rev2) Patchwork
@ 2026-06-30  0:53 ` Patchwork
  2026-06-30 13:18 ` ✓ Xe.CI.FULL: " Patchwork
  7 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2026-06-30  0:53 UTC (permalink / raw)
  To: Alexander Kaplan; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 912 bytes --]

== Series Details ==

Series: drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs (rev2)
URL   : https://patchwork.freedesktop.org/series/168276/
State : success

== Summary ==

CI Bug Log - changes from xe-5306-03288b34f48c3fe60055353c30da4aacab572cdc_BAT -> xe-pw-168276v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-5306-03288b34f48c3fe60055353c30da4aacab572cdc -> xe-pw-168276v2

  IGT_8988: 8988
  xe-5306-03288b34f48c3fe60055353c30da4aacab572cdc: 03288b34f48c3fe60055353c30da4aacab572cdc
  xe-pw-168276v2: 168276v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/index.html

[-- Attachment #2: Type: text/html, Size: 1460 bytes --]

^ permalink raw reply	[flat|nested] 14+ messages in thread

* ✓ Xe.CI.FULL: success for drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs (rev2)
  2026-06-10 17:44 [PATCH 0/3] drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs Alexander Kaplan
                   ` (6 preceding siblings ...)
  2026-06-30  0:53 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-06-30 13:18 ` Patchwork
  7 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2026-06-30 13:18 UTC (permalink / raw)
  To: Alexander Kaplan; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 25481 bytes --]

== Series Details ==

Series: drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs (rev2)
URL   : https://patchwork.freedesktop.org/series/168276/
State : success

== Summary ==

CI Bug Log - changes from xe-5306-03288b34f48c3fe60055353c30da4aacab572cdc_FULL -> xe-pw-168276v2_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-168276v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-3:
    - shard-bmg:          [PASS][1] -> [INCOMPLETE][2] ([Intel XE#8174]) +1 other test incomplete
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5306-03288b34f48c3fe60055353c30da4aacab572cdc/shard-bmg-5/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-3.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-3/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-3.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#2327]) +1 other test skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][4] ([Intel XE#3658] / [Intel XE#7360])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-lnl-4/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#1124]) +2 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_bw@linear-tiling-2-displays-target-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#367])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-7/igt@kms_bw@linear-tiling-2-displays-target-2560x1440p.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2887]) +9 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-7/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs.html

  * igt@kms_chamelium_color_pipeline@plane-ctm3x4-lut1d:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#7358]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-7/igt@kms_chamelium_color_pipeline@plane-ctm3x4-lut1d.html

  * igt@kms_chamelium_hpd@dp-hpd-after-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2252]) +3 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html

  * igt@kms_content_protection@lic-type-0-hdcp14@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][10] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@kms_content_protection@lic-type-0-hdcp14@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-random-64x21:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#2320]) +1 other test skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@kms_cursor_crc@cursor-random-64x21.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2321] / [Intel XE#7355])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#4354] / [Intel XE#5882])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc-bigjoiner:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#8265])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-7/igt@kms_dsc@dsc-fractional-bpp-with-bpc-bigjoiner.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [PASS][15] -> [FAIL][16] ([Intel XE#301])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5306-03288b34f48c3fe60055353c30da4aacab572cdc/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#7178] / [Intel XE#7351]) +3 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-indfb-pgflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#6312] / [Intel XE#651])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-lnl-4/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrshdr-1p-rte:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#2311]) +24 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@kms_frontbuffer_tracking@drrshdr-1p-rte.html

  * igt@kms_frontbuffer_tracking@drrshdr-2p-scndscrn-pri-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][21] ([Intel XE#7905]) +2 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-lnl-4/igt@kms_frontbuffer_tracking@drrshdr-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrshdr-argb161616f-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#7061]) +3 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@kms_frontbuffer_tracking@drrshdr-argb161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#4141]) +8 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2313]) +22 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#4298] / [Intel XE#5873])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-7/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#6911] / [Intel XE#7466])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-6/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#7283])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2763] / [Intel XE#6886]) +4 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b.html

  * igt@kms_pm_dc@dc5-dpms-negative:
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#1131])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-lnl-4/igt@kms_pm_dc@dc5-dpms-negative.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#1489]) +2 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr@psr-sprite-plane-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#2234] / [Intel XE#2850]) +4 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@kms_psr@psr-sprite-plane-onoff.html

  * igt@kms_sharpness_filter@filter-basic:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#6503])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-6/igt@kms_sharpness_filter@filter-basic.html

  * igt@xe_configfs@ctx-restore-mid-bb-invalid:
    - shard-bmg:          [PASS][33] -> [ABORT][34] ([Intel XE#8007])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5306-03288b34f48c3fe60055353c30da4aacab572cdc/shard-bmg-4/igt@xe_configfs@ctx-restore-mid-bb-invalid.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-4/igt@xe_configfs@ctx-restore-mid-bb-invalid.html

  * igt@xe_eudebug@basic-vm-bind-vm-destroy:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#7636]) +2 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-6/igt@xe_eudebug@basic-vm-bind-vm-destroy.html

  * igt@xe_eudebug@multigpu-basic-client-many:
    - shard-lnl:          NOTRUN -> [SKIP][36] ([Intel XE#7636]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-lnl-4/igt@xe_eudebug@multigpu-basic-client-many.html

  * igt@xe_exec_balancer@many-execqueues-cm-parallel-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][37] ([Intel XE#7482])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-lnl-4/igt@xe_exec_balancer@many-execqueues-cm-parallel-userptr.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#2322] / [Intel XE#7372]) +2 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-rebind.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-imm:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#8374]) +6 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@xe_exec_fault_mode@many-execqueues-multi-queue-imm.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-dyn-priority:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#8364])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-lnl-4/igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-dyn-priority.html

  * igt@xe_exec_multi_queue@many-execs-close-fd-smem:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#8364]) +10 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@xe_exec_multi_queue@many-execs-close-fd-smem.html

  * igt@xe_exec_reset@multi-queue-cancel:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#8369])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-7/igt@xe_exec_reset@multi-queue-cancel.html

  * igt@xe_exec_threads@threads-multi-queue-cm-basic:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#8378]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-7/igt@xe_exec_threads@threads-multi-queue-cm-basic.html

  * igt@xe_intel_bb@blit-reloc:
    - shard-bmg:          NOTRUN -> [ABORT][44] ([Intel XE#8007])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-5/igt@xe_intel_bb@blit-reloc.html

  * igt@xe_mmap@small-bar:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#586] / [Intel XE#7323] / [Intel XE#7384])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@xe_mmap@small-bar.html

  * igt@xe_multigpu_svm@mgpu-migration-basic:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#6964])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@xe_multigpu_svm@mgpu-migration-basic.html

  * igt@xe_page_reclaim@pde-vs-pd:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#7793]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-6/igt@xe_page_reclaim@pde-vs-pd.html

  * igt@xe_pm@s3-d3cold-basic-exec:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#2284] / [Intel XE#7370])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-6/igt@xe_pm@s3-d3cold-basic-exec.html

  * igt@xe_prefetch_fault@prefetch-fault:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#7599])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-8/igt@xe_prefetch_fault@prefetch-fault.html

  * igt@xe_pxp@pxp-optout:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#4733] / [Intel XE#7417])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@xe_pxp@pxp-optout.html

  * igt@xe_query@multigpu-query-topology:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#944])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@xe_query@multigpu-query-topology.html

  
#### Possible fixes ####

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [INCOMPLETE][52] ([Intel XE#7084] / [Intel XE#8150]) -> [PASS][53] +1 other test pass
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5306-03288b34f48c3fe60055353c30da4aacab572cdc/shard-bmg-6/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [FAIL][54] ([Intel XE#301]) -> [PASS][55] +1 other test pass
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5306-03288b34f48c3fe60055353c30da4aacab572cdc/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-lnl:          [FAIL][56] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][57]
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5306-03288b34f48c3fe60055353c30da4aacab572cdc/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][58] ([Intel XE#1503]) -> [PASS][59]
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5306-03288b34f48c3fe60055353c30da4aacab572cdc/shard-bmg-1/igt@kms_hdr@invalid-hdr.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-2/igt@kms_hdr@invalid-hdr.html

  * igt@xe_compute_preempt@compute-preempt-many-vram-evict@engine-drm_xe_engine_class_compute:
    - shard-bmg:          [ABORT][60] ([Intel XE#7893] / [Intel XE#8300]) -> [PASS][61] +1 other test pass
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5306-03288b34f48c3fe60055353c30da4aacab572cdc/shard-bmg-3/igt@xe_compute_preempt@compute-preempt-many-vram-evict@engine-drm_xe_engine_class_compute.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-7/igt@xe_compute_preempt@compute-preempt-many-vram-evict@engine-drm_xe_engine_class_compute.html

  * igt@xe_wedged@wedged-mode-toggle:
    - shard-bmg:          [ABORT][62] ([Intel XE#8007]) -> [PASS][63] +1 other test pass
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5306-03288b34f48c3fe60055353c30da4aacab572cdc/shard-bmg-7/igt@xe_wedged@wedged-mode-toggle.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-5/igt@xe_wedged@wedged-mode-toggle.html

  
#### Warnings ####

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
    - shard-lnl:          [SKIP][64] ([Intel XE#309] / [Intel XE#7343] / [Intel XE#7935]) -> [SKIP][65] ([Intel XE#309] / [Intel XE#7343])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5306-03288b34f48c3fe60055353c30da4aacab572cdc/shard-lnl-8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-lnl-4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][66] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][67] ([Intel XE#301])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5306-03288b34f48c3fe60055353c30da4aacab572cdc/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [FAIL][68] ([Intel XE#1729] / [Intel XE#7424]) -> [SKIP][69] ([Intel XE#2426] / [Intel XE#5848])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5306-03288b34f48c3fe60055353c30da4aacab572cdc/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][70] ([Intel XE#2426] / [Intel XE#5848]) -> [SKIP][71] ([Intel XE#2509] / [Intel XE#7437])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5306-03288b34f48c3fe60055353c30da4aacab572cdc/shard-bmg-8/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_survivability@runtime-survivability:
    - shard-bmg:          [ABORT][72] ([Intel XE#8007]) -> [DMESG-WARN][73] ([Intel XE#6627] / [Intel XE#7419])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5306-03288b34f48c3fe60055353c30da4aacab572cdc/shard-bmg-7/igt@xe_survivability@runtime-survivability.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/shard-bmg-10/igt@xe_survivability@runtime-survivability.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1131]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1131
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3658
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4298]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4298
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#586]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/586
  [Intel XE#5873]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5873
  [Intel XE#5882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5882
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6627]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6627
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7323
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7360
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7384]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7384
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7419]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7419
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7466
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7599
  [Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7893
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#7935]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7935
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150
  [Intel XE#8174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8174
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8300]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8300
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-5306-03288b34f48c3fe60055353c30da4aacab572cdc -> xe-pw-168276v2

  IGT_8988: 8988
  xe-5306-03288b34f48c3fe60055353c30da4aacab572cdc: 03288b34f48c3fe60055353c30da4aacab572cdc
  xe-pw-168276v2: 168276v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168276v2/index.html

[-- Attachment #2: Type: text/html, Size: 28247 bytes --]

^ permalink raw reply	[flat|nested] 14+ messages in thread

end of thread, other threads:[~2026-06-30 13:18 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-06-10 17:44 [PATCH 0/3] drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs Alexander Kaplan
2026-06-10 17:44 ` [PATCH 1/3] drm/i915/dp: Prefer DSC over a 6 bpc uncompressed output Alexander Kaplan
2026-06-12 16:32   ` Imre Deak
2026-06-12 18:46     ` Alexander Kaplan
2026-06-29  3:59       ` Nautiyal, Ankit K
2026-06-10 17:44 ` [PATCH 2/3] drm/i915/dp: Ignore the sink's DSC max FRL rate without a PCON DSC encoder Alexander Kaplan
2026-06-29  4:01   ` Nautiyal, Ankit K
2026-06-10 17:44 ` [PATCH 3/3] drm/i915/dp: Check FRL bandwidth limits in the HDMI bpc computation Alexander Kaplan
2026-06-29  4:16   ` Nautiyal, Ankit K
2026-06-10 17:49 ` [PATCH 0/3] drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs Alexander Kaplan
2026-06-10 18:45 ` ✗ LGCI.VerificationFailed: failure for " Patchwork
2026-06-30  0:16 ` ✓ CI.KUnit: success for drm/i915/dp: Fix FRL rate selection and deep color for HDMI sinks behind FRL PCONs (rev2) Patchwork
2026-06-30  0:53 ` ✓ Xe.CI.BAT: " Patchwork
2026-06-30 13:18 ` ✓ Xe.CI.FULL: " Patchwork

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