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* [PATCH 0/9] Add support for 3 VDSC engines 12 slices
@ 2024-10-14  8:09 Ankit Nautiyal
  2024-10-14  8:09 ` [PATCH 1/9] drm/i915/display: Prepare for dsc 3 stream splitter Ankit Nautiyal
                   ` (16 more replies)
  0 siblings, 17 replies; 22+ messages in thread
From: Ankit Nautiyal @ 2024-10-14  8:09 UTC (permalink / raw)
  To: intel-gfx; +Cc: intel-xe

For BMG 3 VDSC engines are supported and each pipe can then support
3 slices. For Ultra joiner cases for modes like 8k@120 Hz we require
ultrajoiner and 3 x 4= 12 slices.
Add support for 3 VDSC engines and 12 DSC slices. Along with this
Pixel replication and Odd pixel considerartions are also required.

Rev2: Rebase

Ankit Nautiyal (9):
  drm/i915/display: Prepare for dsc 3 stream splitter
  drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine
  drm/i915/vdsc: Add register bits for VDSC2 engine
  drm/i915/vdsc: Add support for read/write PPS for DSC3
  drm/i915/dp: Add check for hdisplay divisible by slice count
  drm/i915/display: Add DSC pixel replication
  drm/i915/dp: Compute pixel replication count for DSC 12 slices case
  drm/i915/dsc: Account for Odd pixel removal
  drm/i915/dp: Add support for 3 vdsc engines and 12 slices.

 drivers/gpu/drm/i915/display/icl_dsi.c        |   2 +-
 drivers/gpu/drm/i915/display/intel_display.c  |   3 +-
 .../drm/i915/display/intel_display_types.h    |   9 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |  75 ++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   2 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   2 +
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 105 ++++++++++++++++--
 .../gpu/drm/i915/display/intel_vdsc_regs.h    |  22 +++-
 8 files changed, 200 insertions(+), 20 deletions(-)

-- 
2.45.2


^ permalink raw reply	[flat|nested] 22+ messages in thread
* [PATCH 0/9] Add support for 3 VDSC engines 12 slices
@ 2024-10-14  7:02 Ankit Nautiyal
  2024-10-14  7:02 ` [PATCH 6/9] drm/i915/display: Add DSC pixel replication Ankit Nautiyal
  0 siblings, 1 reply; 22+ messages in thread
From: Ankit Nautiyal @ 2024-10-14  7:02 UTC (permalink / raw)
  To: intel-gfx; +Cc: intel-xe

For BMG 3 VDSC engines are supported and each pipe can then support
3 slices. For Ultra joiner cases for modes like 8k@120 Hz we require
ultrajoiner and 3 x 4= 12 slices.
Add support for 3 VDSC engines and 12 DSC slices. Along with this
Pixel replication and Odd pixel considerartions are also required.

Ankit Nautiyal (9):
  drm/i915/display: Prepare for dsc 3 stream splitter
  drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine
  drm/i915/vdsc: Add register bits for VDSC2 engine
  drm/i915/vdsc: Add support for read/write PPS for DSC3
  drm/i915/dp: Add check for hdisplay divisible by slice count
  drm/i915/display: Add DSC pixel replication
  drm/i915/dp: Compute pixel replication count for DSC 12 slices case
  drm/i915/dsc: Account for Odd pixel removal
  drm/i915/dp: Add support for 3 vdsc engines and 12 slices.

 drivers/gpu/drm/i915/display/icl_dsi.c        |   2 +-
 drivers/gpu/drm/i915/display/intel_display.c  |   3 +-
 .../drm/i915/display/intel_display_types.h    |   9 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |  75 ++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   2 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   2 +
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 105 ++++++++++++++++--
 .../gpu/drm/i915/display/intel_vdsc_regs.h    |  22 +++-
 8 files changed, 200 insertions(+), 20 deletions(-)

-- 
2.45.2


^ permalink raw reply	[flat|nested] 22+ messages in thread

end of thread, other threads:[~2024-10-18  2:21 UTC | newest]

Thread overview: 22+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-10-14  8:09 [PATCH 0/9] Add support for 3 VDSC engines 12 slices Ankit Nautiyal
2024-10-14  8:09 ` [PATCH 1/9] drm/i915/display: Prepare for dsc 3 stream splitter Ankit Nautiyal
2024-10-14  8:09 ` [PATCH 2/9] drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine Ankit Nautiyal
2024-10-14  8:09 ` [PATCH 3/9] drm/i915/vdsc: Add register bits for VDSC2 engine Ankit Nautiyal
2024-10-14  8:09 ` [PATCH 4/9] drm/i915/vdsc: Add support for read/write PPS for DSC3 Ankit Nautiyal
2024-10-14  8:09 ` [PATCH 5/9] drm/i915/dp: Add check for hdisplay divisible by slice count Ankit Nautiyal
2024-10-14  8:09 ` [PATCH 6/9] drm/i915/display: Add DSC pixel replication Ankit Nautiyal
2024-10-15 17:01   ` kernel test robot
2024-10-16 11:00   ` kernel test robot
2024-10-14  8:09 ` [PATCH 7/9] drm/i915/dp: Compute pixel replication count for DSC 12 slices case Ankit Nautiyal
2024-10-18  2:21   ` Kandpal, Suraj
2024-10-14  8:09 ` [PATCH 8/9] drm/i915/dsc: Account for Odd pixel removal Ankit Nautiyal
2024-10-14  8:10 ` [PATCH 9/9] drm/i915/dp: Add support for 3 vdsc engines and 12 slices Ankit Nautiyal
2024-10-14  8:32 ` ✓ CI.Patch_applied: success for Add support for 3 VDSC engines 12 slices (rev2) Patchwork
2024-10-14  8:33 ` ✓ CI.checkpatch: " Patchwork
2024-10-14  8:34 ` ✓ CI.KUnit: " Patchwork
2024-10-14  8:45 ` ✓ CI.Build: " Patchwork
2024-10-14  8:48 ` ✓ CI.Hooks: " Patchwork
2024-10-14  8:49 ` ✗ CI.checksparse: warning " Patchwork
2024-10-14  9:14 ` ✓ CI.BAT: success " Patchwork
2024-10-14 10:58 ` ✗ CI.FULL: failure " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2024-10-14  7:02 [PATCH 0/9] Add support for 3 VDSC engines 12 slices Ankit Nautiyal
2024-10-14  7:02 ` [PATCH 6/9] drm/i915/display: Add DSC pixel replication Ankit Nautiyal

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