From: Lucas De Marchi <lucas.demarchi@intel.com>
To: <intel-xe@lists.freedesktop.org>
Cc: Jani Nikula <jani.nikula@linux.intel.com>,
Alexander Usyskin <alexander.usyskin@intel.com>,
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>,
Ashutosh Dixit <ashutosh.dixit@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [PATCH 3/4] drm/xe: Drop HAS_HECI_*
Date: Thu, 14 Nov 2024 07:21:47 -0800 [thread overview]
Message-ID: <20241114152148.572447-4-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20241114152148.572447-1-lucas.demarchi@intel.com>
Just do the same as for other has_* flags, without a macro.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_device_types.h | 2 --
drivers/gpu/drm/xe/xe_heci_gsc.c | 8 ++++----
drivers/gpu/drm/xe/xe_irq.c | 8 ++++----
3 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index ff19bda9ddadc..27a3d82560498 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -42,8 +42,6 @@ struct xe_pat_ops;
#define GRAPHICS_VERx100(xe) ((xe)->info.graphics_verx100)
#define MEDIA_VERx100(xe) ((xe)->info.media_verx100)
#define IS_DGFX(xe) ((xe)->info.is_dgfx)
-#define HAS_HECI_GSCFI(xe) ((xe)->info.has_heci_gscfi)
-#define HAS_HECI_CSCFI(xe) ((xe)->info.has_heci_cscfi)
#define XE_VRAM_FLAGS_NEED64K BIT(0)
diff --git a/drivers/gpu/drm/xe/xe_heci_gsc.c b/drivers/gpu/drm/xe/xe_heci_gsc.c
index 65b2e147c4b92..d765bfd3636b4 100644
--- a/drivers/gpu/drm/xe/xe_heci_gsc.c
+++ b/drivers/gpu/drm/xe/xe_heci_gsc.c
@@ -92,7 +92,7 @@ void xe_heci_gsc_fini(struct xe_device *xe)
{
struct xe_heci_gsc *heci_gsc = &xe->heci_gsc;
- if (!HAS_HECI_GSCFI(xe) && !HAS_HECI_CSCFI(xe))
+ if (!xe->info.has_heci_gscfi && !xe->info.has_heci_cscfi)
return;
if (heci_gsc->adev) {
@@ -177,7 +177,7 @@ void xe_heci_gsc_init(struct xe_device *xe)
const struct heci_gsc_def *def;
int ret;
- if (!HAS_HECI_GSCFI(xe) && !HAS_HECI_CSCFI(xe))
+ if (!xe->info.has_heci_gscfi && !xe->info.has_heci_cscfi)
return;
heci_gsc->irq = -1;
@@ -222,7 +222,7 @@ void xe_heci_gsc_irq_handler(struct xe_device *xe, u32 iir)
if ((iir & GSC_IRQ_INTF(1)) == 0)
return;
- if (!HAS_HECI_GSCFI(xe)) {
+ if (!xe->info.has_heci_gscfi) {
drm_warn_once(&xe->drm, "GSC irq: not supported");
return;
}
@@ -242,7 +242,7 @@ void xe_heci_csc_irq_handler(struct xe_device *xe, u32 iir)
if ((iir & CSC_IRQ_INTF(1)) == 0)
return;
- if (!HAS_HECI_CSCFI(xe)) {
+ if (!xe->info.has_heci_cscfi) {
drm_warn_once(&xe->drm, "CSC irq: not supported");
return;
}
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index b7995ebd54abd..7bf7201529ac8 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -192,7 +192,7 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
if (xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER)) {
gsc_mask = irqs | GSC_ER_COMPLETE;
heci_mask = GSC_IRQ_INTF(1);
- } else if (HAS_HECI_GSCFI(xe)) {
+ } else if (xe->info.has_heci_gscfi) {
gsc_mask = GSC_IRQ_INTF(1);
}
@@ -325,7 +325,7 @@ static void gt_irq_handler(struct xe_tile *tile,
if (class == XE_ENGINE_CLASS_OTHER) {
/* HECI GSCFI interrupts come from outside of GT */
- if (HAS_HECI_GSCFI(xe) && instance == OTHER_GSC_INSTANCE)
+ if (xe->info.has_heci_gscfi && instance == OTHER_GSC_INSTANCE)
xe_heci_gsc_irq_handler(xe, intr_vec);
else
gt_other_irq_handler(engine_gt, instance, intr_vec);
@@ -459,7 +459,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
* the primary tile.
*/
if (id == 0) {
- if (HAS_HECI_CSCFI(xe))
+ if (xe->info.has_heci_cscfi)
xe_heci_csc_irq_handler(xe, master_ctl);
xe_display_irq_handler(xe, master_ctl);
gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
@@ -508,7 +508,7 @@ static void gt_irq_reset(struct xe_tile *tile)
if ((tile->media_gt &&
xe_hw_engine_mask_per_class(tile->media_gt, XE_ENGINE_CLASS_OTHER)) ||
- HAS_HECI_GSCFI(tile_to_xe(tile))) {
+ tile_to_xe(tile)->info.has_heci_gscfi) {
xe_mmio_write32(mmio, GUNIT_GSC_INTR_ENABLE, 0);
xe_mmio_write32(mmio, GUNIT_GSC_INTR_MASK, ~0);
xe_mmio_write32(mmio, HECI2_RSVD_INTR_MASK, ~0);
--
2.47.0
next prev parent reply other threads:[~2024-11-14 15:22 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-14 15:21 [PATCH 0/4] drm/xe: Trivial header/flags cleanups Lucas De Marchi
2024-11-14 15:21 ` [PATCH 1/4] drm/xe: Sort again info flags Lucas De Marchi
2024-11-14 17:37 ` Rodrigo Vivi
2024-11-14 15:21 ` [PATCH 2/4] drm/xe: Include xe_oa_types.h Lucas De Marchi
2024-11-14 17:37 ` Rodrigo Vivi
2024-11-14 15:21 ` Lucas De Marchi [this message]
2024-11-14 17:38 ` [PATCH 3/4] drm/xe: Drop HAS_HECI_* Rodrigo Vivi
2024-11-14 15:21 ` [PATCH 4/4] drm/xe: Split xe_gt_stat.h Lucas De Marchi
2024-11-14 17:39 ` Rodrigo Vivi
2024-11-15 23:49 ` Lucas De Marchi
2024-11-14 15:51 ` ✓ CI.Patch_applied: success for drm/xe: Trivial header/flags cleanups Patchwork
2024-11-14 15:52 ` ✗ CI.checkpatch: warning " Patchwork
2024-11-14 15:53 ` ✓ CI.KUnit: success " Patchwork
2024-11-14 16:04 ` ✓ CI.Build: " Patchwork
2024-11-14 16:07 ` ✓ CI.Hooks: " Patchwork
2024-11-14 16:08 ` ✓ CI.checksparse: " Patchwork
2024-11-14 16:42 ` ✓ CI.BAT: " Patchwork
2024-11-15 8:24 ` ✗ CI.FULL: failure " Patchwork
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