Intel-XE Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: <intel-xe@lists.freedesktop.org>,
	Jani Nikula <jani.nikula@linux.intel.com>,
	Alexander Usyskin <alexander.usyskin@intel.com>,
	Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>,
	Ashutosh Dixit <ashutosh.dixit@intel.com>
Subject: Re: [PATCH 1/4] drm/xe: Sort again info flags
Date: Thu, 14 Nov 2024 12:37:03 -0500	[thread overview]
Message-ID: <ZzY1P49f-h-HCVx-@intel.com> (raw)
In-Reply-To: <20241114152148.572447-2-lucas.demarchi@intel.com>

On Thu, Nov 14, 2024 at 07:21:45AM -0800, Lucas De Marchi wrote:
> Those flags are supposed to be kept sorted alphabetically. 

It is a good thing to keep a dream alive :)

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> Unfortunately
> it's a constant battle as new flags are added to the end or at random
> places. Sort it again.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_device_types.h | 20 ++++++++++----------
>  1 file changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index fffbb7d1c40b4..2c6a2040f0d82 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -300,10 +300,18 @@ struct xe_device {
>  		u8 is_dgfx:1;
>  		/** @info.has_asid: Has address space ID */
>  		u8 has_asid:1;
> +		/** @info.has_atomic_enable_pte_bit: Device has atomic enable PTE bit */
> +		u8 has_atomic_enable_pte_bit:1;
> +		/** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */
> +		u8 has_device_atomics_on_smem:1;
>  		/** @info.force_execlist: Forced execlist submission */
>  		u8 force_execlist:1;
>  		/** @info.has_flat_ccs: Whether flat CCS metadata is used */
>  		u8 has_flat_ccs:1;
> +		/** @info.has_heci_cscfi: device has heci cscfi */
> +		u8 has_heci_cscfi:1;
> +		/** @info.has_heci_gscfi: device has heci gscfi */
> +		u8 has_heci_gscfi:1;
>  		/** @info.has_llc: Device has a shared CPU+GPU last level cache */
>  		u8 has_llc:1;
>  		/** @info.has_mmio_ext: Device has extra MMIO address range */
> @@ -323,20 +331,12 @@ struct xe_device {
>  		 * state the firmware or bootloader left it in.
>  		 */
>  		u8 probe_display:1;
> +		/** @info.skip_guc_pc: Skip GuC based PM feature init */
> +		u8 skip_guc_pc:1;
>  		/** @info.skip_mtcfg: skip Multi-Tile configuration from MTCFG register */
>  		u8 skip_mtcfg:1;
>  		/** @info.skip_pcode: skip access to PCODE uC */
>  		u8 skip_pcode:1;
> -		/** @info.has_heci_gscfi: device has heci gscfi */
> -		u8 has_heci_gscfi:1;
> -		/** @info.has_heci_cscfi: device has heci cscfi */
> -		u8 has_heci_cscfi:1;
> -		/** @info.skip_guc_pc: Skip GuC based PM feature init */
> -		u8 skip_guc_pc:1;
> -		/** @info.has_atomic_enable_pte_bit: Device has atomic enable PTE bit */
> -		u8 has_atomic_enable_pte_bit:1;
> -		/** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */
> -		u8 has_device_atomics_on_smem:1;
>  	} info;
>  
>  	/** @irq: device interrupt state */
> -- 
> 2.47.0
> 

  reply	other threads:[~2024-11-14 17:37 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-14 15:21 [PATCH 0/4] drm/xe: Trivial header/flags cleanups Lucas De Marchi
2024-11-14 15:21 ` [PATCH 1/4] drm/xe: Sort again info flags Lucas De Marchi
2024-11-14 17:37   ` Rodrigo Vivi [this message]
2024-11-14 15:21 ` [PATCH 2/4] drm/xe: Include xe_oa_types.h Lucas De Marchi
2024-11-14 17:37   ` Rodrigo Vivi
2024-11-14 15:21 ` [PATCH 3/4] drm/xe: Drop HAS_HECI_* Lucas De Marchi
2024-11-14 17:38   ` Rodrigo Vivi
2024-11-14 15:21 ` [PATCH 4/4] drm/xe: Split xe_gt_stat.h Lucas De Marchi
2024-11-14 17:39   ` Rodrigo Vivi
2024-11-15 23:49     ` Lucas De Marchi
2024-11-14 15:51 ` ✓ CI.Patch_applied: success for drm/xe: Trivial header/flags cleanups Patchwork
2024-11-14 15:52 ` ✗ CI.checkpatch: warning " Patchwork
2024-11-14 15:53 ` ✓ CI.KUnit: success " Patchwork
2024-11-14 16:04 ` ✓ CI.Build: " Patchwork
2024-11-14 16:07 ` ✓ CI.Hooks: " Patchwork
2024-11-14 16:08 ` ✓ CI.checksparse: " Patchwork
2024-11-14 16:42 ` ✓ CI.BAT: " Patchwork
2024-11-15  8:24 ` ✗ CI.FULL: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=ZzY1P49f-h-HCVx-@intel.com \
    --to=rodrigo.vivi@intel.com \
    --cc=alexander.usyskin@intel.com \
    --cc=ashutosh.dixit@intel.com \
    --cc=daniele.ceraolospurio@intel.com \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=jani.nikula@linux.intel.com \
    --cc=lucas.demarchi@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox