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From: "Jouni Högander" <jouni.hogander@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: "Jouni Högander" <jouni.hogander@intel.com>
Subject: [PATCH 08/10] drm/i915/psr: Changes for PSR2_MAN_TRK_CTL handling when DSB is in use
Date: Fri, 13 Dec 2024 08:35:26 +0200	[thread overview]
Message-ID: <20241213063528.2759659-9-jouni.hogander@intel.com> (raw)
In-Reply-To: <20241213063528.2759659-1-jouni.hogander@intel.com>

Do needed changes to handle PSR2_MAN_TRK_CTL correctly when DSB is in use:

1. Write PSR2_MAN_TRK_CTL in commit_pipe_pre_planes only when not using
   DSB.
2. Add PSR2_MAN_TRK_CTL writing into DSB commit in
   intel_atomic_dsb_finish.

Taking PSR lock over DSB commit is not needed because PSR2_MAN_TRK_CTL is now
written only by DSB.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 974c13829fe4..985d7242b102 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7111,7 +7111,8 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state,
 			intel_pipe_fastset(old_crtc_state, new_crtc_state);
 	}
 
-	intel_psr2_program_trans_man_trk_ctl(NULL, new_crtc_state);
+	if (!new_crtc_state->use_dsb)
+		intel_psr2_program_trans_man_trk_ctl(NULL, new_crtc_state);
 
 	intel_atomic_update_watermarks(state, crtc);
 }
@@ -7700,6 +7701,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 					       new_crtc_state);
 		bdw_set_pipe_misc(new_crtc_state->dsb_commit,
 				  new_crtc_state);
+		intel_psr2_program_trans_man_trk_ctl(new_crtc_state->dsb_commit,
+						     new_crtc_state);
 		intel_crtc_planes_update_arm(new_crtc_state->dsb_commit,
 					     state, crtc);
 
-- 
2.34.1


  parent reply	other threads:[~2024-12-13  6:35 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-13  6:35 [PATCH 00/10] PSR DSB support Jouni Högander
2024-12-13  6:35 ` [PATCH 01/10] drm/i915/psr: Use PSR2_MAN_TRK_CTL CFF bit only to send full update Jouni Högander
2024-12-13  6:35 ` [PATCH 02/10] drm/i915/psr: Rename psr_force_hw_tracking_exit as intel_psr_force_update Jouni Högander
2024-12-13  6:35 ` [PATCH 03/10] drm/i915/psr: Split setting sff and cff bits away from intel_psr_force_update Jouni Högander
2024-12-13  6:35 ` [PATCH 04/10] drm/i915/psr: Add register definitions for SFF_CTL and CFF_CTL registers Jouni Högander
2024-12-20  9:36   ` Ville Syrjälä
2024-12-13  6:35 ` [PATCH 05/10] drm/i915/psr: Ensure SFF/CFF bits are not written at their sample point Jouni Högander
2024-12-20  9:34   ` Ville Syrjälä
2024-12-31  9:02     ` Hogander, Jouni
2024-12-13  6:35 ` [PATCH 06/10] drm/i915/psr: Use SFF_CTL on invalidate/flush for LunarLake onwards Jouni Högander
2024-12-13  6:35 ` [PATCH 07/10] drm/i915/psr: Allow writing PSR2_MAN_TRK_CTL using DSB Jouni Högander
2024-12-13  6:35 ` Jouni Högander [this message]
2024-12-13  6:35 ` [PATCH 09/10] drm/i915/psr: Remove DSB_SKIP_WAITS_EN chicken bit Jouni Högander
2024-12-13  6:35 ` [PATCH 10/10] drm/i915/psr: Allow DSB usage when PSR is enabled Jouni Högander
2024-12-13  7:48 ` ✓ CI.Patch_applied: success for PSR DSB support Patchwork
2024-12-13  7:48 ` ✗ CI.checkpatch: warning " Patchwork
2024-12-13  7:49 ` ✓ CI.KUnit: success " Patchwork
2024-12-13  8:07 ` ✓ CI.Build: " Patchwork
2024-12-13  8:10 ` ✓ CI.Hooks: " Patchwork
2024-12-13  8:12 ` ✗ CI.checksparse: warning " Patchwork
2024-12-13  9:03 ` ✓ Xe.CI.BAT: success " Patchwork
2024-12-13 13:59 ` ✗ Xe.CI.Full: failure " Patchwork

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