From: "Jouni Högander" <jouni.hogander@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: "Jouni Högander" <jouni.hogander@intel.com>
Subject: [PATCH v3 01/10] drm/i915/psr: Use PSR2_MAN_TRK_CTL CFF bit only to send full update
Date: Thu, 9 Jan 2025 09:31:28 +0200 [thread overview]
Message-ID: <20250109073137.1977494-2-jouni.hogander@intel.com> (raw)
In-Reply-To: <20250109073137.1977494-1-jouni.hogander@intel.com>
We are preparing for a change where only frontbuffer flush will use
single full frame bit of a new register (SFF_CTL) available on LunarLake
onwards.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 0b021acb330f..476305010e11 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2381,7 +2381,6 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
val |= man_trk_ctl_partial_frame_bit_get(display);
if (full_update) {
- val |= man_trk_ctl_single_full_frame_bit_get(display);
val |= man_trk_ctl_continuos_full_frame(display);
goto exit;
}
--
2.43.0
next prev parent reply other threads:[~2025-01-09 7:32 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-09 7:31 [PATCH v3 00/10] PSR DSB support Jouni Högander
2025-01-09 7:31 ` Jouni Högander [this message]
2025-01-15 7:43 ` [PATCH v3 01/10] drm/i915/psr: Use PSR2_MAN_TRK_CTL CFF bit only to send full update Manna, Animesh
2025-01-09 7:31 ` [PATCH v3 02/10] drm/i915/psr: Rename psr_force_hw_tracking_exit as intel_psr_force_update Jouni Högander
2025-01-15 7:46 ` Manna, Animesh
2025-01-09 7:31 ` [PATCH v3 03/10] drm/i915/psr: Split setting sff and cff bits away from intel_psr_force_update Jouni Högander
2025-01-15 7:58 ` Manna, Animesh
2025-01-09 7:31 ` [PATCH v3 04/10] drm/i915/psr: Add register definitions for SFF_CTL and CFF_CTL registers Jouni Högander
2025-01-15 8:32 ` Manna, Animesh
2025-01-09 7:31 ` [PATCH v3 05/10] drm/i915/psr: Use SFF_CTL on invalidate/flush for LunarLake onwards Jouni Högander
2025-01-15 8:18 ` Manna, Animesh
2025-01-09 7:31 ` [PATCH v3 06/10] drm/i915/psr: Allow writing PSR2_MAN_TRK_CTL using DSB Jouni Högander
2025-01-16 6:03 ` Manna, Animesh
2025-01-17 19:22 ` Ville Syrjälä
2025-01-20 6:47 ` Hogander, Jouni
2025-01-09 7:31 ` [PATCH v3 07/10] drm/i915/psr: Changes for PSR2_MAN_TRK_CTL handling when DSB is in use Jouni Högander
2025-01-16 6:10 ` Manna, Animesh
2025-01-09 7:31 ` [PATCH v3 08/10] drm/i915/psr: Add intel_psr_is_psr_mode_changing Jouni Högander
2025-01-16 7:15 ` Manna, Animesh
2025-01-09 7:31 ` [PATCH v3 09/10] drm/i915/display: Don't use DSB if psr mode changing Jouni Högander
2025-01-16 7:19 ` Manna, Animesh
2025-01-09 7:31 ` [PATCH v3 10/10] drm/i915/psr: Allow DSB usage when PSR is enabled Jouni Högander
2025-01-16 7:27 ` Manna, Animesh
2025-01-17 20:20 ` Ville Syrjälä
2025-01-17 23:07 ` Ville Syrjälä
2025-01-20 7:28 ` Hogander, Jouni
2025-01-20 14:39 ` Ville Syrjälä
2025-01-20 15:27 ` Ville Syrjälä
2025-01-21 10:29 ` Hogander, Jouni
2025-01-21 13:57 ` Ville Syrjälä
2025-01-21 15:11 ` Ville Syrjälä
2025-01-22 5:53 ` Hogander, Jouni
2025-01-09 7:46 ` ✓ CI.Patch_applied: success for PSR DSB support (rev3) Patchwork
2025-01-09 7:46 ` ✓ CI.checkpatch: " Patchwork
2025-01-09 7:47 ` ✓ CI.KUnit: " Patchwork
2025-01-09 8:05 ` ✓ CI.Build: " Patchwork
2025-01-09 8:07 ` ✓ CI.Hooks: " Patchwork
2025-01-09 8:09 ` ✗ CI.checksparse: warning " Patchwork
2025-01-09 8:38 ` ✓ Xe.CI.BAT: success " Patchwork
2025-01-11 11:27 ` ✗ Xe.CI.Full: failure " Patchwork
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