From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
To: intel-xe@lists.freedesktop.org
Cc: kernel-dev@igalia.com, Tvrtko Ursulin <tvrtko.ursulin@igalia.com>,
Lucas De Marchi <lucas.demarchi@intel.com>,
Matt Roper <matthew.d.roper@intel.com>
Subject: [PATCH 4/5] drm/xe/xelp: L3 recommended hashing mask
Date: Thu, 27 Feb 2025 10:13:03 +0000 [thread overview]
Message-ID: <20250227101304.46660-5-tvrtko.ursulin@igalia.com> (raw)
In-Reply-To: <20250227101304.46660-1-tvrtko.ursulin@igalia.com>
According to the i915 codebase xe missed to set the recommended
performance tuning for L3 hashing which is applicable to all legacy XeLP
platforms. Lets add it.
v2:
* Rename prefixes to XELP_.
* Tweak version end point.
v3:
* Add bspec tag.
* Tweak version range.
v4:
* Move from LRC to engine tunings list.
Bspec: 31870
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
References: c46c5fb725be ("drm/i915/gen12: Apply recommended L3 hashing mask")
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 ++++-
drivers/gpu/drm/xe/xe_tuning.c | 5 +++++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 282afd22b68b..da833a147c0c 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -365,10 +365,13 @@
#define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4)
#define FORCEWAKE_GSC XE_REG(0xa618)
+/* L3 Cache Control */
+#define XELP_GARBCNTL XE_REG(0xb004)
+#define XELP_BUS_HASH_CTL_BIT_EXC REG_BIT(7)
+
#define XEHPC_LNCFMISCCFGREG0 XE_REG_MCR(0xb01c, XE_REG_OPTION_MASKED)
#define XEHPC_OVRLSCCC REG_BIT(0)
-/* L3 Cache Control */
#define LNCFCMOCS_REG_COUNT 32
#define XELP_LNCFCMOCS(i) XE_REG(0xb020 + (i) * 4)
#define XEHP_LNCFCMOCS(i) XE_REG_MCR(0xb020 + (i) * 4)
diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index 3c78f3d71559..551c2f308e1c 100644
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -88,6 +88,11 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
};
static const struct xe_rtp_entry_sr engine_tunings[] = {
+ { XE_RTP_NAME("Tuning: L3 Hashing Mask"),
+ XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210),
+ FUNC(xe_rtp_match_first_render_or_compute)),
+ XE_RTP_ACTIONS(CLR(XELP_GARBCNTL, XELP_BUS_HASH_CTL_BIT_EXC))
+ },
{ XE_RTP_NAME("Tuning: Set Indirect State Override"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274),
ENGINE_CLASS(RENDER)),
--
2.48.0
next prev parent reply other threads:[~2025-02-27 10:13 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-27 10:12 [PATCH v4 0/5] Workaround fixes, improvements, additions Tvrtko Ursulin
2025-02-27 10:13 ` [PATCH 1/5] drm/xe: Fix GT "for each engine" workarounds Tvrtko Ursulin
2025-02-27 10:13 ` [PATCH 2/5] drm/xe/xelp: Move Wa_16011163337 from tunings to workarounds Tvrtko Ursulin
2025-02-27 20:58 ` Lucas De Marchi
2025-02-28 8:08 ` Tvrtko Ursulin
2025-03-01 0:55 ` Lucas De Marchi
2025-02-27 10:13 ` [PATCH 3/5] drm/xe/xelp: Add Wa_1604555607 Tvrtko Ursulin
2025-02-27 21:13 ` Matt Roper
2025-02-27 21:13 ` Lucas De Marchi
2025-02-27 10:13 ` Tvrtko Ursulin [this message]
2025-02-27 21:16 ` [PATCH 4/5] drm/xe/xelp: L3 recommended hashing mask Lucas De Marchi
2025-02-27 21:21 ` Matt Roper
2025-03-01 5:48 ` Lucas De Marchi
2025-03-03 16:28 ` Tvrtko Ursulin
2025-02-27 10:13 ` [PATCH 5/5] drm/xe: Add performance tunings to debugfs Tvrtko Ursulin
2025-02-27 10:54 ` ✓ CI.Patch_applied: success for Workaround fixes, improvements, additions (rev4) Patchwork
2025-02-27 10:54 ` ✗ CI.checkpatch: warning " Patchwork
2025-02-27 10:55 ` ✓ CI.KUnit: success " Patchwork
2025-02-27 11:12 ` ✓ CI.Build: " Patchwork
2025-02-27 11:15 ` ✓ CI.Hooks: " Patchwork
2025-02-27 11:16 ` ✓ CI.checksparse: " Patchwork
2025-02-27 11:42 ` ✓ Xe.CI.BAT: " Patchwork
2025-02-27 13:52 ` ✗ Xe.CI.Full: failure " Patchwork
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