From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
To: intel-xe@lists.freedesktop.org
Cc: kernel-dev@igalia.com, Tvrtko Ursulin <tvrtko.ursulin@igalia.com>,
Matt Roper <matthew.d.roper@intel.com>
Subject: [PATCH 3/4] drm/xe: Pass flags directly to emit_flush_imm_ggtt
Date: Fri, 7 Mar 2025 11:14:01 +0000 [thread overview]
Message-ID: <20250307111402.26577-4-tvrtko.ursulin@igalia.com> (raw)
In-Reply-To: <20250307111402.26577-1-tvrtko.ursulin@igalia.com>
This is more readable than the nameless booleans and will also come handy
later.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_ring_ops.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index 3d1b4d3d788f..917fc16de866 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -90,11 +90,10 @@ static int emit_flush_dw(u32 *dw, int i)
return i;
}
-static int emit_flush_imm_ggtt(u32 addr, u32 value, bool invalidate_tlb,
- u32 *dw, int i)
+static int emit_flush_imm_ggtt(u32 addr, u32 value, u32 flags, u32 *dw, int i)
{
dw[i++] = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW |
- (invalidate_tlb ? MI_INVALIDATE_TLB : 0);
+ flags;
dw[i++] = addr | MI_FLUSH_DW_USE_GTT;
dw[i++] = 0;
dw[i++] = value;
@@ -254,7 +253,7 @@ static void __emit_job_gen12_simple(struct xe_sched_job *job, struct xe_lrc *lrc
if (job->ring_ops_flush_tlb) {
dw[i++] = preparser_disable(true);
i = emit_flush_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
- seqno, true, dw, i);
+ seqno, MI_INVALIDATE_TLB, dw, i);
dw[i++] = preparser_disable(false);
} else {
i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
@@ -270,7 +269,7 @@ static void __emit_job_gen12_simple(struct xe_sched_job *job, struct xe_lrc *lrc
dw, i);
}
- i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, false, dw, i);
+ i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, 0, dw, i);
i = emit_user_interrupt(dw, i);
@@ -316,7 +315,7 @@ static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,
if (job->ring_ops_flush_tlb)
i = emit_flush_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
- seqno, true, dw, i);
+ seqno, MI_INVALIDATE_TLB, dw, i);
dw[i++] = preparser_disable(false);
@@ -333,7 +332,7 @@ static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,
dw, i);
}
- i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, false, dw, i);
+ i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, 0, dw, i);
i = emit_user_interrupt(dw, i);
--
2.48.0
next prev parent reply other threads:[~2025-03-07 11:14 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-07 11:13 [CI 0/4] Misc reviewed patches for CI Tvrtko Ursulin
2025-03-07 11:13 ` [PATCH 1/4] drm/xe: Fix MOCS debugfs LNCF readout Tvrtko Ursulin
2025-03-07 11:14 ` [PATCH 2/4] drm/xe: Fix ring flush invalidation Tvrtko Ursulin
2025-03-07 11:14 ` Tvrtko Ursulin [this message]
2025-03-07 12:26 ` [PATCH 3/4] drm/xe: Pass flags directly to emit_flush_imm_ggtt Upadhyay, Tejas
2025-03-07 11:14 ` [PATCH 4/4] drm/xe: Use correct type width for alignment in fb pinning code Tvrtko Ursulin
2025-03-07 12:02 ` ✓ CI.Patch_applied: success for Misc reviewed patches for CI Patchwork
2025-03-07 12:03 ` ✓ CI.checkpatch: " Patchwork
2025-03-07 12:04 ` ✓ CI.KUnit: " Patchwork
2025-03-07 12:21 ` ✓ CI.Build: " Patchwork
2025-03-07 12:23 ` ✓ CI.Hooks: " Patchwork
2025-03-07 12:24 ` ✓ CI.checksparse: " Patchwork
2025-03-07 12:46 ` ✓ Xe.CI.BAT: " Patchwork
2025-03-08 6:06 ` ✗ Xe.CI.Full: failure " Patchwork
2025-03-10 15:51 ` [CI 0/4] " Rodrigo Vivi
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