From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
To: intel-xe@lists.freedesktop.org
Cc: kernel-dev@igalia.com, Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Subject: [PATCH v5 01/16] drm/xe: Adjust ringbuf emission for maximum possible size
Date: Thu, 3 Apr 2025 20:03:01 +0100 [thread overview]
Message-ID: <20250403190317.6064-2-tvrtko.ursulin@igalia.com> (raw)
In-Reply-To: <20250403190317.6064-1-tvrtko.ursulin@igalia.com>
MAX_JOB_SIZE_DW seems to be undersized. For the worst case emission from
__emit_job_gen12_render_compute I hand count 57 dwords so lets bump this
to an even 58.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
---
drivers/gpu/drm/xe/xe_ring_ops_types.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_ring_ops_types.h b/drivers/gpu/drm/xe/xe_ring_ops_types.h
index 1ae56e2ee7b4..d7e3e150a9a5 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops_types.h
+++ b/drivers/gpu/drm/xe/xe_ring_ops_types.h
@@ -8,7 +8,7 @@
struct xe_sched_job;
-#define MAX_JOB_SIZE_DW 48
+#define MAX_JOB_SIZE_DW 58
#define MAX_JOB_SIZE_BYTES (MAX_JOB_SIZE_DW * 4)
/**
--
2.48.0
next prev parent reply other threads:[~2025-04-03 19:03 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-03 19:03 [PATCH v5 00/16] AuxCCS handling and render compression modifiers Tvrtko Ursulin
2025-04-03 19:03 ` Tvrtko Ursulin [this message]
2025-04-15 11:59 ` [PATCH v5 01/16] drm/xe: Adjust ringbuf emission for maximum possible size Francois Dugast
2025-04-15 12:40 ` Tvrtko Ursulin
2025-04-15 14:21 ` Lucas De Marchi
2025-04-03 19:03 ` [PATCH v5 02/16] drm/xe: Use emit_flush_imm_ggtt helper instead of open coding Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 03/16] drm/xe/xelpg: Flush CCS when flushing caches Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 04/16] drm/xe: Flush L3 when flushing render cache Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 05/16] drm/xe/xelp: Quiesce memory traffic before invalidating auxccs Tvrtko Ursulin
2025-04-04 15:44 ` Ville Syrjälä
2025-04-03 19:03 ` [PATCH v5 06/16] drm/xe/xelp: Support auxccs invalidation on blitter Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 07/16] drm/xe/xelp: Use MI_FLUSH_DW_CCS on auxccs platforms Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 08/16] drm/xe/xelp: Wait for AuxCCS invalidation to complete Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 09/16] drm/xe/xelp: Add AuxCCS invalidation to the buffer migration path Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 10/16] drm/xe: Use fb cached min alignment Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 11/16] drm/xe: Reduce DPT table alignment as in i915 Tvrtko Ursulin
2025-04-04 15:52 ` Ville Syrjälä
2025-04-03 19:03 ` [PATCH v5 12/16] drm/xe: Flush GGTT writes after populating DPT Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 13/16] drm/xe: Handle DPT in system memory Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 14/16] drm/xe: Force flush system memory AuxCCS framebuffers before scan out Tvrtko Ursulin
2025-04-04 16:20 ` Ville Syrjälä
2025-04-14 9:44 ` Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 15/16] drm/xe/display: Add support for AuxCCS Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 16/16] drm/i915/display: Expose AuxCCS frame buffer modifiers for Xe Tvrtko Ursulin
2025-04-04 2:19 ` ✓ CI.Patch_applied: success for AuxCCS handling and render compression modifiers (rev5) Patchwork
2025-04-04 2:19 ` ✗ CI.checkpatch: warning " Patchwork
2025-04-04 2:21 ` ✓ CI.KUnit: success " Patchwork
2025-04-04 2:37 ` ✓ CI.Build: " Patchwork
2025-04-04 2:40 ` ✓ CI.Hooks: " Patchwork
2025-04-04 2:41 ` ✓ CI.checksparse: " Patchwork
2025-04-04 3:27 ` ✓ Xe.CI.BAT: " Patchwork
2025-04-04 12:03 ` ✗ Xe.CI.Full: failure " Patchwork
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