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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Cc: intel-xe@lists.freedesktop.org, kernel-dev@igalia.com
Subject: Re: [PATCH v5 05/16] drm/xe/xelp: Quiesce memory traffic before invalidating auxccs
Date: Fri, 4 Apr 2025 18:44:56 +0300	[thread overview]
Message-ID: <Z-_-ePLbnbZOALEN@intel.com> (raw)
In-Reply-To: <20250403190317.6064-6-tvrtko.ursulin@igalia.com>

On Thu, Apr 03, 2025 at 08:03:05PM +0100, Tvrtko Ursulin wrote:
> According to i915 before invalidating auxccs we must quiesce the memory
> traffic by an extra flush.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> ---
>  drivers/gpu/drm/xe/xe_ring_ops.c       | 14 ++++++++++----
>  drivers/gpu/drm/xe/xe_ring_ops_types.h |  2 +-
>  2 files changed, 11 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
> index 61295f93ffb7..3f075dd36c86 100644
> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> @@ -172,7 +172,8 @@ static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,
>  	return i;
>  }
>  
> -static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
> +static int emit_render_cache_flush(struct xe_sched_job *job, bool flush_l3,
> +				   u32 *dw, int i)
>  {
>  	struct xe_gt *gt = job->q->gt;
>  	struct xe_device *xe = gt_to_xe(gt);
> @@ -204,7 +205,7 @@ static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
>  	 * deals with Protected Memory which is not needed for
>  	 * AUX CCS invalidation and lead to unwanted side effects.
>  	 */
> -	if (GRAPHICS_VERx100(xe) < 1270)
> +	if (flush_l3 && GRAPHICS_VERx100(xe) < 1270)
>  		flags |= PIPE_CONTROL_FLUSH_L3;
>  
>  	if (lacks_render)
> @@ -370,10 +371,15 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
>  	struct xe_gt *gt = job->q->gt;
>  	struct xe_device *xe = gt_to_xe(gt);
>  	bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK);
> +	const bool aux_ccs = has_aux_ccs(xe);
>  	u32 mask_flags = 0;
>  
>  	i = emit_copy_timestamp(lrc, dw, i);
>  
> +	/* hsdes: 1809175790 */
> +	if (aux_ccs)
> +		i = emit_render_cache_flush(job, 0, dw, i);

s/0/false/

> +
>  	dw[i++] = preparser_disable(true);
>  	if (lacks_render)
>  		mask_flags = PIPE_CONTROL_3D_ARCH_FLAGS;
> @@ -384,7 +390,7 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
>  	i = emit_pipe_invalidate(mask_flags, job->ring_ops_flush_tlb, dw, i);
>  
>  	/* hsdes: 1809175790 */
> -	if (has_aux_ccs(xe))
> +	if (aux_ccs)
>  		i = emit_aux_table_inv(gt, CCS_AUX_INV, dw, i);
>  
>  	dw[i++] = preparser_disable(false);
> @@ -394,7 +400,7 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
>  
>  	i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
>  
> -	i = emit_render_cache_flush(job, dw, i);
> +	i = emit_render_cache_flush(job, true, dw, i);
>  
>  	if (job->user_fence.used)
>  		i = emit_store_imm_ppgtt_posted(job->user_fence.addr,
> diff --git a/drivers/gpu/drm/xe/xe_ring_ops_types.h b/drivers/gpu/drm/xe/xe_ring_ops_types.h
> index d7e3e150a9a5..477dc7defd72 100644
> --- a/drivers/gpu/drm/xe/xe_ring_ops_types.h
> +++ b/drivers/gpu/drm/xe/xe_ring_ops_types.h
> @@ -8,7 +8,7 @@
>  
>  struct xe_sched_job;
>  
> -#define MAX_JOB_SIZE_DW 58
> +#define MAX_JOB_SIZE_DW 70
>  #define MAX_JOB_SIZE_BYTES (MAX_JOB_SIZE_DW * 4)
>  
>  /**
> -- 
> 2.48.0

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2025-04-04 15:45 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-03 19:03 [PATCH v5 00/16] AuxCCS handling and render compression modifiers Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 01/16] drm/xe: Adjust ringbuf emission for maximum possible size Tvrtko Ursulin
2025-04-15 11:59   ` Francois Dugast
2025-04-15 12:40     ` Tvrtko Ursulin
2025-04-15 14:21       ` Lucas De Marchi
2025-04-03 19:03 ` [PATCH v5 02/16] drm/xe: Use emit_flush_imm_ggtt helper instead of open coding Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 03/16] drm/xe/xelpg: Flush CCS when flushing caches Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 04/16] drm/xe: Flush L3 when flushing render cache Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 05/16] drm/xe/xelp: Quiesce memory traffic before invalidating auxccs Tvrtko Ursulin
2025-04-04 15:44   ` Ville Syrjälä [this message]
2025-04-03 19:03 ` [PATCH v5 06/16] drm/xe/xelp: Support auxccs invalidation on blitter Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 07/16] drm/xe/xelp: Use MI_FLUSH_DW_CCS on auxccs platforms Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 08/16] drm/xe/xelp: Wait for AuxCCS invalidation to complete Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 09/16] drm/xe/xelp: Add AuxCCS invalidation to the buffer migration path Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 10/16] drm/xe: Use fb cached min alignment Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 11/16] drm/xe: Reduce DPT table alignment as in i915 Tvrtko Ursulin
2025-04-04 15:52   ` Ville Syrjälä
2025-04-03 19:03 ` [PATCH v5 12/16] drm/xe: Flush GGTT writes after populating DPT Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 13/16] drm/xe: Handle DPT in system memory Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 14/16] drm/xe: Force flush system memory AuxCCS framebuffers before scan out Tvrtko Ursulin
2025-04-04 16:20   ` Ville Syrjälä
2025-04-14  9:44     ` Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 15/16] drm/xe/display: Add support for AuxCCS Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 16/16] drm/i915/display: Expose AuxCCS frame buffer modifiers for Xe Tvrtko Ursulin
2025-04-04  2:19 ` ✓ CI.Patch_applied: success for AuxCCS handling and render compression modifiers (rev5) Patchwork
2025-04-04  2:19 ` ✗ CI.checkpatch: warning " Patchwork
2025-04-04  2:21 ` ✓ CI.KUnit: success " Patchwork
2025-04-04  2:37 ` ✓ CI.Build: " Patchwork
2025-04-04  2:40 ` ✓ CI.Hooks: " Patchwork
2025-04-04  2:41 ` ✓ CI.checksparse: " Patchwork
2025-04-04  3:27 ` ✓ Xe.CI.BAT: " Patchwork
2025-04-04 12:03 ` ✗ Xe.CI.Full: failure " Patchwork

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