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From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
To: intel-xe@lists.freedesktop.org
Cc: kernel-dev@igalia.com, Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Subject: [PATCH v5 08/16] drm/xe/xelp: Wait for AuxCCS invalidation to complete
Date: Thu,  3 Apr 2025 20:03:08 +0100	[thread overview]
Message-ID: <20250403190317.6064-9-tvrtko.ursulin@igalia.com> (raw)
In-Reply-To: <20250403190317.6064-1-tvrtko.ursulin@igalia.com>

On AuxCCS platforms we need to wait for AuxCCS invalidations to complete.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
---
 drivers/gpu/drm/xe/instructions/xe_mi_commands.h | 6 ++++++
 drivers/gpu/drm/xe/xe_ring_ops.c                 | 9 ++++++++-
 drivers/gpu/drm/xe/xe_ring_ops_types.h           | 2 +-
 3 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
index eba582058d55..ae62a8b83265 100644
--- a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
+++ b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
@@ -76,4 +76,10 @@
 #define MI_SET_APPID_SESSION_ID_MASK	REG_GENMASK(6, 0)
 #define MI_SET_APPID_SESSION_ID(x)	REG_FIELD_PREP(MI_SET_APPID_SESSION_ID_MASK, x)
 
+#define MI_SEMAPHORE_WAIT_TOKEN		(__MI_INSTR(0x1c) | XE_INSTR_NUM_DW(3)) /* XeLP+ */
+#define   MI_SEMAPHORE_REGISTER_POLL	REG_BIT(16)
+#define   MI_SEMAPHORE_POLL		REG_BIT(15)
+#define   MI_SEMAPHORE_CMP_OP_MASK	REG_GENMASK(14, 12)
+#define   MI_SEMAPHORE_SAD_EQ_SDD	REG_FIELD_PREP(MI_SEMAPHORE_CMP_OP_MASK, 4)
+
 #endif
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index 7509c41dee97..62e62f0c6787 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -56,7 +56,14 @@ static int emit_aux_table_inv(struct xe_gt *gt, struct xe_reg reg,
 	dw[i++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1) | MI_LRI_MMIO_REMAP_EN;
 	dw[i++] = reg.addr + gt->mmio.adj_offset;
 	dw[i++] = AUX_INV;
-	dw[i++] = MI_NOOP;
+	dw[i++] = MI_SEMAPHORE_WAIT_TOKEN |
+		  MI_SEMAPHORE_REGISTER_POLL |
+		  MI_SEMAPHORE_POLL |
+		  MI_SEMAPHORE_SAD_EQ_SDD;
+	dw[i++] = 0;
+	dw[i++] = reg.addr + gt->mmio.adj_offset;
+	dw[i++] = 0;
+	dw[i++] = 0;
 
 	return i;
 }
diff --git a/drivers/gpu/drm/xe/xe_ring_ops_types.h b/drivers/gpu/drm/xe/xe_ring_ops_types.h
index 477dc7defd72..1197fc0bf2af 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops_types.h
+++ b/drivers/gpu/drm/xe/xe_ring_ops_types.h
@@ -8,7 +8,7 @@
 
 struct xe_sched_job;
 
-#define MAX_JOB_SIZE_DW 70
+#define MAX_JOB_SIZE_DW 74
 #define MAX_JOB_SIZE_BYTES (MAX_JOB_SIZE_DW * 4)
 
 /**
-- 
2.48.0


  parent reply	other threads:[~2025-04-03 19:03 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-03 19:03 [PATCH v5 00/16] AuxCCS handling and render compression modifiers Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 01/16] drm/xe: Adjust ringbuf emission for maximum possible size Tvrtko Ursulin
2025-04-15 11:59   ` Francois Dugast
2025-04-15 12:40     ` Tvrtko Ursulin
2025-04-15 14:21       ` Lucas De Marchi
2025-04-03 19:03 ` [PATCH v5 02/16] drm/xe: Use emit_flush_imm_ggtt helper instead of open coding Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 03/16] drm/xe/xelpg: Flush CCS when flushing caches Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 04/16] drm/xe: Flush L3 when flushing render cache Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 05/16] drm/xe/xelp: Quiesce memory traffic before invalidating auxccs Tvrtko Ursulin
2025-04-04 15:44   ` Ville Syrjälä
2025-04-03 19:03 ` [PATCH v5 06/16] drm/xe/xelp: Support auxccs invalidation on blitter Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 07/16] drm/xe/xelp: Use MI_FLUSH_DW_CCS on auxccs platforms Tvrtko Ursulin
2025-04-03 19:03 ` Tvrtko Ursulin [this message]
2025-04-03 19:03 ` [PATCH v5 09/16] drm/xe/xelp: Add AuxCCS invalidation to the buffer migration path Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 10/16] drm/xe: Use fb cached min alignment Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 11/16] drm/xe: Reduce DPT table alignment as in i915 Tvrtko Ursulin
2025-04-04 15:52   ` Ville Syrjälä
2025-04-03 19:03 ` [PATCH v5 12/16] drm/xe: Flush GGTT writes after populating DPT Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 13/16] drm/xe: Handle DPT in system memory Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 14/16] drm/xe: Force flush system memory AuxCCS framebuffers before scan out Tvrtko Ursulin
2025-04-04 16:20   ` Ville Syrjälä
2025-04-14  9:44     ` Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 15/16] drm/xe/display: Add support for AuxCCS Tvrtko Ursulin
2025-04-03 19:03 ` [PATCH v5 16/16] drm/i915/display: Expose AuxCCS frame buffer modifiers for Xe Tvrtko Ursulin
2025-04-04  2:19 ` ✓ CI.Patch_applied: success for AuxCCS handling and render compression modifiers (rev5) Patchwork
2025-04-04  2:19 ` ✗ CI.checkpatch: warning " Patchwork
2025-04-04  2:21 ` ✓ CI.KUnit: success " Patchwork
2025-04-04  2:37 ` ✓ CI.Build: " Patchwork
2025-04-04  2:40 ` ✓ CI.Hooks: " Patchwork
2025-04-04  2:41 ` ✓ CI.checksparse: " Patchwork
2025-04-04  3:27 ` ✓ Xe.CI.BAT: " Patchwork
2025-04-04 12:03 ` ✗ Xe.CI.Full: failure " Patchwork

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