From: "Jouni Högander" <jouni.hogander@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
Cc: "Jouni Högander" <jouni.hogander@intel.com>,
"Ankit Nautiyal" <ankit.k.nautiyal@intel.com>
Subject: [PATCH v4 09/12] drm/i915/display: Add PHY_CMN1_CONTROL register definitions
Date: Wed, 21 May 2025 14:53:16 +0300 [thread overview]
Message-ID: <20250521115319.2380655-10-jouni.hogander@intel.com> (raw)
In-Reply-To: <20250521115319.2380655-1-jouni.hogander@intel.com>
Add PHY_CMN1_CONTROL register and its definitions to configure port LFPS
sending.
Bspec: 68962
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 59c22beaf1de..580a43be195e 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -285,6 +285,9 @@
#define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control))
#define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6)
+#define PHY_CMN1_CONTROL(tx, control) (0x800 + ((tx) - 1) * 0x200 + (control))
+#define CONTROL0_MAC_TRANSMIT_LFPS REG_BIT(1)
+
/* C20 Registers */
#define PHY_C20_WR_ADDRESS_L 0xC02
#define PHY_C20_WR_ADDRESS_H 0xC03
--
2.43.0
next prev parent reply other threads:[~2025-05-21 11:54 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-21 11:53 [PATCH v4 00/12] Panel Replay + Adaptive sync Jouni Högander
2025-05-21 11:53 ` [PATCH v4 01/12] drm/panelreplay: Panel Replay capability DPCD register definitions Jouni Högander
2025-05-21 11:53 ` [PATCH v4 02/12] drm/dp: Add Panel Replay capability bits from DP2.1 specification Jouni Högander
2025-05-21 12:16 ` Nautiyal, Ankit K
2025-05-21 11:53 ` [PATCH v4 03/12] drm/i915/psr: Read all Panel Replay capability registers from DPCD Jouni Högander
2025-05-21 11:53 ` [PATCH v4 04/12] drm/i915/alpm: Add PR_ALPM_CTL register definitions Jouni Högander
2025-05-21 11:53 ` [PATCH v4 05/12] drm/i915/alpm: Write PR_ALPM_CTL register Jouni Högander
2025-05-21 11:53 ` [PATCH v4 06/12] drm/i915/psr: Add interface to check if AUXLess ALPM is needed by PSR Jouni Högander
2025-05-21 11:53 ` [PATCH v4 07/12] drm/i915/alpm: Add new interface to check if AUXLess ALPM is used Jouni Högander
2025-05-21 11:53 ` [PATCH v4 08/12] drm/i915/alpm: Move port alpm configuration Jouni Högander
2025-05-21 11:53 ` Jouni Högander [this message]
2025-05-21 11:53 ` [PATCH v4 10/12] drm/i915/display: Add function to configure LFPS sending Jouni Högander
2025-05-21 11:53 ` [PATCH v4 11/12] drm/i915/psr: Fix using wrong mask in REG_FIELD_PREP Jouni Högander
2025-05-21 11:53 ` [PATCH v4 12/12] drm/i915/psr: Do not disable Panel Replay in case VRR is enabled Jouni Högander
2025-05-22 5:25 ` [PATCH v4 00/12] Panel Replay + Adaptive sync Hogander, Jouni
2025-05-26 11:43 ` Maarten Lankhorst
2025-05-29 5:33 ` Hogander, Jouni
-- strict thread matches above, loose matches on Subject: below --
2025-05-26 12:05 Jouni Högander
2025-05-26 12:05 ` [PATCH v4 09/12] drm/i915/display: Add PHY_CMN1_CONTROL register definitions Jouni Högander
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