From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
Cc: chaitanya.kumar.borah@intel.com, ville.syrjala@linux.intel.com,
pekka.paalanen@collabora.com, contact@emersion.fr,
harry.wentland@amd.com, mwen@igalia.com, jadahl@redhat.com,
sebastian.wick@redhat.com, shashank.sharma@amd.com,
swati2.sharma@intel.com, alex.hung@amd.com,
Uma Shankar <uma.shankar@intel.com>
Subject: [v5 04/24] drm: Add 1D LUT multi-segmented color op
Date: Wed, 2 Jul 2025 14:49:16 +0530 [thread overview]
Message-ID: <20250702091936.3004854-5-uma.shankar@intel.com> (raw)
In-Reply-To: <20250702091936.3004854-1-uma.shankar@intel.com>
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Add support for color ops that can be programmed
by 1 dimensional multi segmented Look Up Tables.
v2: Fixed the documentation for Multi segmented lut (Dmitry)
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/drm_atomic.c | 4 ++++
drivers/gpu/drm/drm_atomic_uapi.c | 3 +++
drivers/gpu/drm/drm_colorop.c | 1 +
include/uapi/drm/drm_mode.h | 10 ++++++++++
4 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 3ab32fe7fe1c..71160a71f5a3 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -800,6 +800,10 @@ static void drm_atomic_colorop_print_state(struct drm_printer *p,
drm_get_colorop_lut1d_interpolation_name(colorop->lut1d_interpolation));
drm_printf(p, "\tdata blob id=%d\n", state->data ? state->data->base.id : 0);
break;
+ case DRM_COLOROP_1D_LUT_MULTSEG:
+ drm_printf(p, "\thw cap blob id=%d\n", state->hw_caps ? state->hw_caps->base.id : 0);
+ drm_printf(p, "\tdata blob id=%d\n", state->data ? state->data->base.id : 0);
+ break;
case DRM_COLOROP_CTM_3X4:
drm_printf(p, "\tdata blob id=%d\n", state->data ? state->data->base.id : 0);
break;
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c
index 81a8da09fbfe..c59f6671b73d 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -723,6 +723,9 @@ static int drm_atomic_color_set_data_property(struct drm_colorop *colorop,
size = colorop->lut_size * colorop->lut_size * colorop->lut_size *
sizeof(struct drm_color_lut_32);
break;
+ case DRM_COLOROP_1D_LUT_MULTSEG:
+ elem_size = sizeof(struct drm_color_lut_32);
+ break;
default:
/* should never get here */
return -EINVAL;
diff --git a/drivers/gpu/drm/drm_colorop.c b/drivers/gpu/drm/drm_colorop.c
index 52c08d717944..97e9acbb0f2c 100644
--- a/drivers/gpu/drm/drm_colorop.c
+++ b/drivers/gpu/drm/drm_colorop.c
@@ -65,6 +65,7 @@
static const struct drm_prop_enum_list drm_colorop_type_enum_list[] = {
{ DRM_COLOROP_1D_CURVE, "1D Curve" },
{ DRM_COLOROP_1D_LUT, "1D LUT" },
+ { DRM_COLOROP_1D_LUT_MULTSEG, "1D LUT Multi Segmented" },
{ DRM_COLOROP_CTM_3X4, "3x4 Matrix"},
{ DRM_COLOROP_MULTIPLIER, "Multiplier"},
{ DRM_COLOROP_3D_LUT, "3D LUT"},
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index dd223077f4e9..18e36cbe10f7 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -915,6 +915,16 @@ enum drm_colorop_type {
*/
DRM_COLOROP_1D_LUT,
+ /**
+ * @DRM_COLOROP_1D_LUT_MULTSEG:
+ *
+ * A 1D LUT with multiple segments to cover the full color range with non-uniformly
+ * distributed &drm_color_lut entries, packed into a blob via the DATA property.
+ * The driver's expected LUT size and segmented capabilities are advertised via the
+ * HW_CAPS property.
+ */
+ DRM_COLOROP_1D_LUT_MULTSEG,
+
/**
* @DRM_COLOROP_CTM_3X4:
*
--
2.42.0
next prev parent reply other threads:[~2025-07-02 9:07 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-02 9:19 [v5 00/24] Plane Color Pipeline support for Intel platforms Uma Shankar
2025-07-02 9:19 ` [v5 01/24] [NOT FOR REVIEW] drm: AMD series squashed Uma Shankar
2025-07-02 9:19 ` [v5 02/24] drm: Add Color lut range attributes Uma Shankar
2025-10-23 5:25 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 03/24] drm: Add Color ops capability property Uma Shankar
2025-10-28 5:31 ` Kandpal, Suraj
2025-07-02 9:19 ` Uma Shankar [this message]
2025-10-23 8:11 ` [v5 04/24] drm: Add 1D LUT multi-segmented color op Kandpal, Suraj
2025-07-02 9:19 ` [v5 05/24] drm: Define helper to initialize segmented 1D LUT Uma Shankar
2025-10-23 8:27 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 06/24] drm: Add helper to extract lut from struct drm_color_lut_32 Uma Shankar
2025-10-24 4:29 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 07/24] drm/i915: Add identifiers for intel color blocks Uma Shankar
2025-07-04 12:35 ` Jani Nikula
2025-10-23 6:04 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 08/24] drm/i915: Add intel_color_op Uma Shankar
2025-07-04 12:36 ` Jani Nikula
2025-11-05 12:24 ` Borah, Chaitanya Kumar
2025-07-02 9:19 ` [v5 09/24] drm/i915/color: Add helper to create intel colorop Uma Shankar
2025-07-04 12:37 ` Jani Nikula
2025-10-27 9:38 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 10/24] drm/i915/color: Create a transfer function color pipeline Uma Shankar
2025-07-04 12:39 ` Jani Nikula
2025-10-28 4:59 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 11/24] drm/i915/color: Add and attach COLORPIPELINE plane property Uma Shankar
2025-07-04 12:41 ` Jani Nikula
2025-10-28 5:13 ` Kandpal, Suraj
2025-11-05 12:25 ` Borah, Chaitanya Kumar
2025-07-02 9:19 ` [v5 12/24] drm/i915/color: Add framework to program CSC Uma Shankar
2025-10-28 8:09 ` Kandpal, Suraj
2025-10-28 8:12 ` Kandpal, Suraj
2025-11-05 12:25 ` Borah, Chaitanya Kumar
2025-11-05 12:25 ` Borah, Chaitanya Kumar
2025-07-02 9:19 ` [v5 13/24] drm/i915/color: Add callbacks to set plane CTM Uma Shankar
2025-07-04 12:42 ` Jani Nikula
2025-07-02 9:19 ` [v5 14/24] drm/i915/color: Add new color callbacks for Xelpd Uma Shankar
2025-07-02 9:19 ` [v5 15/24] drm/i915/color: Preserve sign bit when int_bits is Zero Uma Shankar
2025-07-02 9:19 ` [v5 16/24] drm/i915/color: Add plane CTM callback for D13 and beyond Uma Shankar
2025-10-28 8:16 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 17/24] drm/i915: Add register definitions for Plane Degamma Uma Shankar
2025-10-23 6:22 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 18/24] drm/i915/color: Add framework to program PRE/POST CSC LUT Uma Shankar
2025-07-02 9:19 ` [v5 19/24] drm/i915: Add register definitions for Plane Post CSC Uma Shankar
2025-10-23 6:25 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 20/24] drm/i915/color: Program Pre-CSC registers Uma Shankar
2025-10-23 6:28 ` Kandpal, Suraj
2025-11-05 12:26 ` Borah, Chaitanya Kumar
2025-10-28 8:25 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 21/24] drm/i915/xelpd: Program Plane Post CSC Registers Uma Shankar
2025-10-28 8:29 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 22/24] drm/i915/color: Enable Plane Color Pipelines Uma Shankar
2025-07-02 9:19 ` [v5 23/24] drm/i915/color: Create color pipeline with multisegmented LUT Uma Shankar
2025-10-28 8:31 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 24/24] drm/doc/rfc: Add documentation for multi-segmented 1D LUT Uma Shankar
2025-07-02 10:24 ` ✗ CI.checkpatch: warning for Plane Color Pipeline support for Intel platforms (rev4) Patchwork
2025-07-02 10:25 ` ✓ CI.KUnit: success " Patchwork
2025-07-02 10:40 ` ✗ CI.checksparse: warning " Patchwork
2025-07-02 11:07 ` ✓ Xe.CI.BAT: success " Patchwork
2025-07-04 2:05 ` ✗ Xe.CI.Full: failure " Patchwork
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