From: "Borah, Chaitanya Kumar" <chaitanya.kumar.borah@intel.com>
To: "Kandpal, Suraj" <suraj.kandpal@intel.com>,
"Shankar, Uma" <uma.shankar@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>,
"dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>
Cc: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>,
"pekka.paalanen@collabora.com" <pekka.paalanen@collabora.com>,
"contact@emersion.fr" <contact@emersion.fr>,
"harry.wentland@amd.com" <harry.wentland@amd.com>,
"mwen@igalia.com" <mwen@igalia.com>,
"jadahl@redhat.com" <jadahl@redhat.com>,
"sebastian.wick@redhat.com" <sebastian.wick@redhat.com>,
"shashank.sharma@amd.com" <shashank.sharma@amd.com>,
"Sharma, Swati2" <swati2.sharma@intel.com>,
"alex.hung@amd.com" <alex.hung@amd.com>
Subject: Re: [v5 12/24] drm/i915/color: Add framework to program CSC
Date: Wed, 5 Nov 2025 17:55:19 +0530 [thread overview]
Message-ID: <87b85c18-64e9-408a-ac6c-40ebe01a0407@intel.com> (raw)
In-Reply-To: <DM3PPF208195D8D2955A727287B465E3434E3FDA@DM3PPF208195D8D.namprd11.prod.outlook.com>
On 10/28/2025 1:42 PM, Kandpal, Suraj wrote:
>
>
>> -----Original Message-----
>> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of
>> Kandpal, Suraj
>> Sent: Tuesday, October 28, 2025 1:40 PM
>> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
>> intel-xe@lists.freedesktop.org; dri-devel@lists.freedesktop.org
>> Cc: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>;
>> ville.syrjala@linux.intel.com; pekka.paalanen@collabora.com;
>> contact@emersion.fr; harry.wentland@amd.com; mwen@igalia.com;
>> jadahl@redhat.com; sebastian.wick@redhat.com;
>> shashank.sharma@amd.com; Sharma, Swati2 <swati2.sharma@intel.com>;
>> alex.hung@amd.com; Shankar, Uma <uma.shankar@intel.com>
>> Subject: RE: [v5 12/24] drm/i915/color: Add framework to program CSC
>>
>>> Subject: [v5 12/24] drm/i915/color: Add framework to program CSC
>>>
>>> From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
>>>
>>> Add framework to program CSC. It enables copying of matrix from uapi
>>> to intel plane state. Also adding helper functions which will
>>> eventually program values to hardware.
>>>
>>> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
>>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_color.c | 14 +++++++
>>> drivers/gpu/drm/i915/display/intel_color.h | 4 +-
>>> .../drm/i915/display/intel_display_types.h | 1 +
>>> drivers/gpu/drm/i915/display/intel_plane.c | 39 +++++++++++++++++++
>>> 4 files changed, 57 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
>>> b/drivers/gpu/drm/i915/display/intel_color.c
>>> index 363c9590c5c1..7c53572f729b 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_color.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_color.c
>>> @@ -3967,6 +3967,20 @@ static const struct intel_color_funcs
>>> ilk_color_funcs = { };
>>>
>>> /* TODO: Move to another file */
>>> +static void
>>> +intel_color_load_plane_csc_matrix(struct intel_dsb *dsb,
>>> + const struct intel_plane_state *plane_state)
>>> {
>>> + /* CTM programming */
>>
>> Add TODO
>>
>>> +}
>>> +
>>> +void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
>>> + const struct intel_plane_state
>>> *plane_state) {
>>> + if (plane_state->hw.ctm)
>>> + intel_color_load_plane_csc_matrix(dsb, plane_state); }
>>> +
>
> Also the functions above introduced seem to be out of place introduce them later where they are used.
>
The idea here is to get the plumbing in first and then enable the
interface later on.
==
Chaitanya
> Regards,
> Suraj Kandpal
>
>>> struct intel_plane_colorop *intel_colorop_alloc(void) {
>>> struct intel_plane_colorop *colorop; diff --git
>>> a/drivers/gpu/drm/i915/display/intel_color.h
>>> b/drivers/gpu/drm/i915/display/intel_color.h
>>> index c2561b86bb26..420d596dbbae 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_color.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_color.h
>>> @@ -13,6 +13,7 @@ struct intel_crtc_state; struct intel_crtc; struct
>>> intel_display; struct intel_dsb;
>>> +struct intel_plane_state;
>>> struct drm_property_blob;
>>> struct drm_plane;
>>> struct drm_prop_enum_list;
>>> @@ -49,5 +50,6 @@ struct intel_plane_colorop
>>> *intel_colorop_alloc(void); struct intel_plane_colorop
>>> *intel_plane_colorop_create(enum intel_color_block id); int
>>> intel_plane_tf_pipeline_init(struct drm_plane *plane, struct
>>> drm_prop_enum_list *list); int intel_plane_color_init(struct
>>> drm_plane *plane);
>>> -
>>> +void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
>>> + const struct intel_plane_state
>>> *plane_state);
>>> #endif /* __INTEL_COLOR_H__ */
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
>>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> index 4b5124a08cc9..c709df0cea9e 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> @@ -634,6 +634,7 @@ struct intel_plane_state {
>>> enum drm_color_encoding color_encoding;
>>> enum drm_color_range color_range;
>>> enum drm_scaling_filter scaling_filter;
>>> + struct drm_property_blob *ctm;
>>> } hw;
>>>
>>> struct i915_vma *ggtt_vma;
>>> diff --git a/drivers/gpu/drm/i915/display/intel_plane.c
>>> b/drivers/gpu/drm/i915/display/intel_plane.c
>>> index 36fb07471deb..cc8f3e15c82e 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_plane.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_plane.c
>>> @@ -380,6 +380,43 @@ intel_plane_copy_uapi_plane_damage(struct
>>> intel_plane_state *new_plane_state,
>>> *damage = drm_plane_state_src(&new_uapi_plane_state-
>>>> uapi);
>>> }
>>>
>>> +static void
>>> +intel_plane_colorop_replace_blob(struct intel_plane_state *plane_state,
>>> + struct intel_plane_colorop *intel_colorop,
>>> + struct drm_property_blob *blob)
>>> +{
>>> + if (intel_colorop->id == CB_PLANE_CSC)
>>> + drm_property_replace_blob(&plane_state->hw.ctm, blob); }
>>> +
>>> +static void
>>> +intel_plane_copy_uapi_to_hw_state_color(struct intel_plane_state
>>
>> This should be intel_plane_color_copy_uapi_to_hw_state
>>
>>> *plane_state,
>>> + const struct intel_plane_state
>>> *from_plane_state,
>>> + struct intel_crtc *crtc)
>>> +{
>>> + struct drm_colorop *iter_colorop, *colorop;
>>> + struct drm_colorop_state *new_colorop_state;
>>> + struct drm_atomic_state *state = plane_state->uapi.state;
>>> + struct intel_plane_colorop *intel_colorop;
>>> + struct drm_property_blob *blob;
>>> + int i = 0;
>>> +
>>> + iter_colorop = plane_state->uapi.color_pipeline;
>>> +
>>> + while (iter_colorop) {
>>> + for_each_new_colorop_in_state(state, colorop,
>>> new_colorop_state, i) {
>>> + if (new_colorop_state->colorop == iter_colorop) {
>>> + blob = new_colorop_state->bypass ? NULL :
>>> new_colorop_state->data;
>>> + intel_colorop =
>>> to_intel_plane_colorop(colorop);
>>> +
>>> intel_plane_colorop_replace_blob(plane_state,
>>> +
>>> intel_colorop,
>>> + blob);
>>
>> A break here why keep iterating if you have found what you are looking for I
>> think I am seeing more and more reason to have a separate file as Jani had
>> said Called intel_plane_color.c
>>
>> Regards,
>> Suraj Kandpal
>>> + }
>>> + }
>>> + iter_colorop = iter_colorop->next;
>>> + }
>>> +}
>>> +
>>> void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state
>>> *plane_state,
>>> const struct intel_plane_state
>> *from_plane_state,
>>> struct intel_crtc *crtc)
>>> @@ -408,6 +445,8 @@ void intel_plane_copy_uapi_to_hw_state(struct
>>> intel_plane_state *plane_state,
>>>
>>> plane_state->uapi.src = drm_plane_state_src(&from_plane_state-
>>>> uapi);
>>> plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state-
>>>> uapi);
>>> +
>>> + intel_plane_copy_uapi_to_hw_state_color(plane_state,
>>> from_plane_state,
>>> +crtc);
>>> }
>>>
>>> void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
>>> --
>>> 2.42.0
>
next prev parent reply other threads:[~2025-11-05 12:25 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-02 9:19 [v5 00/24] Plane Color Pipeline support for Intel platforms Uma Shankar
2025-07-02 9:19 ` [v5 01/24] [NOT FOR REVIEW] drm: AMD series squashed Uma Shankar
2025-07-02 9:19 ` [v5 02/24] drm: Add Color lut range attributes Uma Shankar
2025-10-23 5:25 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 03/24] drm: Add Color ops capability property Uma Shankar
2025-10-28 5:31 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 04/24] drm: Add 1D LUT multi-segmented color op Uma Shankar
2025-10-23 8:11 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 05/24] drm: Define helper to initialize segmented 1D LUT Uma Shankar
2025-10-23 8:27 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 06/24] drm: Add helper to extract lut from struct drm_color_lut_32 Uma Shankar
2025-10-24 4:29 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 07/24] drm/i915: Add identifiers for intel color blocks Uma Shankar
2025-07-04 12:35 ` Jani Nikula
2025-10-23 6:04 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 08/24] drm/i915: Add intel_color_op Uma Shankar
2025-07-04 12:36 ` Jani Nikula
2025-11-05 12:24 ` Borah, Chaitanya Kumar
2025-07-02 9:19 ` [v5 09/24] drm/i915/color: Add helper to create intel colorop Uma Shankar
2025-07-04 12:37 ` Jani Nikula
2025-10-27 9:38 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 10/24] drm/i915/color: Create a transfer function color pipeline Uma Shankar
2025-07-04 12:39 ` Jani Nikula
2025-10-28 4:59 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 11/24] drm/i915/color: Add and attach COLORPIPELINE plane property Uma Shankar
2025-07-04 12:41 ` Jani Nikula
2025-10-28 5:13 ` Kandpal, Suraj
2025-11-05 12:25 ` Borah, Chaitanya Kumar
2025-07-02 9:19 ` [v5 12/24] drm/i915/color: Add framework to program CSC Uma Shankar
2025-10-28 8:09 ` Kandpal, Suraj
2025-10-28 8:12 ` Kandpal, Suraj
2025-11-05 12:25 ` Borah, Chaitanya Kumar [this message]
2025-11-05 12:25 ` Borah, Chaitanya Kumar
2025-07-02 9:19 ` [v5 13/24] drm/i915/color: Add callbacks to set plane CTM Uma Shankar
2025-07-04 12:42 ` Jani Nikula
2025-07-02 9:19 ` [v5 14/24] drm/i915/color: Add new color callbacks for Xelpd Uma Shankar
2025-07-02 9:19 ` [v5 15/24] drm/i915/color: Preserve sign bit when int_bits is Zero Uma Shankar
2025-07-02 9:19 ` [v5 16/24] drm/i915/color: Add plane CTM callback for D13 and beyond Uma Shankar
2025-10-28 8:16 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 17/24] drm/i915: Add register definitions for Plane Degamma Uma Shankar
2025-10-23 6:22 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 18/24] drm/i915/color: Add framework to program PRE/POST CSC LUT Uma Shankar
2025-07-02 9:19 ` [v5 19/24] drm/i915: Add register definitions for Plane Post CSC Uma Shankar
2025-10-23 6:25 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 20/24] drm/i915/color: Program Pre-CSC registers Uma Shankar
2025-10-23 6:28 ` Kandpal, Suraj
2025-11-05 12:26 ` Borah, Chaitanya Kumar
2025-10-28 8:25 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 21/24] drm/i915/xelpd: Program Plane Post CSC Registers Uma Shankar
2025-10-28 8:29 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 22/24] drm/i915/color: Enable Plane Color Pipelines Uma Shankar
2025-07-02 9:19 ` [v5 23/24] drm/i915/color: Create color pipeline with multisegmented LUT Uma Shankar
2025-10-28 8:31 ` Kandpal, Suraj
2025-07-02 9:19 ` [v5 24/24] drm/doc/rfc: Add documentation for multi-segmented 1D LUT Uma Shankar
2025-07-02 10:24 ` ✗ CI.checkpatch: warning for Plane Color Pipeline support for Intel platforms (rev4) Patchwork
2025-07-02 10:25 ` ✓ CI.KUnit: success " Patchwork
2025-07-02 10:40 ` ✗ CI.checksparse: warning " Patchwork
2025-07-02 11:07 ` ✓ Xe.CI.BAT: success " Patchwork
2025-07-04 2:05 ` ✗ Xe.CI.Full: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87b85c18-64e9-408a-ac6c-40ebe01a0407@intel.com \
--to=chaitanya.kumar.borah@intel.com \
--cc=alex.hung@amd.com \
--cc=contact@emersion.fr \
--cc=dri-devel@lists.freedesktop.org \
--cc=harry.wentland@amd.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=intel-xe@lists.freedesktop.org \
--cc=jadahl@redhat.com \
--cc=mwen@igalia.com \
--cc=pekka.paalanen@collabora.com \
--cc=sebastian.wick@redhat.com \
--cc=shashank.sharma@amd.com \
--cc=suraj.kandpal@intel.com \
--cc=swati2.sharma@intel.com \
--cc=uma.shankar@intel.com \
--cc=ville.syrjala@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox