Re: [v5 20/24] drm/i915/color: Program Pre-CSC registers

["Borah, Chaitanya Kumar" <chaitanya.kumar.borah@intel.com>]

On 10/23/2025 11:58 AM, Kandpal, Suraj wrote:
>> Subject: [v5 20/24] drm/i915/color: Program Pre-CSC registers
>>
>> From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
>>
>> Add callback for programming Pre-CSC LUT for TGL and beyond
> 
> Do you mean ADL and beyond.
> Also "Add callback to program ....."

Thanks for pointing it out. We actually intended it from TGL+.
I will make the changes to reflect that.

==
Chaitanya

> 
> Regards,
> Suraj Kandpal
> 
>>
>> v2: Add DSB support
>> v3: Add support for single segment 1D LUT color op
>>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_color.c | 104 +++++++++++++++++++++
>>   1 file changed, 104 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
>> b/drivers/gpu/drm/i915/display/intel_color.c
>> index c7378af8fbdf..75981fe232bf 100644
>> --- a/drivers/gpu/drm/i915/display/intel_color.c
>> +++ b/drivers/gpu/drm/i915/display/intel_color.c
>> @@ -3945,6 +3945,109 @@ xelpd_load_plane_csc_matrix(struct intel_dsb
>> *dsb,
>>   			   ctm_to_twos_complement(input[11], 0, 12));  }
>>
>> +static void
>> +xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
>> +				const struct intel_plane_state *plane_state) {
>> +	struct intel_display *display = to_intel_display(plane_state);
>> +	const struct drm_plane_state *state = &plane_state->uapi;
>> +	enum pipe pipe = to_intel_plane(state->plane)->pipe;
>> +	enum plane_id plane = to_intel_plane(state->plane)->id;
>> +	const struct drm_color_lut_32 *pre_csc_lut = plane_state-
>>> hw.degamma_lut->data;
>> +	u32 i, lut_size;
>> +	bool is_single_seg = drm_color_lut_32_size(plane_state-
>>> hw.degamma_lut) == 128 ?
>> +			     true : false;
>> +
>> +	if (icl_is_hdr_plane(display, plane)) {
>> +		lut_size = 128;
>> +
>> +		intel_de_write_dsb(display, dsb,
>> +				   PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe,
>> plane, 0),
>> +				   PLANE_PAL_PREC_AUTO_INCREMENT);
>> +
>> +		if (pre_csc_lut) {
>> +			for (i = 0; i < lut_size; i++) {
>> +				u32 lut_val = is_single_seg ?
>> +
>> drm_color_lut_32_extract(pre_csc_lut[i].green, 24) :
>> +					  (pre_csc_lut[i].green & 0xffffff);
>> +
>> +				intel_de_write_dsb(display, dsb,
>> +
>> PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
>> +						   lut_val);
>> +			}
>> +
>> +			/* Program the max register to clamp values > 1.0. */
>> +			/* ToDo: Restrict to 0x7ffffff*/
>> +			do {
>> +				intel_de_write_dsb(display, dsb,
>> +
>> PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
>> +						   is_single_seg ? (1 << 24) :
>> +						   pre_csc_lut[i].green);
>> +			} while (i++ > 130);
>> +		} else {
>> +			for (i = 0; i < lut_size; i++) {
>> +				u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
>> +
>> +				intel_de_write_dsb(display, dsb,
>> +
>> PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), v);
>> +			}
>> +
>> +			do {
>> +				intel_de_write_dsb(display, dsb,
>> +
>> PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
>> +						   1 << 24);
>> +			} while (i++ < 130);
>> +		}
>> +
>> +		intel_de_write_dsb(display, dsb,
>> PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);
>> +	} else {
>> +		lut_size = 32;
>> +
>> +		/*
>> +		 * First 3 planes are HDR, so reduce by 3 to get to the right
>> +		 * SDR plane offset
>> +		 */
>> +		plane = plane - 3;
>> +
>> +		intel_de_write_dsb(display, dsb,
>> PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, 0),
>> +				   PLANE_PAL_PREC_AUTO_INCREMENT);
>> +
>> +		if (pre_csc_lut) {
>> +			for (i = 0; i < lut_size; i++)
>> +				intel_de_write_dsb(display, dsb,
>> +
>> PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0),
>> +						   pre_csc_lut[i].green);
>> +			/* Program the max register to clamp values > 1.0. */
>> +			while (i < 35)
>> +				intel_de_write_dsb(display, dsb,
>> +
>> PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0),
>> +						   pre_csc_lut[i++].green);
>> +		} else {
>> +			for (i = 0; i < lut_size; i++) {
>> +				u32 v = (i * ((1 << 16) - 1)) / (lut_size - 1);
>> +
>> +				intel_de_write_dsb(display, dsb,
>> +
>> PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0), v);
>> +			}
>> +
>> +			do {
>> +				intel_de_write_dsb(display, dsb,
>> +
>> PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0),
>> +						   1 << 16);
>> +			} while (i++ < 34);
>> +		}
>> +
>> +		intel_de_write_dsb(display, dsb,
>> PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, 0), 0);
>> +	}
>> +}
>> +
>> +static void
>> +xelpd_plane_load_luts(struct intel_dsb *dsb, const struct
>> +intel_plane_state *plane_state) {
>> +	if (plane_state->hw.degamma_lut)
>> +		xelpd_program_plane_pre_csc_lut(dsb, plane_state); }
>> +
>>   static const struct intel_color_funcs chv_color_funcs = {
>>   	.color_check = chv_color_check,
>>   	.color_commit_arm = i9xx_color_commit_arm, @@ -4004,6 +4107,7
>> @@ static const struct intel_color_funcs xelpd_color_funcs = {
>>   	.read_csc = icl_read_csc,
>>   	.get_config = skl_get_config,
>>   	.load_plane_csc_matrix = xelpd_load_plane_csc_matrix,
>> +	.load_plane_luts = xelpd_plane_load_luts,
>>   };
>>
>>   static const struct intel_color_funcs icl_color_funcs = {
>> --
>> 2.42.0
>